Search found 18 matches

by Shelton
Fri Mar 10, 2017 2:06 pm
Forum: Introduction
Topic: Hey!
Replies: 0
Views: 1527

Hey!

Hello all! My name is Shelton, and "leggo" was an old nickname of mine based on my initials (though I am also fond of Eggo waffles ;)). So I have finally bitten the bait, and signed up for an account. I first discovered this forum back in the spring, when I was awaiting my results from the structura...
by Shelton
Wed Mar 08, 2017 6:38 am
Forum: FPGa Projects
Topic: 4DSP development kit + Stellar IP tool
Replies: 0
Views: 1423

4DSP development kit + Stellar IP tool

Dear all,

Can any body here help me in some things regarding 4DSP product. and Stellar IP software.
I am using in one of my project and need some assistance in some area.

If any one has experience of using this please let me know. I want to inquire something about STAR communication issue.
by Shelton
Wed Mar 08, 2017 6:33 am
Forum: FPGa Projects
Topic: Xilinx Old school software "XACT" or "ViewLogic4"
Replies: 1
Views: 1555

Xilinx Old school software "XACT" or "ViewLogic4"

Hey Folks, I've run into a snag here.... I dug out the old school Xilinx "Xact" software boxes from storage, and I even found the hardware Dongle which was what I was most concerned about finding in order to revive this old software that came out in the early 90's. Just looking to mess around with t...
by Shelton
Wed Mar 08, 2017 6:31 am
Forum: FPGa Projects
Topic: VME controller configuration in FPGA
Replies: 0
Views: 1237

VME controller configuration in FPGA

Friends,

I would like to configure VME controller in Vertex-6 FPGA. please share ur ideas to implement it.
by Shelton
Wed Mar 08, 2017 6:30 am
Forum: FPGa Projects
Topic: FPGA based Modulation and Demodulation
Replies: 6
Views: 1626

FPGA based Modulation and Demodulation

hello friends... please guide me how to go about this project "fpga based mod/demod". i'll be using a spartan 3 fpga kit. and my modulation technique will be 'binary amplitude shift keying'. what i intend in doing is ... i have two kits ...in one i'll be giving my message signal as input(now that me...
by Shelton
Wed Mar 08, 2017 6:26 am
Forum: FPGa Projects
Topic: Loading .rbf file into EPCS16 for remote configuration of FPGA.
Replies: 0
Views: 1239

Loading .rbf file into EPCS16 for remote configuration of FPGA.

Hi all, I am dealing with .rbf file, generated by Quartus II. I want to write the contents of rbf file into the EPCS flash using SPI interface. But the problem is that the .rbf file is encrypted and so I can't access the data though it. (Having rbf file loaded in flash, the FPGA can configure remote...
by Shelton
Wed Mar 08, 2017 6:22 am
Forum: FPGa Projects
Topic: In FIFO how Read / Write Pointer Functionality Happens ?
Replies: 0
Views: 1180

In FIFO how Read / Write Pointer Functionality Happens ?

Hi every 1 here i have some doubts on FIFO read and write. please any1 knows tel me. In FIFO how Read / Write Pointer Functionality Happens ? in the following cases ? 1. when fifo is in almost full and almost empty condition ? 2. when fifo is in full and empty ? 3. when fifo , program threshold valu...
by Shelton
Wed Mar 08, 2017 6:15 am
Forum: FPGa Projects
Topic: In system memory editor of Altera for Xilinx
Replies: 0
Views: 1208

In system memory editor of Altera for Xilinx

Hi!, I have been working with Altera FPGAs for a long time and now I have to deal with Xilinx ones. Until now, with Quartus II I have been able to manage the content of different registers and memories with 'In system memory editor' and I would like to do the same with Xilinx. I cannot find the righ...
by Shelton
Wed Mar 08, 2017 6:13 am
Forum: FPGa Projects
Topic: .txt file to xilinx FPGA
Replies: 0
Views: 1199

.txt file to xilinx FPGA

HI everyone.
i need to get an input (column of bits) from .txt file via usb into xilinx FPGA.
so if anyone can help me i will be grateful.

and thanks in advance.
by Shelton
Wed Mar 08, 2017 6:12 am
Forum: FPGa Projects
Topic: verilog code of sin wave generation
Replies: 0
Views: 1206

verilog code of sin wave generation

i need verilog code of sine wave generator........i tried with cordic algorithm but i cant able to proceed