Search found 18 matches

by Shelton
Wed Mar 08, 2017 6:11 am
Forum: FPGa Projects
Topic: Doubt regarding using ODIN II tool for converting a verilog file into BLIF format
Replies: 0
Views: 1068

Doubt regarding using ODIN II tool for converting a verilog file into BLIF format

I am an M.tech student and have been working on a project related to FPGA architecture research.In this, among other things i am supposed to convert verilog files into BLIF format as a part of technology mapping.While some files are getting neatly converted,some files do not.I dont understand why. B...
by Shelton
Wed Mar 08, 2017 6:10 am
Forum: FPGa Projects
Topic: 128 data to show on LCD 32hex of spartan 3E
Replies: 0
Views: 853

128 data to show on LCD 32hex of spartan 3E

can anyone please help. i am trying to make a verilog code for 128bit data to show on LCD of spartan 3E.
but its just showing first line means 64 bits
its a part of my project i am working on it from last 8 hours but... please help
by Shelton
Wed Mar 08, 2017 6:08 am
Forum: FPGa Projects
Topic: problem in vhdl test bench cod
Replies: 0
Views: 966

problem in vhdl test bench cod

hello, Why the following testbench code in the first clock d1, d2 are value And the second clock a, b library IEEE; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; use IEEE.MATH_REAL.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_TEXTIO.ALL; library ...
by Shelton
Wed Mar 08, 2017 6:07 am
Forum: FPGa Projects
Topic: Zynq 7000 board required
Replies: 0
Views: 904

Zynq 7000 board required

Guyz,

Any one with zed board(zynq 7000 based) do give a reply. Trying to get this board for my research.
Thanks in advance.
by Shelton
Wed Mar 08, 2017 6:05 am
Forum: FPGa Projects
Topic: Digital Timer
Replies: 0
Views: 1026

Digital Timer

Can anyone here give me the verilog code for a digital timer which includes a counter , finite state machine and display?
by Shelton
Wed Mar 08, 2017 6:03 am
Forum: FPGa Projects
Topic: Sending an Image file into an FPGA!
Replies: 0
Views: 1082

Sending an Image file into an FPGA!

Hello guys, I am completely new with the device. I attempting to implement an image processing algorithm onto an fpga. I am trying to do this by explicitly writing a verilog code for the algorithm that I have designed. It requires me to filter an image first row wise and then column wise. But, I am ...
by Shelton
Wed Mar 08, 2017 5:59 am
Forum: FPGa Projects
Topic: Real data type increment by fraction in VHDL
Replies: 0
Views: 968

Real data type increment by fraction in VHDL

Hi,

I am trying to increment real data by 0.03 in LOOP.Not able to see exact values.

angle <= angle + 0.03;

when angle is real data type.

in simulation I am seeing 0.02999999,0.059999999998,0.0899999999997,0.12.... .....


Thanks
by Shelton
Mon Feb 20, 2017 9:16 am
Forum: Proteus Projects
Topic: Virual Terminal In Proteus
Replies: 1
Views: 976

Virual Terminal In Proteus

Hi everyone
I want to use Virtual Terminal in proteus and send or receive data from my μC(atmega16).
I can send data from μC and receive it with the virtual terminal, but I dont know how to use this terminal to send data to μC..:confused:
how to set this as a sender.