FPGA LVDS-receiver input capacitance

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Vernie
Posts: 33
Joined: Mon Feb 20, 2017 9:19 am

FPGA LVDS-receiver input capacitance

Post by Vernie » Wed Mar 08, 2017 6:51 am

Hello,

I am currently designing a LVDS standard interface to drive a Virtex-6 FPGA with 1.25Gbps (DDR) and I would like to know if the corresponding values for the input capacitance of the LVDS-pins in the data-sheet or IBIS-file are valid? With a normal LVDS interface (I=3.5 mA and Rd=100 Ohm) it is to my mind not possible to drive 6-8pF single-ended input capacitance at 1.25Gbps. What do I misunderstand, because the data-sheet says that it is possible to drive the Virtex-6 at 1.25Gbps with a standard LVDS driver? Are the values right?

I´m grateful for any help regarding this topic.....

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