The 47 registers of MCAN0 (Controller Area Network), from 0x40030000, with their reset value and every field. The ATSAME70J21B has 2388 registers in 54 peripherals, one page each.
MCAN0 Controller Area Network
MCAN_CRELCore Release Register
Address
0x40030000
Reset
0x00000000
Access
read only
Size
32-bit
6 fields
Field
Bits
What it does
STEP
27:24
Step of Core Release
SUBSTEP
23:20
Sub-step of Core Release
YEAR
19:16
Timestamp Year
MON
15:8
Timestamp Month
DAY
7:0
Timestamp Day
REL
31:28
Core Release
MCAN_ENDNEndian Register
Address
0x40030004
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
ETV
31:0
Endianness Test Value
MCAN_CUSTCustomer Register
Address
0x40030008
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CSV
31:0
Customer-specific Value
MCAN_DBTPData Bit Timing and Prescaler Register
Address
0x4003000C
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
TDC
23
Transmitter Delay Compensation
0 Transmitter Delay Compensation disabled.
1 Transmitter Delay Compensation enabled.
DBRP
20:16
Data Bit Rate Prescaler
DTSEG1
12:8
Data Time Segment Before Sample Point
DTSEG2
7:4
Data Time Segment After Sample Point
DSJW
2:0
Data (Re) Synchronization Jump Width
MCAN_TESTTest Register
Address
0x40030010
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
RX
7
Receive Pin (read-only)
TX
6:5
Control of Transmit Pin (read/write)
0 Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time.
1 Sample Point can be monitored at pin CANTX.
2 Dominant ('0') level at pin CANTX.
3 Recessive ('1') at pin CANTX.
LBCK
4
Loop Back Mode (read/write)
0 Reset value. Loop Back mode is disabled.
1 Loop Back mode is enabled (see Section 6.1.9).
MCAN_RWDRAM Watchdog Register
Address
0x40030014
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
WDV
15:8
Watchdog Value (read-only)
WDC
7:0
Watchdog Configuration (read/write)
MCAN_CCCRCC Control Register
Address
0x40030018
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
NISO
15
Non-ISO Operation
TXP
14
Transmit Pause (read/write, write protection)
EFBI
13
Edge Filtering during Bus Integration (read/write, write protection)
0 Automatic retransmission of messages not transmitted successfully enabled.
1 Automatic retransmission disabled.
MON
5
Bus Monitoring Mode (read/write, write protection against '1')
0 Bus Monitoring mode is disabled.
1 Bus Monitoring mode is enabled.
CSR
4
Clock Stop Request (read/write)
0 No clock stop is requested.
1 Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle.
CSA
3
Clock Stop Acknowledge (read-only)
ASM
2
Restricted Operation Mode (read/write, write protection against '1')
0 The processor has no write access to the protected configuration registers.
1 The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1').
INIT
0
Initialization (read/write)
0 Normal operation.
1 Initialization is started.
MCAN_NBTPNominal Bit Timing and Prescaler Register
Address
0x4003001C
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
NBRP
24:16
Nominal Bit Rate Prescaler
NTSEG1
15:8
Nominal Time Segment Before Sample Point
NTSEG2
6:0
Nominal Time Segment After Sample Point
NSJW
31:25
Nominal (Re) Synchronization Jump Width
MCAN_TSCCTimestamp Counter Configuration Register
Address
0x40030020
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
TCP
19:16
Timestamp Counter Prescaler
TSS
1:0
Timestamp Select
0 Timestamp counter value always 0x0000
1 Timestamp counter value incremented according to TCP
2 External timestamp counter value used
MCAN_TSCVTimestamp Counter Value Register
Address
0x40030024
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TSC
15:0
Timestamp Counter (cleared on write)
MCAN_TOCCTimeout Counter Configuration Register
Address
0x40030028
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
TOS
2:1
Timeout Select
0 Continuous operation
1 Timeout controlled by Tx Event FIFO
2 Timeout controlled by Receive FIFO 0
3 Timeout controlled by Receive FIFO 1
ETOC
0
Enable Timeout Counter
0 Timeout Counter disabled.
1 Timeout Counter enabled.
TOP
31:16
Timeout Period
MCAN_TOCVTimeout Counter Value Register
Address
0x4003002C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TOC
15:0
Timeout Counter (cleared on write)
MCAN_ECRError Counter Register
Address
0x40030040
Reset
0x00000000
Access
read only
Size
32-bit
4 fields
Field
Bits
What it does
CEL
23:16
CAN Error Logging (cleared on read)
RP
15
Receive Error Passive
REC
14:8
Receive Error Counter
TEC
7:0
Transmit Error Counter
MCAN_PSRProtocol Status Register
Address
0x40030044
Reset
0x00000000
Access
read only
Size
32-bit
11 fields
Field
Bits
What it does
TDCV
22:16
Transmitter Delay Compensation Value
PXE
14
Protocol Exception Event (cleared on read)
RFDF
13
Received a CAN FD Message (cleared on read)
RBRS
12
BRS Flag of Last Received CAN FD Message (cleared on read)
RESI
11
ESI Flag of Last Received CAN FD Message (cleared on read)
DLEC
10:8
Data Phase Last Error Code (set to 111 on read)
BO
7
Bus_Off Status
EW
6
Warning Status
EP
5
Error Passive
ACT
4:3
Activity
0 Node is synchronizing on CAN communication
1 Node is neither receiver nor transmitter
2 Node is operating as receiver
3 Node is operating as transmitter
LEC
2:0
Last Error Code (set to 111 on read)
0 No error occurred since LEC has been reset by successful reception or transmission.
1 More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.
2 A fixed format part of a received frame has the wrong format.
3 The message transmitted by the MCAN was not acknowledged by another node.
4 During transmission of a message (with the exception of the arbitration field), the device tried to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant.
5 During transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device tried to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery, this status is set each time a sequence of 11 reces
6 The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match the CRC calculated from the received data.
7 Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register.
MCAN_TDCRTransmit Delay Compensation Register
Address
0x40030048
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
TDCO
14:8
Transmitter Delay Compensation Offset
TDCF
6:0
Transmitter Delay Compensation Filter
MCAN_IRInterrupt Register
Address
0x40030050
Reset
0x00000000
Access
read/write
Size
32-bit
28 fields
Field
Bits
What it does
ARA
29
Access to Reserved Address
PED
28
Protocol Error in Data Phase
PEA
27
Protocol Error in Arbitration Phase
WDI
26
Watchdog Interrupt
BO
25
Bus_Off Status
EW
24
Warning Status
EP
23
Error Passive
ELO
22
Error Logging Overflow
DRX
19
Message stored to Dedicated Receive Buffer
TOO
18
Timeout Occurred
MRAF
17
Message RAM Access Failure
TSW
16
Timestamp Wraparound
TEFL
15
Tx Event FIFO Element Lost
TEFF
14
Tx Event FIFO Full
TEFW
13
Tx Event FIFO Watermark Reached
TEFN
12
Tx Event FIFO New Entry
TFE
11
Tx FIFO Empty
TCF
10
Transmission Cancellation Finished
TC
9
Transmission Completed
HPM
8
High Priority Message
RF1L
7
Receive FIFO 1 Message Lost
RF1F
6
Receive FIFO 1 Full
RF1W
5
Receive FIFO 1 Watermark Reached
RF1N
4
Receive FIFO 1 New Message
RF0L
3
Receive FIFO 0 Message Lost
RF0F
2
Receive FIFO 0 Full
RF0W
1
Receive FIFO 0 Watermark Reached
RF0N
0
Receive FIFO 0 New Message
MCAN_IEInterrupt Enable Register
Address
0x40030054
Reset
0x00000000
Access
read/write
Size
32-bit
28 fields
Field
Bits
What it does
ARAE
29
Access to Reserved Address Enable
PEDE
28
Protocol Error in Data Phase Enable
PEAE
27
Protocol Error in Arbitration Phase Enable
WDIE
26
Watchdog Interrupt Enable
BOE
25
Bus_Off Status Interrupt Enable
EWE
24
Warning Status Interrupt Enable
EPE
23
Error Passive Interrupt Enable
ELOE
22
Error Logging Overflow Interrupt Enable
DRXE
19
Message stored to Dedicated Receive Buffer Interrupt Enable