ATSAME70N21B QSPI registers

The 16 registers of QSPI (Quad Serial Peripheral Interface), from 0x4007C000, with their reset value and every field. The ATSAME70N21B has 2806 registers in 62 peripherals, one page each.

QSPI Quad Serial Peripheral Interface

QSPI_CRControl Register

Address
0x4007C000
Reset
0x00000000
Access
write only
Size
32-bit
4 fields
FieldBitsWhat it does
LASTXFER24Last Transfer
SWRST7QSPI Software Reset
QSPIDIS1QSPI Disable
QSPIEN0QSPI Enable

QSPI_MRMode Register

Address
0x4007C004
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
DLYBCT23:16Delay Between Consecutive Transfers
NBBITS11:8Number Of Bits Per Transfer
  • 0 8 bits for transfer
  • 8 16 bits for transfer
CSMODE5:4Chip Select Mode
  • 0 The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer.
  • 1 The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred.
  • 2 The chip select is deasserted systematically after each transfer.
WDRBT2Wait Data Read Before Transfer
  • 0 No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is.
  • 1 In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception.
LLB1Local Loopback Enable
  • 0 Local loopback path disabled.
  • 1 Local loopback path enabled.
SMM0Serial Memory Mode
  • 0 The QSPI is in SPI mode.
  • 1 The QSPI is in Serial Memory mode.
DLYCS31:24Minimum Inactive QCS Delay

QSPI_RDRReceive Data Register

Address
0x4007C008
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
RD15:0Receive Data

QSPI_TDRTransmit Data Register

Address
0x4007C00C
Reset
0x00000000
Access
write only
Size
32-bit
1 field
FieldBitsWhat it does
TD15:0Transmit Data

QSPI_SRStatus Register

Address
0x4007C010
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
FieldBitsWhat it does
QSPIENS24QSPI Enable Status
INSTRE10Instruction End Status (cleared on read)
CSS9Chip Select Status
CSR8Chip Select Rise (cleared on read)
OVRES3Overrun Error Status (cleared on read)
TXEMPTY2Transmission Registers Empty (cleared by writing SPI_TDR)
TDRE1Transmit Data Register Empty (cleared by writing SPI_TDR)
RDRF0Receive Data Register Full (cleared by reading SPI_RDR)

QSPI_IERInterrupt Enable Register

Address
0x4007C014
Reset
0x00000000
Access
write only
Size
32-bit
7 fields
FieldBitsWhat it does
INSTRE10Instruction End Interrupt Enable
CSS9Chip Select Status Interrupt Enable
CSR8Chip Select Rise Interrupt Enable
OVRES3Overrun Error Interrupt Enable
TXEMPTY2Transmission Registers Empty Enable
TDRE1Transmit Data Register Empty Interrupt Enable
RDRF0Receive Data Register Full Interrupt Enable

QSPI_IDRInterrupt Disable Register

Address
0x4007C018
Reset
0x00000000
Access
write only
Size
32-bit
7 fields
FieldBitsWhat it does
INSTRE10Instruction End Interrupt Disable
CSS9Chip Select Status Interrupt Disable
CSR8Chip Select Rise Interrupt Disable
OVRES3Overrun Error Interrupt Disable
TXEMPTY2Transmission Registers Empty Disable
TDRE1Transmit Data Register Empty Interrupt Disable
RDRF0Receive Data Register Full Interrupt Disable

QSPI_IMRInterrupt Mask Register

Address
0x4007C01C
Reset
0x00000000
Access
read only
Size
32-bit
7 fields
FieldBitsWhat it does
INSTRE10Instruction End Interrupt Mask
CSS9Chip Select Status Interrupt Mask
CSR8Chip Select Rise Interrupt Mask
OVRES3Overrun Error Interrupt Mask
TXEMPTY2Transmission Registers Empty Mask
TDRE1Transmit Data Register Empty Interrupt Mask
RDRF0Receive Data Register Full Interrupt Mask

QSPI_SCRSerial Clock Register

Address
0x4007C020
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
DLYBS23:16Delay Before QSCK
SCBR15:8Serial Clock Baud Rate
CPHA1Clock Phase
CPOL0Clock Polarity

QSPI_IARInstruction Address Register

Address
0x4007C030
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADDR31:0Address

QSPI_ICRInstruction Code Register

Address
0x4007C034
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
OPT23:16Option Code
INST7:0Instruction Code

QSPI_IFRInstruction Frame Register

Address
0x4007C038
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
FieldBitsWhat it does
NBDUM20:16Number Of Dummy Cycles
CRM14Continuous Read Mode
  • 0 The Continuous Read mode is disabled.
  • 1 The Continuous Read mode is enabled.
TFRTYP13:12Data Transfer Type
  • 0 Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible.
  • 1 Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible.
  • 2 Write transfer into the serial memory.Scrambling is not performed.
  • 3 Write data transfer into the serial memory.If enabled, scrambling is performed.
ADDRL10Address Length
  • 0 The address is 24 bits long.
  • 1 The address is 32 bits long.
OPTL9:8Option Code Length
  • 0 The option code is 1 bit long.
  • 1 The option code is 2 bits long.
  • 2 The option code is 4 bits long.
  • 3 The option code is 8 bits long.
DATAEN7Data Enable
OPTEN6Option Enable
ADDREN5Address Enable
INSTEN4Instruction Enable
WIDTH2:0Width of Instruction Code, Address, Option Code and Data
  • 0 Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI
  • 1 Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI
  • 2 Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI
  • 3 Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI
  • 4 Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI
  • 5 Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI
  • 6 Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI

QSPI_SMRScrambling Mode Register

Address
0x4007C040
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
RVDIS1Scrambling/Unscrambling Random Value Disable
SCREN0Scrambling/Unscrambling Enable
  • 0 The scrambling/unscrambling is disabled.
  • 1 The scrambling/unscrambling is enabled.

QSPI_SKRScrambling Key Register

Address
0x4007C044
Reset
0x00000000
Access
write only
Size
32-bit
1 field
FieldBitsWhat it does
USRK31:0User Scrambling Key

QSPI_WPMRWrite Protection Mode Register

Address
0x4007C0E4
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
WPEN0Write Protection Enable
WPKEY31:8Write Protection Key
  • 5329744 Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

QSPI_WPSRWrite Protection Status Register

Address
0x4007C0E8
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
WPVSRC15:8Write Protection Violation Source
WPVS0Write Protection Violation Status