ATSAME70Q20B I2SC0 registers

The 10 registers of I2SC0 (Inter-IC Sound Controller), from 0x4008C000, with their reset value and every field. The ATSAME70Q20B has 2961 registers in 67 peripherals, one page each.

I2SC0 Inter-IC Sound Controller

I2SC_CRControl Register

Address
0x4008C000
Reset
0x00000000
Access
write only
Size
32-bit
7 fields
FieldBitsWhat it does
SWRST7Software Reset
TXDIS5Transmitter Disable
TXEN4Transmitter Enable
CKDIS3Clocks Disable
CKEN2Clocks Enable
RXDIS1Receiver Disable
RXEN0Receiver Enable

I2SC_MRMode Register

Address
0x4008C004
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
IMCKMODE30Master Clock Mode
IMCKFS29:24Master Clock to fs Ratio
  • 0 Sample frequency ratio set to 32
  • 1 Sample frequency ratio set to 64
  • 2 Sample frequency ratio set to 96
  • 3 Sample frequency ratio set to 128
  • 5 Sample frequency ratio set to 192
  • 7 Sample frequency ratio set to 256
  • 11 Sample frequency ratio set to 384
  • 15 Sample frequency ratio set to 512
  • 23 Sample frequency ratio set to 768
  • 31 Sample frequency ratio set to 1024
  • 47 Sample frequency ratio set to 1536
  • 63 Sample frequency ratio set to 2048
IMCKDIV21:16Selected Clock to I2SC Master Clock Ratio
TXSAME14Transmit Data when Underrun
TXDMA13Single or Multiple DMA Controller Channels for Transmitter
TXMONO12Transmit Mono
RXLOOP10Loopback Test Mode
RXDMA9Single or Multiple DMA Controller Channels for Receiver
RXMONO8Receive Mono
DATALENGTH4:2Data Word Length
  • 0 Data length is set to 32 bits
  • 1 Data length is set to 24 bits
  • 2 Data length is set to 20 bits
  • 3 Data length is set to 18 bits
  • 4 Data length is set to 16 bits
  • 5 Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word.
  • 6 Data length is set to 8 bits
  • 7 Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word.
MODE0Inter-IC Sound Controller Mode
  • 0 I2SC_CK and I2SC_WS pin inputs used as bit clock and word select/frame synchronization.
  • 1 Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SC_CK and I2SC_WS pins. Peripheral clock or GCLK is output as master clock on I2SC_MCK if I2SC_MR.IMCKMODE is set.
IWS31I2SC_WS Slot Width

I2SC_SRStatus Register

Address
0x4008C008
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
FieldBitsWhat it does
TXURCH21:20Transmit Underrun Channel
RXORCH9:8Receive Overrun Channel
TXUR6Transmit Underrun
TXRDY5Transmit Ready
TXEN4Transmitter Enabled
RXOR2Receive Overrun
RXRDY1Receive Ready
RXEN0Receiver Enabled

I2SC_SCRStatus Clear Register

Address
0x4008C00C
Reset
0x00000000
Access
write only
Size
32-bit
4 fields
FieldBitsWhat it does
TXURCH21:20Transmit Underrun Per Channel Status Clear
RXORCH9:8Receive Overrun Per Channel Status Clear
TXUR6Transmit Underrun Status Clear
RXOR2Receive Overrun Status Clear

I2SC_SSRStatus Set Register

Address
0x4008C010
Reset
0x00000000
Access
write only
Size
32-bit
4 fields
FieldBitsWhat it does
TXURCH21:20Transmit Underrun Per Channel Status Set
RXORCH9:8Receive Overrun Per Channel Status Set
TXUR6Transmit Underrun Status Set
RXOR2Receive Overrun Status Set

I2SC_IERInterrupt Enable Register

Address
0x4008C014
Reset
0x00000000
Access
write only
Size
32-bit
4 fields
FieldBitsWhat it does
TXUR6Transmit Underflow Interrupt Enable
TXRDY5Transmit Ready Interrupt Enable
RXOR2Receiver Overrun Interrupt Enable
RXRDY1Receiver Ready Interrupt Enable

I2SC_IDRInterrupt Disable Register

Address
0x4008C018
Reset
0x00000000
Access
write only
Size
32-bit
4 fields
FieldBitsWhat it does
TXUR6Transmit Underflow Interrupt Disable
TXRDY5Transmit Ready Interrupt Disable
RXOR2Receiver Overrun Interrupt Disable
RXRDY1Receiver Ready Interrupt Disable

I2SC_IMRInterrupt Mask Register

Address
0x4008C01C
Reset
0x00000000
Access
read only
Size
32-bit
4 fields
FieldBitsWhat it does
TXUR6Transmit Underflow Interrupt Disable
TXRDY5Transmit Ready Interrupt Disable
RXOR2Receiver Overrun Interrupt Disable
RXRDY1Receiver Ready Interrupt Disable

I2SC_RHRReceiver Holding Register

Address
0x4008C020
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
RHR31:0Receiver Holding Register

I2SC_THRTransmitter Holding Register

Address
0x4008C024
Reset
0x00000000
Access
write only
Size
32-bit
1 field
FieldBitsWhat it does
THR31:0Transmitter Holding Register