ATSAME70Q20B TC2 registers The 47 registers of TC2 (Timer Counter), from 0x40014000, with their reset value and every field. The ATSAME70Q20B has 2961 registers in 67 peripherals, one page each.
TC2 Timer Counter TC_CHANNEL0.TC_CCRChannel Control Register (channel = 0)
Address 0x40014000
Reset 0x00000000
Access write only
Size 32-bit 3 fields
Field Bits What it does SWTRG 2 Software Trigger Command CLKDIS 1 Counter Clock Disable Command CLKEN 0 Counter Clock Enable Command
TC_CHANNEL0.TC_CMRChannel Mode Register (channel = 0)
Address 0x40014004
Reset 0x00000000
Access read/write
Size 32-bit 26 fields
Field Bits What it does BEEVT 29:28 External Event Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE BCPC 27:26 RC Compare Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE BCPB 25:24 RB Compare Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE ASWTRG 23:22 Software Trigger Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE SBSMPLR 22:20 Loading Edge Subsampling Ratio0 Load a Capture Register each selected edge1 Load a Capture Register every 2 selected edges2 Load a Capture Register every 4 selected edges3 Load a Capture Register every 8 selected edges4 Load a Capture Register every 16 selected edges AEEVT 21:20 External Event Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE ACPC 19:18 RC Compare Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE LDRB 19:18 RB Loading Edge Selection0 None1 Rising edge of TIOAx2 Falling edge of TIOAx3 Each edge of TIOAx ACPA 17:16 RA Compare Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE LDRA 17:16 RA Loading Edge Selection0 None1 Rising edge of TIOAx2 Falling edge of TIOAx3 Each edge of TIOAx WAVE 15 Waveform Mode WAVSEL 14:13 Waveform Selection0 UP mode without automatic trigger on RC Compare1 UPDOWN mode without automatic trigger on RC Compare2 UP mode with automatic trigger on RC Compare3 UPDOWN mode with automatic trigger on RC Compare CPCTRG 14 RC Compare Trigger Enable ENETRG 12 External Event Trigger Enable EEVT 11:10 External Event Selection ABETRG 10 TIOAx or TIOBx External Trigger Selection EEVTEDG 9:8 External Event Edge Selection0 None1 Rising edge2 Falling edge3 Each edges ETRGEDG 9:8 External Trigger Edge Selection0 The clock is not gated by an external signal.1 Rising edge2 Falling edge3 Each edge CPCDIS 7 Counter Clock Disable with RC Loading LDBDIS 7 Counter Clock Disable with RB Loading CPCSTOP 6 Counter Clock Stopped with RC Compare LDBSTOP 6 Counter Clock Stopped with RB Loading BURST 5:4 Burst Signal Selection0 The clock is not gated by an external signal.1 XC0 is ANDed with the selected clock.2 XC1 is ANDed with the selected clock.3 XC2 is ANDed with the selected clock. CLKI 3 Clock Invert TCCLKS 2:0 Clock Selection0 Clock selected: internal PCK6 clock signal (from PMC)1 Clock selected: internal MCK/8 clock signal (from PMC)2 Clock selected: internal MCK/32 clock signal (from PMC)3 Clock selected: internal MCK/128 clock signal (from PMC)4 Clock selected: internal SLCK clock signal (from PMC)5 Clock selected: XC06 Clock selected: XC17 Clock selected: XC2 BSWTRG 31:30 Software Trigger Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE
TC_CHANNEL0.TC_SMMRStepper Motor Mode Register (channel = 0)
Address 0x40014008
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does DOWN 1 Down Count GCEN 0 Gray Count Enable
TC_CHANNEL0.TC_RABRegister AB (channel = 0)
Address 0x4001400C
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does RAB 31:0 Register A or Register B
TC_CHANNEL0.TC_CVCounter Value (channel = 0)
Address 0x40014010
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CV 31:0 Counter Value
TC_CHANNEL0.TC_RARegister A (channel = 0)
Address 0x40014014
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RA 31:0 Register A
TC_CHANNEL0.TC_RBRegister B (channel = 0)
Address 0x40014018
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RB 31:0 Register B
TC_CHANNEL0.TC_RCRegister C (channel = 0)
Address 0x4001401C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RC 31:0 Register C
TC_CHANNEL0.TC_SRStatus Register (channel = 0)
Address 0x40014020
Reset 0x00000000
Access read only
Size 32-bit 11 fields
Field Bits What it does MTIOB 18 TIOBx Mirror MTIOA 17 TIOAx Mirror CLKSTA 16 Clock Enabling Status ETRGS 7 External Trigger Status (cleared on read) LDRBS 6 RB Loading Status (cleared on read) LDRAS 5 RA Loading Status (cleared on read) CPCS 4 RC Compare Status (cleared on read) CPBS 3 RB Compare Status (cleared on read) CPAS 2 RA Compare Status (cleared on read) LOVRS 1 Load Overrun Status (cleared on read) COVFS 0 Counter Overflow Status (cleared on read)
TC_CHANNEL0.TC_IERInterrupt Enable Register (channel = 0)
Address 0x40014024
Reset 0x00000000
Access write only
Size 32-bit 8 fields
Field Bits What it does ETRGS 7 External Trigger LDRBS 6 RB Loading LDRAS 5 RA Loading CPCS 4 RC Compare CPBS 3 RB Compare CPAS 2 RA Compare LOVRS 1 Load Overrun COVFS 0 Counter Overflow
TC_CHANNEL0.TC_IDRInterrupt Disable Register (channel = 0)
Address 0x40014028
Reset 0x00000000
Access write only
Size 32-bit 8 fields
Field Bits What it does ETRGS 7 External Trigger LDRBS 6 RB Loading LDRAS 5 RA Loading CPCS 4 RC Compare CPBS 3 RB Compare CPAS 2 RA Compare LOVRS 1 Load Overrun COVFS 0 Counter Overflow
TC_CHANNEL0.TC_IMRInterrupt Mask Register (channel = 0)
Address 0x4001402C
Reset 0x00000000
Access read only
Size 32-bit 8 fields
Field Bits What it does ETRGS 7 External Trigger LDRBS 6 RB Loading LDRAS 5 RA Loading CPCS 4 RC Compare CPBS 3 RB Compare CPAS 2 RA Compare LOVRS 1 Load Overrun COVFS 0 Counter Overflow
TC_CHANNEL0.TC_EMRExtended Mode Register (channel = 0)
Address 0x40014030
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does NODIVCLK 8 No Divided Clock TRIGSRCB 5:4 Trigger Source for Input B0 The trigger/capture input B is driven by external pin TIOBx1 For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). TRIGSRCA 1:0 Trigger Source for Input A0 The trigger/capture input A is driven by external pin TIOAx1 The trigger/capture input A is driven internally by PWMx
TC_CHANNEL1.TC_CCRChannel Control Register (channel = 0)
Address 0x40014040
Reset 0x00000000
Access write only
Size 32-bit 3 fields
Field Bits What it does SWTRG 2 Software Trigger Command CLKDIS 1 Counter Clock Disable Command CLKEN 0 Counter Clock Enable Command
TC_CHANNEL1.TC_CMRChannel Mode Register (channel = 0)
Address 0x40014044
Reset 0x00000000
Access read/write
Size 32-bit 26 fields
Field Bits What it does BEEVT 29:28 External Event Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE BCPC 27:26 RC Compare Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE BCPB 25:24 RB Compare Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE ASWTRG 23:22 Software Trigger Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE SBSMPLR 22:20 Loading Edge Subsampling Ratio0 Load a Capture Register each selected edge1 Load a Capture Register every 2 selected edges2 Load a Capture Register every 4 selected edges3 Load a Capture Register every 8 selected edges4 Load a Capture Register every 16 selected edges AEEVT 21:20 External Event Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE ACPC 19:18 RC Compare Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE LDRB 19:18 RB Loading Edge Selection0 None1 Rising edge of TIOAx2 Falling edge of TIOAx3 Each edge of TIOAx ACPA 17:16 RA Compare Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE LDRA 17:16 RA Loading Edge Selection0 None1 Rising edge of TIOAx2 Falling edge of TIOAx3 Each edge of TIOAx WAVE 15 Waveform Mode WAVSEL 14:13 Waveform Selection0 UP mode without automatic trigger on RC Compare1 UPDOWN mode without automatic trigger on RC Compare2 UP mode with automatic trigger on RC Compare3 UPDOWN mode with automatic trigger on RC Compare CPCTRG 14 RC Compare Trigger Enable ENETRG 12 External Event Trigger Enable EEVT 11:10 External Event Selection ABETRG 10 TIOAx or TIOBx External Trigger Selection EEVTEDG 9:8 External Event Edge Selection0 None1 Rising edge2 Falling edge3 Each edges ETRGEDG 9:8 External Trigger Edge Selection0 The clock is not gated by an external signal.1 Rising edge2 Falling edge3 Each edge CPCDIS 7 Counter Clock Disable with RC Loading LDBDIS 7 Counter Clock Disable with RB Loading CPCSTOP 6 Counter Clock Stopped with RC Compare LDBSTOP 6 Counter Clock Stopped with RB Loading BURST 5:4 Burst Signal Selection0 The clock is not gated by an external signal.1 XC0 is ANDed with the selected clock.2 XC1 is ANDed with the selected clock.3 XC2 is ANDed with the selected clock. CLKI 3 Clock Invert TCCLKS 2:0 Clock Selection0 Clock selected: internal PCK6 clock signal (from PMC)1 Clock selected: internal MCK/8 clock signal (from PMC)2 Clock selected: internal MCK/32 clock signal (from PMC)3 Clock selected: internal MCK/128 clock signal (from PMC)4 Clock selected: internal SLCK clock signal (from PMC)5 Clock selected: XC06 Clock selected: XC17 Clock selected: XC2 BSWTRG 31:30 Software Trigger Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE
TC_CHANNEL1.TC_SMMRStepper Motor Mode Register (channel = 0)
Address 0x40014048
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does DOWN 1 Down Count GCEN 0 Gray Count Enable
TC_CHANNEL1.TC_RABRegister AB (channel = 0)
Address 0x4001404C
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does RAB 31:0 Register A or Register B
TC_CHANNEL1.TC_CVCounter Value (channel = 0)
Address 0x40014050
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CV 31:0 Counter Value
TC_CHANNEL1.TC_RARegister A (channel = 0)
Address 0x40014054
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RA 31:0 Register A
TC_CHANNEL1.TC_RBRegister B (channel = 0)
Address 0x40014058
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RB 31:0 Register B
TC_CHANNEL1.TC_RCRegister C (channel = 0)
Address 0x4001405C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RC 31:0 Register C
TC_CHANNEL1.TC_SRStatus Register (channel = 0)
Address 0x40014060
Reset 0x00000000
Access read only
Size 32-bit 11 fields
Field Bits What it does MTIOB 18 TIOBx Mirror MTIOA 17 TIOAx Mirror CLKSTA 16 Clock Enabling Status ETRGS 7 External Trigger Status (cleared on read) LDRBS 6 RB Loading Status (cleared on read) LDRAS 5 RA Loading Status (cleared on read) CPCS 4 RC Compare Status (cleared on read) CPBS 3 RB Compare Status (cleared on read) CPAS 2 RA Compare Status (cleared on read) LOVRS 1 Load Overrun Status (cleared on read) COVFS 0 Counter Overflow Status (cleared on read)
TC_CHANNEL1.TC_IERInterrupt Enable Register (channel = 0)
Address 0x40014064
Reset 0x00000000
Access write only
Size 32-bit 8 fields
Field Bits What it does ETRGS 7 External Trigger LDRBS 6 RB Loading LDRAS 5 RA Loading CPCS 4 RC Compare CPBS 3 RB Compare CPAS 2 RA Compare LOVRS 1 Load Overrun COVFS 0 Counter Overflow
TC_CHANNEL1.TC_IDRInterrupt Disable Register (channel = 0)
Address 0x40014068
Reset 0x00000000
Access write only
Size 32-bit 8 fields
Field Bits What it does ETRGS 7 External Trigger LDRBS 6 RB Loading LDRAS 5 RA Loading CPCS 4 RC Compare CPBS 3 RB Compare CPAS 2 RA Compare LOVRS 1 Load Overrun COVFS 0 Counter Overflow
TC_CHANNEL1.TC_IMRInterrupt Mask Register (channel = 0)
Address 0x4001406C
Reset 0x00000000
Access read only
Size 32-bit 8 fields
Field Bits What it does ETRGS 7 External Trigger LDRBS 6 RB Loading LDRAS 5 RA Loading CPCS 4 RC Compare CPBS 3 RB Compare CPAS 2 RA Compare LOVRS 1 Load Overrun COVFS 0 Counter Overflow
TC_CHANNEL1.TC_EMRExtended Mode Register (channel = 0)
Address 0x40014070
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does NODIVCLK 8 No Divided Clock TRIGSRCB 5:4 Trigger Source for Input B0 The trigger/capture input B is driven by external pin TIOBx1 For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). TRIGSRCA 1:0 Trigger Source for Input A0 The trigger/capture input A is driven by external pin TIOAx1 The trigger/capture input A is driven internally by PWMx
TC_CHANNEL2.TC_CCRChannel Control Register (channel = 0)
Address 0x40014080
Reset 0x00000000
Access write only
Size 32-bit 3 fields
Field Bits What it does SWTRG 2 Software Trigger Command CLKDIS 1 Counter Clock Disable Command CLKEN 0 Counter Clock Enable Command
TC_CHANNEL2.TC_CMRChannel Mode Register (channel = 0)
Address 0x40014084
Reset 0x00000000
Access read/write
Size 32-bit 26 fields
Field Bits What it does BEEVT 29:28 External Event Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE BCPC 27:26 RC Compare Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE BCPB 25:24 RB Compare Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE ASWTRG 23:22 Software Trigger Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE SBSMPLR 22:20 Loading Edge Subsampling Ratio0 Load a Capture Register each selected edge1 Load a Capture Register every 2 selected edges2 Load a Capture Register every 4 selected edges3 Load a Capture Register every 8 selected edges4 Load a Capture Register every 16 selected edges AEEVT 21:20 External Event Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE ACPC 19:18 RC Compare Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE LDRB 19:18 RB Loading Edge Selection0 None1 Rising edge of TIOAx2 Falling edge of TIOAx3 Each edge of TIOAx ACPA 17:16 RA Compare Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE LDRA 17:16 RA Loading Edge Selection0 None1 Rising edge of TIOAx2 Falling edge of TIOAx3 Each edge of TIOAx WAVE 15 Waveform Mode WAVSEL 14:13 Waveform Selection0 UP mode without automatic trigger on RC Compare1 UPDOWN mode without automatic trigger on RC Compare2 UP mode with automatic trigger on RC Compare3 UPDOWN mode with automatic trigger on RC Compare CPCTRG 14 RC Compare Trigger Enable ENETRG 12 External Event Trigger Enable EEVT 11:10 External Event Selection ABETRG 10 TIOAx or TIOBx External Trigger Selection EEVTEDG 9:8 External Event Edge Selection0 None1 Rising edge2 Falling edge3 Each edges ETRGEDG 9:8 External Trigger Edge Selection0 The clock is not gated by an external signal.1 Rising edge2 Falling edge3 Each edge CPCDIS 7 Counter Clock Disable with RC Loading LDBDIS 7 Counter Clock Disable with RB Loading CPCSTOP 6 Counter Clock Stopped with RC Compare LDBSTOP 6 Counter Clock Stopped with RB Loading BURST 5:4 Burst Signal Selection0 The clock is not gated by an external signal.1 XC0 is ANDed with the selected clock.2 XC1 is ANDed with the selected clock.3 XC2 is ANDed with the selected clock. CLKI 3 Clock Invert TCCLKS 2:0 Clock Selection0 Clock selected: internal PCK6 clock signal (from PMC)1 Clock selected: internal MCK/8 clock signal (from PMC)2 Clock selected: internal MCK/32 clock signal (from PMC)3 Clock selected: internal MCK/128 clock signal (from PMC)4 Clock selected: internal SLCK clock signal (from PMC)5 Clock selected: XC06 Clock selected: XC17 Clock selected: XC2 BSWTRG 31:30 Software Trigger Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE
TC_CHANNEL2.TC_SMMRStepper Motor Mode Register (channel = 0)
Address 0x40014088
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does DOWN 1 Down Count GCEN 0 Gray Count Enable
TC_CHANNEL2.TC_RABRegister AB (channel = 0)
Address 0x4001408C
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does RAB 31:0 Register A or Register B
TC_CHANNEL2.TC_CVCounter Value (channel = 0)
Address 0x40014090
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CV 31:0 Counter Value
TC_CHANNEL2.TC_RARegister A (channel = 0)
Address 0x40014094
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RA 31:0 Register A
TC_CHANNEL2.TC_RBRegister B (channel = 0)
Address 0x40014098
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RB 31:0 Register B
TC_CHANNEL2.TC_RCRegister C (channel = 0)
Address 0x4001409C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RC 31:0 Register C
TC_CHANNEL2.TC_SRStatus Register (channel = 0)
Address 0x400140A0
Reset 0x00000000
Access read only
Size 32-bit 11 fields
Field Bits What it does MTIOB 18 TIOBx Mirror MTIOA 17 TIOAx Mirror CLKSTA 16 Clock Enabling Status ETRGS 7 External Trigger Status (cleared on read) LDRBS 6 RB Loading Status (cleared on read) LDRAS 5 RA Loading Status (cleared on read) CPCS 4 RC Compare Status (cleared on read) CPBS 3 RB Compare Status (cleared on read) CPAS 2 RA Compare Status (cleared on read) LOVRS 1 Load Overrun Status (cleared on read) COVFS 0 Counter Overflow Status (cleared on read)
TC_CHANNEL2.TC_IERInterrupt Enable Register (channel = 0)
Address 0x400140A4
Reset 0x00000000
Access write only
Size 32-bit 8 fields
Field Bits What it does ETRGS 7 External Trigger LDRBS 6 RB Loading LDRAS 5 RA Loading CPCS 4 RC Compare CPBS 3 RB Compare CPAS 2 RA Compare LOVRS 1 Load Overrun COVFS 0 Counter Overflow
TC_CHANNEL2.TC_IDRInterrupt Disable Register (channel = 0)
Address 0x400140A8
Reset 0x00000000
Access write only
Size 32-bit 8 fields
Field Bits What it does ETRGS 7 External Trigger LDRBS 6 RB Loading LDRAS 5 RA Loading CPCS 4 RC Compare CPBS 3 RB Compare CPAS 2 RA Compare LOVRS 1 Load Overrun COVFS 0 Counter Overflow
TC_CHANNEL2.TC_IMRInterrupt Mask Register (channel = 0)
Address 0x400140AC
Reset 0x00000000
Access read only
Size 32-bit 8 fields
Field Bits What it does ETRGS 7 External Trigger LDRBS 6 RB Loading LDRAS 5 RA Loading CPCS 4 RC Compare CPBS 3 RB Compare CPAS 2 RA Compare LOVRS 1 Load Overrun COVFS 0 Counter Overflow
TC_CHANNEL2.TC_EMRExtended Mode Register (channel = 0)
Address 0x400140B0
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does NODIVCLK 8 No Divided Clock TRIGSRCB 5:4 Trigger Source for Input B0 The trigger/capture input B is driven by external pin TIOBx1 For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). TRIGSRCA 1:0 Trigger Source for Input A0 The trigger/capture input A is driven by external pin TIOAx1 The trigger/capture input A is driven internally by PWMx
TC_BCRBlock Control Register
Address 0x400140C0
Reset 0x00000000
Access write only
Size 32-bit 1 field
Field Bits What it does SYNC 0 Synchro Command
TC_BMRBlock Mode Register
Address 0x400140C4
Reset 0x00000000
Access read/write
Size 32-bit 16 fields
Field Bits What it does MAXCMP 29:26 Maximum Consecutive Missing Pulses MAXFILT 25:20 Maximum Filter AUTOC 18 AutoCorrection of missing pulses IDXPHB 17 Index Pin is PHB Pin SWAP 16 Swap PHA and PHB INVIDX 15 Inverted Index INVB 14 Inverted PHB INVA 13 Inverted PHA EDGPHA 12 Edge on PHA Count Mode QDTRANS 11 Quadrature Decoding Transparent SPEEDEN 10 Speed Enabled POSEN 9 Position Enabled QDEN 8 Quadrature Decoder Enabled TC2XC2S 5:4 External Clock Signal 2 Selection0 Signal connected to XC2: TCLK22 Signal connected to XC2: TIOA03 Signal connected to XC2: TIOA1 TC1XC1S 3:2 External Clock Signal 1 Selection0 Signal connected to XC1: TCLK12 Signal connected to XC1: TIOA03 Signal connected to XC1: TIOA2 TC0XC0S 1:0 External Clock Signal 0 Selection0 Signal connected to XC0: TCLK02 Signal connected to XC0: TIOA13 Signal connected to XC0: TIOA2
TC_QIERQDEC Interrupt Enable Register
Address 0x400140C8
Reset 0x00000000
Access write only
Size 32-bit 4 fields
Field Bits What it does MPE 3 Consecutive Missing Pulse Error QERR 2 Quadrature Error DIRCHG 1 Direction Change IDX 0 Index
TC_QIDRQDEC Interrupt Disable Register
Address 0x400140CC
Reset 0x00000000
Access write only
Size 32-bit 4 fields
Field Bits What it does MPE 3 Consecutive Missing Pulse Error QERR 2 Quadrature Error DIRCHG 1 Direction Change IDX 0 Index
TC_QIMRQDEC Interrupt Mask Register
Address 0x400140D0
Reset 0x00000000
Access read only
Size 32-bit 4 fields
Field Bits What it does MPE 3 Consecutive Missing Pulse Error QERR 2 Quadrature Error DIRCHG 1 Direction Change IDX 0 Index
TC_QISRQDEC Interrupt Status Register
Address 0x400140D4
Reset 0x00000000
Access read only
Size 32-bit 5 fields
Field Bits What it does DIR 8 Direction MPE 3 Consecutive Missing Pulse Error QERR 2 Quadrature Error DIRCHG 1 Direction Change IDX 0 Index
TC_FMRFault Mode Register
Address 0x400140D8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does ENCF1 1 Enable Compare Fault Channel 1 ENCF0 0 Enable Compare Fault Channel 0
TC_WPMRWrite Protection Mode Register
Address 0x400140E4
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does WPEN 0 Write Protection Enable WPKEY 31:8 Write Protection Key5523789 Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
BETA