ATSAME70Q21B SMC registers

The 21 registers of SMC (Static Memory Controller), from 0x40080000, with their reset value and every field. The ATSAME70Q21B has 2961 registers in 67 peripherals, one page each.

SMC Static Memory Controller

SMC_CS_NUMBER0.SMC_SETUPSMC Setup Register

Address
0x40080000
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_SETUP29:24NCS Setup Length in READ Access
NRD_SETUP21:16NRD Setup Length
NCS_WR_SETUP13:8NCS Setup Length in WRITE Access
NWE_SETUP5:0NWE Setup Length

SMC_CS_NUMBER0.SMC_PULSESMC Pulse Register

Address
0x40080004
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_PULSE30:24NCS Pulse Length in READ Access
NRD_PULSE22:16NRD Pulse Length
NCS_WR_PULSE14:8NCS Pulse Length in WRITE Access
NWE_PULSE6:0NWE Pulse Length

SMC_CS_NUMBER0.SMC_CYCLESMC Cycle Register

Address
0x40080008
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
NRD_CYCLE24:16Total Read Cycle Length
NWE_CYCLE8:0Total Write Cycle Length

SMC_CS_NUMBER0.SMC_MODESMC Mode Register

Address
0x4008000C
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
PS29:28Page Size
  • 0 4-byte page
  • 1 8-byte page
  • 2 16-byte page
  • 3 32-byte page
PMEN24Page Mode Enabled
TDF_MODE20TDF Optimization
TDF_CYCLES19:16Data Float Time
DBW12Data Bus Width
  • 0 8-bit Data Bus
  • 1 16-bit Data Bus
BAT8Byte Access Type
  • 0 Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1.
  • 1 Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD.
EXNW_MODE5:4NWAIT Mode
  • 0 Disabled-The NWAIT input signal is ignored on the corresponding chip select.
  • 2 Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped.
  • 3 Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high.
WRITE_MODE1Write Mode
READ_MODE0Read Mode

SMC_CS_NUMBER1.SMC_SETUPSMC Setup Register

Address
0x40080010
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_SETUP29:24NCS Setup Length in READ Access
NRD_SETUP21:16NRD Setup Length
NCS_WR_SETUP13:8NCS Setup Length in WRITE Access
NWE_SETUP5:0NWE Setup Length

SMC_CS_NUMBER1.SMC_PULSESMC Pulse Register

Address
0x40080014
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_PULSE30:24NCS Pulse Length in READ Access
NRD_PULSE22:16NRD Pulse Length
NCS_WR_PULSE14:8NCS Pulse Length in WRITE Access
NWE_PULSE6:0NWE Pulse Length

SMC_CS_NUMBER1.SMC_CYCLESMC Cycle Register

Address
0x40080018
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
NRD_CYCLE24:16Total Read Cycle Length
NWE_CYCLE8:0Total Write Cycle Length

SMC_CS_NUMBER1.SMC_MODESMC Mode Register

Address
0x4008001C
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
PS29:28Page Size
  • 0 4-byte page
  • 1 8-byte page
  • 2 16-byte page
  • 3 32-byte page
PMEN24Page Mode Enabled
TDF_MODE20TDF Optimization
TDF_CYCLES19:16Data Float Time
DBW12Data Bus Width
  • 0 8-bit Data Bus
  • 1 16-bit Data Bus
BAT8Byte Access Type
  • 0 Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1.
  • 1 Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD.
EXNW_MODE5:4NWAIT Mode
  • 0 Disabled-The NWAIT input signal is ignored on the corresponding chip select.
  • 2 Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped.
  • 3 Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high.
WRITE_MODE1Write Mode
READ_MODE0Read Mode

SMC_CS_NUMBER2.SMC_SETUPSMC Setup Register

Address
0x40080020
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_SETUP29:24NCS Setup Length in READ Access
NRD_SETUP21:16NRD Setup Length
NCS_WR_SETUP13:8NCS Setup Length in WRITE Access
NWE_SETUP5:0NWE Setup Length

SMC_CS_NUMBER2.SMC_PULSESMC Pulse Register

Address
0x40080024
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_PULSE30:24NCS Pulse Length in READ Access
NRD_PULSE22:16NRD Pulse Length
NCS_WR_PULSE14:8NCS Pulse Length in WRITE Access
NWE_PULSE6:0NWE Pulse Length

SMC_CS_NUMBER2.SMC_CYCLESMC Cycle Register

Address
0x40080028
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
NRD_CYCLE24:16Total Read Cycle Length
NWE_CYCLE8:0Total Write Cycle Length

SMC_CS_NUMBER2.SMC_MODESMC Mode Register

Address
0x4008002C
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
PS29:28Page Size
  • 0 4-byte page
  • 1 8-byte page
  • 2 16-byte page
  • 3 32-byte page
PMEN24Page Mode Enabled
TDF_MODE20TDF Optimization
TDF_CYCLES19:16Data Float Time
DBW12Data Bus Width
  • 0 8-bit Data Bus
  • 1 16-bit Data Bus
BAT8Byte Access Type
  • 0 Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1.
  • 1 Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD.
EXNW_MODE5:4NWAIT Mode
  • 0 Disabled-The NWAIT input signal is ignored on the corresponding chip select.
  • 2 Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped.
  • 3 Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high.
WRITE_MODE1Write Mode
READ_MODE0Read Mode

SMC_CS_NUMBER3.SMC_SETUPSMC Setup Register

Address
0x40080030
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_SETUP29:24NCS Setup Length in READ Access
NRD_SETUP21:16NRD Setup Length
NCS_WR_SETUP13:8NCS Setup Length in WRITE Access
NWE_SETUP5:0NWE Setup Length

SMC_CS_NUMBER3.SMC_PULSESMC Pulse Register

Address
0x40080034
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_PULSE30:24NCS Pulse Length in READ Access
NRD_PULSE22:16NRD Pulse Length
NCS_WR_PULSE14:8NCS Pulse Length in WRITE Access
NWE_PULSE6:0NWE Pulse Length

SMC_CS_NUMBER3.SMC_CYCLESMC Cycle Register

Address
0x40080038
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
NRD_CYCLE24:16Total Read Cycle Length
NWE_CYCLE8:0Total Write Cycle Length

SMC_CS_NUMBER3.SMC_MODESMC Mode Register

Address
0x4008003C
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
PS29:28Page Size
  • 0 4-byte page
  • 1 8-byte page
  • 2 16-byte page
  • 3 32-byte page
PMEN24Page Mode Enabled
TDF_MODE20TDF Optimization
TDF_CYCLES19:16Data Float Time
DBW12Data Bus Width
  • 0 8-bit Data Bus
  • 1 16-bit Data Bus
BAT8Byte Access Type
  • 0 Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1.
  • 1 Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD.
EXNW_MODE5:4NWAIT Mode
  • 0 Disabled-The NWAIT input signal is ignored on the corresponding chip select.
  • 2 Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped.
  • 3 Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high.
WRITE_MODE1Write Mode
READ_MODE0Read Mode

SMC_OCMSSMC Off-Chip Memory Scrambling Register

Address
0x40080080
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
CS3SE11Chip Select (x = 0 to 3) Scrambling Enable
CS2SE10Chip Select (x = 0 to 3) Scrambling Enable
CS1SE9Chip Select (x = 0 to 3) Scrambling Enable
CS0SE8Chip Select (x = 0 to 3) Scrambling Enable
SMSE0Static Memory Controller Scrambling Enable

SMC_KEY1SMC Off-Chip Memory Scrambling KEY1 Register

Address
0x40080084
Reset
0x00000000
Access
write only
Size
32-bit
1 field
FieldBitsWhat it does
KEY131:0Off-Chip Memory Scrambling (OCMS) Key Part 1

SMC_KEY2SMC Off-Chip Memory Scrambling KEY2 Register

Address
0x40080088
Reset
0x00000000
Access
write only
Size
32-bit
1 field
FieldBitsWhat it does
KEY231:0Off-Chip Memory Scrambling (OCMS) Key Part 2

SMC_WPMRSMC Write Protection Mode Register

Address
0x400800E4
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
WPEN0Write Protect Enable
WPKEY31:8Write Protection Key
  • 5459267 Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

SMC_WPSRSMC Write Protection Status Register

Address
0x400800E8
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
WPVSRC23:8Write Protection Violation Source
WPVS0Write Protection Violation Status