ATSAME70Q21B USART2 registers The 31 registers of USART2 (Universal Synchronous Asynchronous Receiver Transmitter), from 0x4002C000, with their reset value and every field. The ATSAME70Q21B has 2961 registers in 67 peripherals, one page each.
USART2 Universal Synchronous Asynchronous Receiver Transmitter US_CRControl Register
Address 0x4002C000
Reset 0x00000000
Access write only
Size 32-bit 36 fields
Field Bits What it does LINWKUP 21 Send LIN Wakeup Signal LINABT 20 Abort LIN Transmission RCS 19 Release SPI Chip Select RTSDIS 19 Request to Send Disable FCS 18 Force SPI Chip Select RTSEN 18 Request to Send Enable DTRDIS 17 Data Terminal Ready Disable DTREN 16 Data Terminal Ready Enable RETTO 15 Start Timeout Immediately RSTNACK 14 Reset Non Acknowledge RSTIT 13 Reset Iterations SENDA 12 Send Address STTTO 11 Clear TIMEOUT Flag and Start Timeout After Next Character Received STPBRK 10 Stop Break STTBRK 9 Start Break RSTSTA 8 Reset Status Bits RSTSTA 8 Reset Status Bits RSTSTA 8 Reset Status Bits TXDIS 7 Transmitter Disable TXDIS 7 Transmitter Disable TXDIS 7 Transmitter Disable TXEN 6 Transmitter Enable TXEN 6 Transmitter Enable TXEN 6 Transmitter Enable RXDIS 5 Receiver Disable RXDIS 5 Receiver Disable RXDIS 5 Receiver Disable RXEN 4 Receiver Enable RXEN 4 Receiver Enable RXEN 4 Receiver Enable RSTTX 3 Reset Transmitter RSTTX 3 Reset Transmitter RSTTX 3 Reset Transmitter RSTRX 2 Reset Receiver RSTRX 2 Reset Receiver RSTRX 2 Reset Receiver
US_MRMode Register
Address 0x4002C004
Reset 0x00000000
Access read/write
Size 32-bit 27 fields
Field Bits What it does MODSYNC 30 Manchester Synchronization Mode MAN 29 Manchester Encoder/Decoder Enable FILTER 28 Receive Line Filter MAX_ITERATION 26:24 Maximum Number of Automatic Iteration INVDATA 23 Inverted Data VAR_SYNC 22 Variable Synchronization of Command/Data Sync Start Frame Delimiter DSNACK 21 Disable Successive NACK INACK 20 Inhibit Non Acknowledge WRDBT 20 Wait Read Data Before Transfer OVER 19 Oversampling Mode CLKO 18 Clock Output Select CLKO 18 Clock Output Select MODE9 17 9-bit Character Length CPOL 16 SPI Clock Polarity MSBF 16 Bit Order CHMODE 15:14 Channel Mode0 Normal mode1 Automatic Echo. Receiver input is connected to the TXD pin.2 Local Loopback. Transmitter output is connected to the Receiver Input.3 Remote Loopback. RXD pin is internally connected to the TXD pin. NBSTOP 13:12 Number of Stop Bits0 1 stop bit1 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)2 2 stop bits PAR 11:9 Parity Type0 Even parity1 Odd parity2 Parity forced to 0 (Space)3 Parity forced to 1 (Mark)4 No parity6 Multidrop mode CPHA 8 SPI Clock Phase SYNC 8 Synchronous Mode Select CHRL 7:6 Character Length0 Character length is 5 bits1 Character length is 6 bits2 Character length is 7 bits3 Character length is 8 bits CHRL 7:6 Character Length0 Character length is 5 bits1 Character length is 6 bits2 Character length is 7 bits3 Character length is 8 bits USCLKS 5:4 Clock Selection0 Peripheral clock is selected1 Peripheral clock divided (DIV = 8) is selected2 PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1.3 Serial clock (SCK) is selected USCLKS 5:4 Clock Selection0 Peripheral clock is selected1 Peripheral clock divided (DIV = 8) is selected2 PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1.3 Serial clock (SCK) is selected USART_MODE 3:0 USART Mode of Operation0 Normal mode1 RS4852 Hardware handshaking3 Modem4 IS07816 Protocol: T = 06 IS07816 Protocol: T = 18 IrDA9 LON10 LIN Master mode11 LIN Slave mode14 SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2)15 SPI Slave mode USART_MODE 3:0 USART Mode of Operation0 Normal mode1 RS4852 Hardware handshaking3 Modem4 IS07816 Protocol: T = 06 IS07816 Protocol: T = 18 IrDA9 LON10 LIN Master mode11 LIN Slave mode14 SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2)15 SPI Slave mode ONEBIT 31 Start Frame Delimiter Selector
US_IERInterrupt Enable Register
Address 0x4002C008
Reset 0x00000000
Access write only
Size 32-bit 50 fields
Field Bits What it does LINSTE 30 LIN Synch Tolerance Error Interrupt Enable LINSNRE 29 LIN Slave Not Responding Error Interrupt Enable LBLOVFE 28 LON Backlog Overflow Error Interrupt Enable LINCE 28 LIN Checksum Error Interrupt Enable LINIPE 27 LIN Identifier Parity Interrupt Enable LRXD 27 LON Reception Done Interrupt Enable LFET 26 LON Frame Early Termination Interrupt Enable LINISFE 26 LIN Inconsistent Synch Field Error Interrupt Enable LCOL 25 LON Collision Interrupt Enable LINBE 25 LIN Bus Error Interrupt Enable LTXD 24 LON Transmission Done Interrupt Enable MANE 24 Manchester Error Interrupt Enable CTSIC 19 Clear to Send Input Change Interrupt Enable NSSE 19 NSS Line (Driving CTS Pin) Rising or Falling Edge Event DCDIC 18 Data Carrier Detect Input Change Interrupt Enable DSRIC 17 Data Set Ready Input Change Enable RIIC 16 Ring Indicator Input Change Enable LINTC 15 LIN Transfer Completed Interrupt Enable LINID 14 LIN Identifier Sent or LIN Identifier Received Interrupt Enable LINBK 13 LIN Break Sent or LIN Break Received Interrupt Enable NACK 13 Non Acknowledge Interrupt Enable ITER 10 Max number of Repetitions Reached Interrupt Enable UNRE 10 Underrun Error Interrupt Enable UNRE 10 Underrun Error Interrupt Enable TXEMPTY 9 TXEMPTY Interrupt Enable TXEMPTY 9 TXEMPTY Interrupt Enable TXEMPTY 9 TXEMPTY Interrupt Enable TXEMPTY 9 TXEMPTY Interrupt Enable TIMEOUT 8 Timeout Interrupt Enable TIMEOUT 8 Timeout Interrupt Enable LCRCE 7 LON CRC Error Interrupt Enable PARE 7 Parity Error Interrupt Enable PARE 7 Parity Error Interrupt Enable FRAME 6 Framing Error Interrupt Enable FRAME 6 Framing Error Interrupt Enable LSFE 6 LON Short Frame Error Interrupt Enable OVRE 5 Overrun Error Interrupt Enable OVRE 5 Overrun Error Interrupt Enable OVRE 5 Overrun Error Interrupt Enable OVRE 5 Overrun Error Interrupt Enable RXBRK 2 Receiver Break Interrupt Enable TXRDY 1 TXRDY Interrupt Enable TXRDY 1 TXRDY Interrupt Enable TXRDY 1 TXRDY Interrupt Enable TXRDY 1 TXRDY Interrupt Enable RXRDY 0 RXRDY Interrupt Enable RXRDY 0 RXRDY Interrupt Enable RXRDY 0 RXRDY Interrupt Enable RXRDY 0 RXRDY Interrupt Enable LINHTE 31 LIN Header Timeout Error Interrupt Enable
US_IDRInterrupt Disable Register
Address 0x4002C00C
Reset 0x00000000
Access write only
Size 32-bit 50 fields
Field Bits What it does LINSTE 30 LIN Synch Tolerance Error Interrupt Disable LINSNRE 29 LIN Slave Not Responding Error Interrupt Disable LBLOVFE 28 LON Backlog Overflow Error Interrupt Disable LINCE 28 LIN Checksum Error Interrupt Disable LINIPE 27 LIN Identifier Parity Interrupt Disable LRXD 27 LON Reception Done Interrupt Disable LFET 26 LON Frame Early Termination Interrupt Disable LINISFE 26 LIN Inconsistent Synch Field Error Interrupt Disable LCOL 25 LON Collision Interrupt Disable LINBE 25 LIN Bus Error Interrupt Disable LTXD 24 LON Transmission Done Interrupt Disable MANE 24 Manchester Error Interrupt Disable CTSIC 19 Clear to Send Input Change Interrupt Disable NSSE 19 NSS Line (Driving CTS Pin) Rising or Falling Edge Event DCDIC 18 Data Carrier Detect Input Change Interrupt Disable DSRIC 17 Data Set Ready Input Change Disable RIIC 16 Ring Indicator Input Change Disable LINTC 15 LIN Transfer Completed Interrupt Disable LINID 14 LIN Identifier Sent or LIN Identifier Received Interrupt Disable LINBK 13 LIN Break Sent or LIN Break Received Interrupt Disable NACK 13 Non Acknowledge Interrupt Disable ITER 10 Max Number of Repetitions Reached Interrupt Disable UNRE 10 SPI Underrun Error Interrupt Disable UNRE 10 SPI Underrun Error Interrupt Disable TXEMPTY 9 TXEMPTY Interrupt Disable TXEMPTY 9 TXEMPTY Interrupt Disable TXEMPTY 9 TXEMPTY Interrupt Disable TXEMPTY 9 TXEMPTY Interrupt Disable TIMEOUT 8 Timeout Interrupt Disable TIMEOUT 8 Timeout Interrupt Disable LCRCE 7 LON CRC Error Interrupt Disable PARE 7 Parity Error Interrupt Disable PARE 7 Parity Error Interrupt Disable FRAME 6 Framing Error Interrupt Disable FRAME 6 Framing Error Interrupt Disable LSFE 6 LON Short Frame Error Interrupt Disable OVRE 5 Overrun Error Interrupt Enable OVRE 5 Overrun Error Interrupt Enable OVRE 5 Overrun Error Interrupt Enable OVRE 5 Overrun Error Interrupt Enable RXBRK 2 Receiver Break Interrupt Disable TXRDY 1 TXRDY Interrupt Disable TXRDY 1 TXRDY Interrupt Disable TXRDY 1 TXRDY Interrupt Disable TXRDY 1 TXRDY Interrupt Disable RXRDY 0 RXRDY Interrupt Disable RXRDY 0 RXRDY Interrupt Disable RXRDY 0 RXRDY Interrupt Disable RXRDY 0 RXRDY Interrupt Disable LINHTE 31 LIN Header Timeout Error Interrupt Disable
US_IMRInterrupt Mask Register
Address 0x4002C010
Reset 0x00000000
Access read only
Size 32-bit 50 fields
Field Bits What it does LINSTE 30 LIN Synch Tolerance Error Interrupt Mask LINSNRE 29 LIN Slave Not Responding Error Interrupt Mask LBLOVFE 28 LON Backlog Overflow Error Interrupt Mask LINCE 28 LIN Checksum Error Interrupt Mask LINIPE 27 LIN Identifier Parity Interrupt Mask LRXD 27 LON Reception Done Interrupt Mask LFET 26 LON Frame Early Termination Interrupt Mask LINISFE 26 LIN Inconsistent Synch Field Error Interrupt Mask LCOL 25 LON Collision Interrupt Mask LINBE 25 LIN Bus Error Interrupt Mask LTXD 24 LON Transmission Done Interrupt Mask MANE 24 Manchester Error Interrupt Mask CTSIC 19 Clear to Send Input Change Interrupt Mask NSSE 19 NSS Line (Driving CTS Pin) Rising or Falling Edge Event DCDIC 18 Data Carrier Detect Input Change Interrupt Mask DSRIC 17 Data Set Ready Input Change Mask RIIC 16 Ring Indicator Input Change Mask LINTC 15 LIN Transfer Completed Interrupt Mask LINID 14 LIN Identifier Sent or LIN Identifier Received Interrupt Mask LINBK 13 LIN Break Sent or LIN Break Received Interrupt Mask NACK 13 Non Acknowledge Interrupt Mask ITER 10 Max Number of Repetitions Reached Interrupt Mask UNRE 10 SPI Underrun Error Interrupt Mask UNRE 10 SPI Underrun Error Interrupt Mask TXEMPTY 9 TXEMPTY Interrupt Mask TXEMPTY 9 TXEMPTY Interrupt Mask TXEMPTY 9 TXEMPTY Interrupt Mask TXEMPTY 9 TXEMPTY Interrupt Mask TIMEOUT 8 Timeout Interrupt Mask TIMEOUT 8 Timeout Interrupt Mask LCRCE 7 LON CRC Error Interrupt Mask PARE 7 Parity Error Interrupt Mask PARE 7 Parity Error Interrupt Mask FRAME 6 Framing Error Interrupt Mask FRAME 6 Framing Error Interrupt Mask LSFE 6 LON Short Frame Error Interrupt Mask OVRE 5 Overrun Error Interrupt Mask OVRE 5 Overrun Error Interrupt Mask OVRE 5 Overrun Error Interrupt Mask OVRE 5 Overrun Error Interrupt Mask RXBRK 2 Receiver Break Interrupt Mask TXRDY 1 TXRDY Interrupt Mask TXRDY 1 TXRDY Interrupt Mask TXRDY 1 TXRDY Interrupt Mask TXRDY 1 TXRDY Interrupt Mask RXRDY 0 RXRDY Interrupt Mask RXRDY 0 RXRDY Interrupt Mask RXRDY 0 RXRDY Interrupt Mask RXRDY 0 RXRDY Interrupt Mask LINHTE 31 LIN Header Timeout Error Interrupt Mask
US_CSRChannel Status Register
Address 0x4002C014
Reset 0x00000000
Access read only
Size 32-bit 56 fields
Field Bits What it does LINSTE 30 LIN Synch Tolerance Error LINSNRE 29 LIN Slave Not Responding Error Interrupt Mask LBLOVFE 28 LON Backlog Overflow Error LINCE 28 LIN Checksum Error LINIPE 27 LIN Identifier Parity Error LRXD 27 LON Reception End Flag LFET 26 LON Frame Early Termination LINISFE 26 LIN Inconsistent Synch Field Error LCOL 25 LON Collision Detected Flag LINBE 25 LIN Bus Error LTXD 24 LON Transmission End Flag MANERR 24 Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) CTS 23 Image of CTS Input LINBLS 23 LIN Bus Line Status NSS 23 Image of NSS Line DCD 22 Image of DCD Input DSR 21 Image of DSR Input RI 20 Image of RI Input CTSIC 19 Clear to Send Input Change Flag (cleared on read) NSSE 19 NSS Line (Driving CTS Pin) Rising or Falling Edge Event DCDIC 18 Data Carrier Detect Input Change Flag (cleared on read) DSRIC 17 Data Set Ready Input Change Flag (cleared on read) RIIC 16 Ring Indicator Input Change Flag (cleared on read) LINTC 15 LIN Transfer Completed LINID 14 LIN Identifier Sent or LIN Identifier Received LINBK 13 LIN Break Sent or LIN Break Received NACK 13 Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) ITER 10 Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) UNRE 10 SPI Underrun Error UNRE 10 Underrun Error TXEMPTY 9 Transmitter Empty (cleared by writing US_THR) TXEMPTY 9 Transmitter Empty (cleared by writing US_THR) TXEMPTY 9 Transmitter Empty (cleared by writing US_THR) TXEMPTY 9 Transmitter Empty (cleared by writing US_THR) TIMEOUT 8 Receiver Timeout (cleared by writing a one to bit US_CR.STTTO) TIMEOUT 8 Receiver Timeout (cleared by writing a one to bit US_CR.STTTO) LCRCE 7 LON CRC Error PARE 7 Parity Error (cleared by writing a one to bit US_CR.RSTSTA) PARE 7 Parity Error (cleared by writing a one to bit US_CR.RSTSTA) FRAME 6 Framing Error (cleared by writing a one to bit US_CR.RSTSTA) FRAME 6 Framing Error (cleared by writing a one to bit US_CR.RSTSTA) LSFE 6 LON Short Frame Error OVRE 5 Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) OVRE 5 Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) OVRE 5 Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) OVRE 5 Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) RXBRK 2 Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) TXRDY 1 Transmitter Ready (cleared by writing US_THR) TXRDY 1 Transmitter Ready (cleared by writing US_THR) TXRDY 1 Transmitter Ready (cleared by writing US_THR) TXRDY 1 Transmitter Ready (cleared by writing US_THR) RXRDY 0 Receiver Ready (cleared by reading US_RHR) RXRDY 0 Receiver Ready (cleared by reading US_RHR) RXRDY 0 Receiver Ready (cleared by reading US_RHR) RXRDY 0 Receiver Ready (cleared by reading US_RHR) LINHTE 31 LIN Header Timeout Error
US_RHRReceive Holding Register
Address 0x4002C018
Reset 0x00000000
Access read only
Size 32-bit 2 fields
Field Bits What it does RXSYNH 15 Received Sync RXCHR 8:0 Received Character
US_THRTransmit Holding Register
Address 0x4002C01C
Reset 0x00000000
Access write only
Size 32-bit 2 fields
Field Bits What it does TXSYNH 15 Sync Field to be Transmitted TXCHR 8:0 Character to be Transmitted
US_BRGRBaud Rate Generator Register
Address 0x4002C020
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does FP 18:16 Fractional Part CD 15:0 Clock Divider
US_RTORReceiver Timeout Register
Address 0x4002C024
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does TO 16:0 Timeout Value
US_TTGRTransmitter Timeguard Register
Address 0x4002C028
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PCYCLE 23:0 LON PCYCLE Length TG 7:0 Timeguard Value
US_FIDIFI DI Ratio Register
Address 0x4002C040
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does BETA2 23:0 LON BETA2 Length FI_DI_RATIO 15:0 FI Over DI Ratio Value
US_NERNumber of Errors Register
Address 0x4002C044
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does NB_ERRORS 7:0 Number of Errors
US_IFIrDA Filter Register
Address 0x4002C04C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does IRDA_FILTER 7:0 IrDA Filter
US_MANManchester Configuration Register
Address 0x4002C050
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does DRIFT 30 Drift Compensation ONE 29 Must Be Set to 1 RX_MPOL 28 Receiver Manchester Polarity RX_PP 25:24 Receiver Preamble Pattern detected0 The preamble is composed of '1's1 The preamble is composed of '0's2 The preamble is composed of '01's3 The preamble is composed of '10's RX_PL 19:16 Receiver Preamble Length TX_MPOL 12 Transmitter Manchester Polarity TX_PP 9:8 Transmitter Preamble Pattern0 The preamble is composed of '1's1 The preamble is composed of '0's2 The preamble is composed of '01's3 The preamble is composed of '10's TX_PL 3:0 Transmitter Preamble Length RXIDLEV 31 Receiver Idle Value
US_LINMRLIN Mode Register
Address 0x4002C054
Reset 0x00000000
Access read/write
Size 32-bit 10 fields
Field Bits What it does SYNCDIS 17 Synchronization Disable PDCM 16 DMAC Mode DLC 15:8 Data Length Control WKUPTYP 7 Wakeup Signal Type FSDIS 6 Frame Slot Mode Disable DLM 5 Data Length Mode CHKTYP 4 Checksum Type CHKDIS 3 Checksum Disable PARDIS 2 Parity Disable NACT 1:0 LIN Node Action0 The USART transmits the response.1 The USART receives the response.2 The USART does not transmit and does not receive the response.
US_LINIRLIN Identifier Register
Address 0x4002C058
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does IDCHR 7:0 Identifier Character
US_LINBRRLIN Baud Rate Register
Address 0x4002C05C
Reset 0x00000000
Access read only
Size 32-bit 2 fields
Field Bits What it does LINFP 18:16 Fractional Part after Synchronization LINCD 15:0 Clock Divider after Synchronization
US_LONMRLON Mode Register
Address 0x4002C060
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does EOFS 23:16 End of Frame Condition Size LCDS 5 LON Collision Detection Source DMAM 4 LON DMA Mode CDTAIL 3 LON Collision Detection on Frame Tail TCOL 2 Terminate Frame upon Collision Notification COLDET 1 LON Collision Detection Feature COMMT 0 LON comm_type Parameter Value
US_LONPRLON Preamble Register
Address 0x4002C064
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does LONPL 13:0 LON Preamble Length
US_LONDLLON Data Length Register
Address 0x4002C068
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does LONDL 7:0 LON Data Length
US_LONL2HDRLON L2HDR Register
Address 0x4002C06C
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does PB 7 LON Priority Bit ALTP 6 LON Alternate Path Bit BLI 5:0 LON Backlog Increment
US_LONBLLON Backlog Register
Address 0x4002C070
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does LONBL 5:0 LON Node Backlog Value
US_LONB1TXLON Beta1 Tx Register
Address 0x4002C074
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BETA1TX 23:0 LON Beta1 Length after Transmission
US_LONB1RXLON Beta1 Rx Register
Address 0x4002C078
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BETA1RX 23:0 LON Beta1 Length after Reception
US_LONPRIOLON Priority Register
Address 0x4002C07C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NPS 14:8 LON Node Priority Slot PSNB 6:0 LON Priority Slot Number
US_IDTTXLON IDT Tx Register
Address 0x4002C080
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does IDTTX 23:0 LON Indeterminate Time after Transmission (comm_type = 1 mode only)
US_IDTRXLON IDT Rx Register
Address 0x4002C084
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does IDTRX 23:0 LON Indeterminate Time after Reception (comm_type = 1 mode only)
US_ICDIFFIC DIFF Register
Address 0x4002C088
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does ICDIFF 3:0 IC Differentiator Number
US_WPMRWrite Protection Mode Register
Address 0x4002C0E4
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does WPEN 0 Write Protection Enable WPKEY 31:8 Write Protection Key5591873 Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
US_WPSRWrite Protection Status Register
Address 0x4002C0E8
Reset 0x00000000
Access read only
Size 32-bit 2 fields
Field Bits What it does WPVSRC 23:8 Write Protection Violation Source WPVS 0 Write Protection Violation Status
BETA