The 32 registers of ADC (Analog-to-Digital Converter), from 0x40038000, with their reset value and every field. The ATSAMG51G18 has 569 registers in 26 peripherals, one page each.
ADC Analog-to-Digital Converter
ADC_CRControl Register
Address
0x40038000
Reset
0x00000000
Access
write only
Size
32-bit
3 fields
Field
Bits
What it does
AUTOCAL
3
Automatic Calibration of ADC
START
1
Start Conversion
SWRST
0
Software Reset
ADC_MRMode Register
Address
0x40038004
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
DIV3
30
ADC Clock Prescaler Division forced to 3
0 The PRESCAL field is used to generate the ADC clock unless DIV1 is written to 1.
1 The ADC clock equals peripheral clock/3 unless DIV1 is written to 1.
TRANSFER
29:28
Transfer Period
TRACKTIM
27:24
Tracking Time
DIV1
22
ADC Clock Prescaler Division forced to 1
0 The PRESCAL field is used to generate the ADC clock unless DIV3 is written to 1.
1 The ADC clock equals peripheral clock (PRESCAL and DIV3 fields have no effect).
STARTUP
19:16
Start Up Time
0 0 periods of ADCCLK
1 8 periods of ADCCLK
2 16 periods of ADCCLK
3 24 periods of ADCCLK
4 64 periods of ADCCLK
5 80 periods of ADCCLK
6 96 periods of ADCCLK
7 112 periods of ADCCLK
8 512 periods of ADCCLK
9 576 periods of ADCCLK
10 640 periods of ADCCLK
11 704 periods of ADCCLK
12 768 periods of ADCCLK
13 832 periods of ADCCLK
14 896 periods of ADCCLK
15 960 periods of ADCCLK
PRESCAL
15:8
Prescaler Rate Selection
FREERUN
7
Free Run Mode
0 Normal Mode
1 Free Run Mode: Never wait for any trigger.
SLEEP
5
Sleep Mode
0 Normal Mode: The ADC core and reference voltage circuitry are kept ON between conversions.
1 Sleep Mode: The ADC core and reference voltage circuitry are OFF between conversions.
LOWRES
4
Resolution
0 10-bit resolution. For higher resolution by averaging, please refer to "ADC Extended Mode Register" on page 77.
1 8-bit resolution
TRGSEL
3:1
Trigger Selection
0 External trigger
1 TIO Output of the Timer Counter Channel 0
2 TIO Output of the Timer Counter Channel 1
3 TIO Output of the Timer Counter Channel 2
4 RTCOUT0
5 RTTINC
TRGEN
0
Trigger Enable
0 Hardware triggers are disabled. Starting a conversion is only possible by software.
1 Hardware trigger selected by TRGSEL field is enabled.
USEQ
31
Use Sequence Enable
0 Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index.
1 User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 register and can be used to convert the same channel several times.
ADC_SEQR1Channel Sequence Register 1
Address
0x40038008
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
USCH7
27:24
User Sequence Number 7
USCH6
23:20
User Sequence Number 6
USCH5
19:16
User Sequence Number 5
USCH4
15:12
User Sequence Number 4
USCH3
11:8
User Sequence Number 3
USCH2
7:4
User Sequence Number 2
USCH1
3:0
User Sequence Number 1
ADC_CHERChannel Enable Register
Address
0x40038010
Reset
0x00000000
Access
write only
Size
32-bit
8 fields
Field
Bits
What it does
CH7
7
Channel 7 Enable
CH6
6
Channel 6 Enable
CH5
5
Channel 5 Enable
CH4
4
Channel 4 Enable
CH3
3
Channel 3 Enable
CH2
2
Channel 2 Enable
CH1
1
Channel 1 Enable
CH0
0
Channel 0 Enable
ADC_CHDRChannel Disable Register
Address
0x40038014
Reset
0x00000000
Access
write only
Size
32-bit
8 fields
Field
Bits
What it does
CH7
7
Channel 7 Disable
CH6
6
Channel 6 Disable
CH5
5
Channel 5 Disable
CH4
4
Channel 4 Disable
CH3
3
Channel 3 Disable
CH2
2
Channel 2 Disable
CH1
1
Channel 1 Disable
CH0
0
Channel 0 Disable
ADC_CHSRChannel Status Register
Address
0x40038018
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
Field
Bits
What it does
CH7
7
Channel 7 Status
CH6
6
Channel 6 Status
CH5
5
Channel 5 Status
CH4
4
Channel 4 Status
CH3
3
Channel 3 Status
CH2
2
Channel 2 Status
CH1
1
Channel 1 Status
CH0
0
Channel 0 Status
ADC_LCDRLast Converted Data Register
Address
0x40038020
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
CHNB
15:12
Channel Number
LDATA
11:0
Last Data Converted
ADC_IERInterrupt Enable Register
Address
0x40038024
Reset
0x00000000
Access
write only
Size
32-bit
15 fields
Field
Bits
What it does
RXBUFF
28
Receive Buffer Full Interrupt Enable
ENDRX
27
End of Receive Buffer Interrupt Enable
COMPE
26
Comparison Event Interrupt Enable
GOVRE
25
General Overrun Error Interrupt Enable
DRDY
24
Data Ready Interrupt Enable
EOCAL
23
End of Calibration Sequence
LCCHG
19
Last Channel Change Interrupt Enable
EOC7
7
End of Conversion Interrupt Enable 7
EOC6
6
End of Conversion Interrupt Enable 6
EOC5
5
End of Conversion Interrupt Enable 5
EOC4
4
End of Conversion Interrupt Enable 4
EOC3
3
End of Conversion Interrupt Enable 3
EOC2
2
End of Conversion Interrupt Enable 2
EOC1
1
End of Conversion Interrupt Enable 1
EOC0
0
End of Conversion Interrupt Enable 0
ADC_IDRInterrupt Disable Register
Address
0x40038028
Reset
0x00000000
Access
write only
Size
32-bit
15 fields
Field
Bits
What it does
RXBUFF
28
Receive Buffer Full Interrupt Disable
ENDRX
27
End of Receive Buffer Interrupt Disable
COMPE
26
Comparison Event Interrupt Disable
GOVRE
25
General Overrun Error Interrupt Disable
DRDY
24
Data Ready Interrupt Disable
EOCAL
23
End of Calibration Sequence
LCCHG
19
Last Channel Change Interrupt Disable
EOC7
7
End of Conversion Interrupt Disable 7
EOC6
6
End of Conversion Interrupt Disable 6
EOC5
5
End of Conversion Interrupt Disable 5
EOC4
4
End of Conversion Interrupt Disable 4
EOC3
3
End of Conversion Interrupt Disable 3
EOC2
2
End of Conversion Interrupt Disable 2
EOC1
1
End of Conversion Interrupt Disable 1
EOC0
0
End of Conversion Interrupt Disable 0
ADC_IMRInterrupt Mask Register
Address
0x4003802C
Reset
0x00000000
Access
read only
Size
32-bit
15 fields
Field
Bits
What it does
RXBUFF
28
Receive Buffer Full Interrupt Mask
ENDRX
27
End of Receive Buffer Interrupt Mask
COMPE
26
Comparison Event Interrupt Mask
GOVRE
25
General Overrun Error Interrupt Mask
DRDY
24
Data Ready Interrupt Mask
EOCAL
23
End of Calibration Sequence
LCCHG
19
Last Channel Change Interrupt Mask
EOC7
7
End of Conversion Interrupt Mask 7
EOC6
6
End of Conversion Interrupt Mask 6
EOC5
5
End of Conversion Interrupt Mask 5
EOC4
4
End of Conversion Interrupt Mask 4
EOC3
3
End of Conversion Interrupt Mask 3
EOC2
2
End of Conversion Interrupt Mask 2
EOC1
1
End of Conversion Interrupt Mask 1
EOC0
0
End of Conversion Interrupt Mask 0
ADC_ISRInterrupt Status Register
Address
0x40038030
Reset
0x00000000
Access
read only
Size
32-bit
15 fields
Field
Bits
What it does
RXBUFF
28
Receive Buffer Full (cleared by writing ADC_RCR or ADC_RNCR)
ENDRX
27
End of Receive Transfer (cleared by writing ADC_RCR or ADC_RNCR)
COMPE
26
Comparison Event (cleared on read)
GOVRE
25
General Overrun Error (cleared on read)
DRDY
24
Data Ready (automatically set / cleared)
EOCAL
23
End of Calibration Sequence
LCCHG
19
Last Channel Change (cleared on read)
EOC7
7
End of Conversion 7 (automatically set / cleared)
EOC6
6
End of Conversion 6 (automatically set / cleared)
EOC5
5
End of Conversion 5 (automatically set / cleared)
EOC4
4
End of Conversion 4 (automatically set / cleared)
EOC3
3
End of Conversion 3 (automatically set / cleared)
EOC2
2
End of Conversion 2 (automatically set / cleared)
EOC1
1
End of Conversion 1 (automatically set / cleared)
EOC0
0
End of Conversion 0 (automatically set / cleared)
ADC_LCTMRLast Channel Trigger Mode Register
Address
0x40038034
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
CMPMOD
5:4
Last Channel Comparison Mode
0 Generates an event when the converted data is lower than the low threshold of the window.
1 Generates an event when the converted data is higher than the high threshold of the window.
2 Generates an event when the converted data is in the comparison window.
3 Generates an event when the converted data is out of the comparison window.
DUALTRIG
0
Dual Trigger ON
ADC_LCCWRLast Channel Compare Window Register
Address
0x40038038
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
HIGHTHRES
27:16
High Threshold
LOWTHRES
11:0
Low Threshold
ADC_OVEROverrun Status Register
Address
0x4003803C
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
Field
Bits
What it does
OVRE7
7
Overrun Error 7
OVRE6
6
Overrun Error 6
OVRE5
5
Overrun Error 5
OVRE4
4
Overrun Error 4
OVRE3
3
Overrun Error 3
OVRE2
2
Overrun Error 2
OVRE1
1
Overrun Error 1
OVRE0
0
Overrun Error 0
ADC_EMRExtended Mode Register
Address
0x40038040
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
TAG
24
Tag of the ADC_LCDR
ASTE
20
Averaging on Single Trigger Event
0 The average requests several trigger events.
1 The average requests only one trigger event.
OSR
17:16
Over Sampling Rate
0 No averaging. ADC sample rate is maximum.
1 1-bit enhanced resolution by averaging. ADC sample rate divided by 4.
2 2-bit enhanced resolution by averaging. ADC sample rate divided by 16.
CMPFILTER
13:12
Compare Event Filtering
CMPALL
9
Compare All Channels
CMPSEL
7:4
Comparison Selected Channel
CMPMODE
1:0
Comparison Mode
0 Generates an event when the converted data is lower than the low threshold of the window.
1 Generates an event when the converted data is higher than the high threshold of the window.
2 Generates an event when the converted data is in the comparison window.
3 Generates an event when the converted data is out of the comparison window.
ADC_CWRCompare Window Register
Address
0x40038044
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
HIGHTHRES
27:16
High Threshold
LOWTHRES
11:0
Low Threshold
ADC_CDR0Channel Data Register 0
Address
0x40038050
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
DATA
11:0
Converted Data
ADC_CDR1Channel Data Register 0
Address
0x40038054
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
DATA
11:0
Converted Data
ADC_CDR2Channel Data Register 0
Address
0x40038058
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
DATA
11:0
Converted Data
ADC_CDR3Channel Data Register 0
Address
0x4003805C
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
DATA
11:0
Converted Data
ADC_CDR4Channel Data Register 0
Address
0x40038060
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
DATA
11:0
Converted Data
ADC_CDR5Channel Data Register 0
Address
0x40038064
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
DATA
11:0
Converted Data
ADC_CDR6Channel Data Register 0
Address
0x40038068
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
DATA
11:0
Converted Data
ADC_CDR7Channel Data Register 0
Address
0x4003806C
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
DATA
11:0
Converted Data
ADC_WPMRWrite Protection Mode Register
Address
0x400380E4
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
WPEN
0
Write Protection Enable
WPKEY
31:8
Write Protection Key
4277315 Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0
BETA