ATSAMG51G18 TWI0 registers

The 25 registers of TWI0 (Two-wire Interface High Speed), from 0x40018000, with their reset value and every field. The ATSAMG51G18 has 569 registers in 26 peripherals, one page each.

TWI0 Two-wire Interface High Speed

TWIHS_CRControl Register

Address
0x40018000
Reset
0x00000000
Access
write only
Size
32-bit
16 fields
FieldBitsWhat it does
CLEAR15Bus CLEAR Command
PECRQ14PEC Request
PECDIS13Packet Error Checking Disable
PECEN12Packet Error Checking Enable
SMBDIS11SMBus Mode Disabled
SMBEN10SMBus Mode Enabled
HSDIS9TWIHS High-Speed Mode Disabled
HSEN8TWIHS High-Speed Mode Enabled
SWRST7Software Reset
QUICK6SMBus Quick Command
SVDIS5TWIHS Slave Mode Disabled
SVEN4TWIHS Slave Mode Enabled
MSDIS3TWIHS Master Mode Disabled
MSEN2TWIHS Master Mode Enabled
STOP1Send a STOP Condition
START0Send a START Condition

TWIHS_MMRMaster Mode Register

Address
0x40018004
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
DADR22:16Device Address
MREAD12Master Read Direction
IADRSZ9:8Internal Device Address Size
  • 0 No internal device address
  • 1 One-byte internal device address
  • 2 Two-byte internal device address
  • 3 Three-byte internal device address

TWIHS_SMRSlave Mode Register

Address
0x40018008
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
SADR22:16Slave Address
MASK14:8Slave Address Mask
SCLWSDIS6Clock Wait State Disable
SMHH3SMBus Host Header
SMDA2SMBus Default Address
NACKEN0Slave Receiver Data Phase NACK enable

TWIHS_IADRInternal Address Register

Address
0x4001800C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
IADR23:0Internal Address

TWIHS_CWGRClock Waveform Generator Register

Address
0x40018010
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
HOLD28:24TWD Hold Time Versus TWCK Falling
CKDIV18:16Clock Divider
CHDIV15:8Clock High Divider
CLDIV7:0Clock Low Divider

TWIHS_SRStatus Register

Address
0x40018020
Reset
0x00000000
Access
read only
Size
32-bit
23 fields
FieldBitsWhat it does
SDA25SDA line value
SCL24SCL line value
SMBHHM21SMBus Host Header Address Match (cleared on read)
SMBDAM20SMBus Default Address Match (cleared on read)
PECERR19PEC Error (cleared on read)
TOUT18Timeout Error (cleared on read)
MCACK16Master Code Acknowledge (cleared on read)
TXBUFE15TX Buffer Empty (cleared by writing TWIHS_TCR or TWIHS_TNCR)
RXBUFF14RX Buffer Full (cleared by writing TWIHS_RCR or TWIHS_RNCR)
ENDTX13End of TX Buffer (cleared by writing TWIHS_TCR or TWIHS_TNCR)
ENDRX12End of RX Buffer (cleared by writing TWIHS_RCR or TWIHS_RNCR)
EOSACC11End Of Slave Access (cleared on read)
SCLWS10Clock Wait State
ARBLST9Arbitration Lost (cleared on read)
NACK8Not Acknowledged (cleared on read)
UNRE7Underrun Error (cleared on read)
OVRE6Overrun Error (cleared on read)
GACC5General Call Access (cleared on read)
SVACC4Slave Access
SVREAD3Slave Read
TXRDY2Transmit Holding Register Ready (cleared by writing TWIHS_THR)
RXRDY1Receive Holding Register Ready (cleared by reading TWIHS_RHR)
TXCOMP0Transmission Completed (cleared by writing TWIHS_THR)

TWIHS_IERInterrupt Enable Register

Address
0x40018024
Reset
0x00000000
Access
write only
Size
32-bit
20 fields
FieldBitsWhat it does
SMBHHM21SMBus Host Header Address Match Interrupt Enable
SMBDAM20SMBus Default Address Match Interrupt Enable
PECERR19PEC Error Interrupt Enable
TOUT18Timeout Error Interrupt Enable
MCACK16Master Code Acknowledge Interrupt Enable
TXBUFE15Transmit Buffer Empty Interrupt Enable
RXBUFF14Receive Buffer Full Interrupt Enable
ENDTX13End of Transmit Buffer Interrupt Enable
ENDRX12End of Receive Buffer Interrupt Enable
EOSACC11End Of Slave Access Interrupt Enable
SCL_WS10Clock Wait State Interrupt Enable
ARBLST9Arbitration Lost Interrupt Enable
NACK8Not Acknowledge Interrupt Enable
UNRE7Underrun Error Interrupt Enable
OVRE6Overrun Error Interrupt Enable
GACC5General Call Access Interrupt Enable
SVACC4Slave Access Interrupt Enable
TXRDY2Transmit Holding Register Ready Interrupt Enable
RXRDY1Receive Holding Register Ready Interrupt Enable
TXCOMP0Transmission Completed Interrupt Enable

TWIHS_IDRInterrupt Disable Register

Address
0x40018028
Reset
0x00000000
Access
write only
Size
32-bit
20 fields
FieldBitsWhat it does
SMBHHM21SMBus Host Header Address Match Interrupt Disable
SMBDAM20SMBus Default Address Match Interrupt Disable
PECERR19PEC Error Interrupt Disable
TOUT18Timeout Error Interrupt Disable
MCACK16Master Code Acknowledge Interrupt Disable
TXBUFE15Transmit Buffer Empty Interrupt Disable
RXBUFF14Receive Buffer Full Interrupt Disable
ENDTX13End of Transmit Buffer Interrupt Disable
ENDRX12End of Receive Buffer Interrupt Disable
EOSACC11End Of Slave Access Interrupt Disable
SCL_WS10Clock Wait State Interrupt Disable
ARBLST9Arbitration Lost Interrupt Disable
NACK8Not Acknowledge Interrupt Disable
UNRE7Underrun Error Interrupt Disable
OVRE6Overrun Error Interrupt Disable
GACC5General Call Access Interrupt Disable
SVACC4Slave Access Interrupt Disable
TXRDY2Transmit Holding Register Ready Interrupt Disable
RXRDY1Receive Holding Register Ready Interrupt Disable
TXCOMP0Transmission Completed Interrupt Disable

TWIHS_IMRInterrupt Mask Register

Address
0x4001802C
Reset
0x00000000
Access
read only
Size
32-bit
20 fields
FieldBitsWhat it does
SMBHHM21SMBus Host Header Address Match Interrupt Mask
SMBDAM20SMBus Default Address Match Interrupt Mask
PECERR19PEC Error Interrupt Mask
TOUT18Timeout Error Interrupt Mask
MCACK16Master Code Acknowledge Interrupt Mask
TXBUFE15Transmit Buffer Empty Interrupt Mask
RXBUFF14Receive Buffer Full Interrupt Mask
ENDTX13End of Transmit Buffer Interrupt Mask
ENDRX12End of Receive Buffer Interrupt Mask
EOSACC11End Of Slave Access Interrupt Mask
SCL_WS10Clock Wait State Interrupt Mask
ARBLST9Arbitration Lost Interrupt Mask
NACK8Not Acknowledge Interrupt Mask
UNRE7Underrun Error Interrupt Mask
OVRE6Overrun Error Interrupt Mask
GACC5General Call Access Interrupt Mask
SVACC4Slave Access Interrupt Mask
TXRDY2Transmit Holding Register Ready Interrupt Mask
RXRDY1Receive Holding Register Ready Interrupt Mask
TXCOMP0Transmission Completed Interrupt Mask

TWIHS_RHRReceive Holding Register

Address
0x40018030
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
RXDATA7:0Master or Slave Receive Holding Data

TWIHS_THRTransmit Holding Register

Address
0x40018034
Reset
0x00000000
Access
write only
Size
32-bit
1 field
FieldBitsWhat it does
TXDATA7:0Master or Slave Transmit Holding Data

TWIHS_SMBTRSMBus Timing Register

Address
0x40018038
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TLOWM23:16Master Clock Stretch Maximum Cycles
TLOWS15:8Slave Clock Stretch Maximum Cycles
PRESC3:0SMBus Clock Prescaler
THMAX31:24Clock High Maximum Cycles

TWIHS_FILTRFilter Register

Address
0x40018044
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
THRES10:8Digital Filter Threshold
PADFCFG2PAD Filter Config
PADFEN1PAD Filter Enable
FILT0RX Digital Filter

TWIHS_WPMRWrite Protection Mode Register

Address
0x400180E4
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
WPEN0Write Protection Enable
WPKEY31:8Write Protection Key
  • 5527369 Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0

TWIHS_WPSRWrite Protection Status Register

Address
0x400180E8
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
WPVS0Write Protection Violation Status
WPVSRC31:8Write Protection Violation Source

TWIHS_RPRReceive Pointer Register

Address
0x40018100
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXPTR31:0Receive Pointer Register

TWIHS_RCRReceive Counter Register

Address
0x40018104
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXCTR15:0Receive Counter Register

TWIHS_TPRTransmit Pointer Register

Address
0x40018108
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXPTR31:0Transmit Counter Register

TWIHS_TCRTransmit Counter Register

Address
0x4001810C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXCTR15:0Transmit Counter Register

TWIHS_RNPRReceive Next Pointer Register

Address
0x40018110
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXNPTR31:0Receive Next Pointer

TWIHS_RNCRReceive Next Counter Register

Address
0x40018114
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXNCTR15:0Receive Next Counter

TWIHS_TNPRTransmit Next Pointer Register

Address
0x40018118
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXNPTR31:0Transmit Next Pointer

TWIHS_TNCRTransmit Next Counter Register

Address
0x4001811C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXNCTR15:0Transmit Counter Next

TWIHS_PTCRTransfer Control Register

Address
0x40018120
Reset
0x00000000
Access
write only
Size
32-bit
4 fields
FieldBitsWhat it does
TXTDIS9Transmitter Transfer Disable
TXTEN8Transmitter Transfer Enable
RXTDIS1Receiver Transfer Disable
RXTEN0Receiver Transfer Enable

TWIHS_PTSRTransfer Status Register

Address
0x40018124
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
TXTEN8Transmitter Transfer Enable
RXTEN0Receiver Transfer Enable