ATSAMG51N18 SystemControl registers

The 17 registers of SystemControl (System Control Registers), from 0xE000E008, with their reset value and every field. The ATSAMG51N18 has 569 registers in 26 peripherals, one page each.

SystemControl System Control Registers

ACTLRAuxiliary Control Register,

Address
0xE000E008
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
DISFOLD2Disables folding of IT instructions.
DISDEFWBUF1Disables write buffer use during default memory map accesses.
DISMCYCINT0Disables interruption of multi-cycle instructions.

CPUIDCPUID Base Register

Address
0xE000ED00
Reset
0x410FC240
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
VARIANT23:20Indicates processor revision: 0x2 = Revision 2
PARTNO15:4Indicates part number
REVISION3:0Indicates patch release: 0x0 = Patch 0
IMPLEMENTER31:24Implementer code

ICSRInterrupt Control and State Register

Address
0xE000ED04
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
FieldBitsWhat it does
PENDSVSET28no description available
  • 0 write: no effect; read: PendSV exception is not pending
  • 1 write: changes PendSV exception state to pending; read: PendSV exception is pending
PENDSVCLR27no description available
  • 0 no effect
  • 1 removes the pending state from the PendSV exception
PENDSTSET26no description available
  • 0 write: no effect; read: SysTick exception is not pending
  • 1 write: changes SysTick exception state to pending; read: SysTick exception is pending
PENDSTCLR25no description available
  • 0 no effect
  • 1 removes the pending state from the SysTick exception
ISRPREEMPT23no description available
  • 0 Will not service
  • 1 Will service a pending exception
ISRPENDING22no description available
VECTPENDING17:12Exception number of the highest priority pending enabled exception
RETTOBASE11no description available
  • 0 there are preempted active exceptions to execute
  • 1 there are no active exceptions, or the currently-executing exception is the only active exception
VECTACTIVE8:0Active exception number
NMIPENDSET31no description available
  • 0 write: no effect; read: NMI exception is not pending
  • 1 write: changes NMI exception state to pending; read: NMI exception is pending

VTORVector Table Offset Register

Address
0xE000ED08
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TBLOFF31:7Vector table base offset

AIRCRApplication Interrupt and Reset Control Register

Address
0xE000ED0C
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
ENDIANNESS15no description available
  • 0 Little-endian
  • 1 Big-endian
PRIGROUP10:8Interrupt priority grouping field. This field determines the split of group priority from subpriority.
SYSRESETREQ2no description available
  • 0 no system reset request
  • 1 asserts a signal to the outer system that requests a reset
VECTCLRACTIVE1no description available
VECTRESET0no description available
VECTKEY31:16Register key

SCRSystem Control Register

Address
0xE000ED10
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
SEVONPEND4no description available
  • 0 only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
  • 1 enabled events and all interrupts, including disabled interrupts, can wakeup the processor
SLEEPDEEP2no description available
  • 0 sleep
  • 1 deep sleep
SLEEPONEXIT1no description available
  • 0 o not sleep when returning to Thread mode
  • 1 enter sleep, or deep sleep, on return from an ISR

CCRConfiguration and Control Register

Address
0xE000ED14
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
STKALIGN9Indicates stack alignment on exception entry
  • 0 4-byte aligned
  • 1 8-byte aligned
BFHFNMIGN8Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions.
  • 0 data bus faults caused by load and store instructions cause a lock-up
  • 1 handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions
DIV_0_TRP4Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0
  • 0 do not trap divide by 0
  • 1 trap divide by 0
UNALIGN_TRP3Enables unaligned access traps
  • 0 do not trap unaligned halfword and word accesses
  • 1 trap unaligned halfword and word accesses
USERSETMPEND1Enables unprivileged software access to the STIR
  • 0 disable
  • 1 enable
NONBASETHRDENA0no description available
  • 0 processor can enter Thread mode only when no exception is active
  • 1 processor can enter Thread mode from any level under the control of an EXC_RETURN value

SHPR1System Handler Priority Register 1

Address
0xE000ED18
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
PRI_623:16Priority of system handler 6, UsageFault
PRI_515:8Priority of system handler 5, BusFault
PRI_47:0Priority of system handler 4, MemManage

SHPR2System Handler Priority Register 2

Address
0xE000ED1C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PRI_1131:24Priority of system handler 11, SVCall

SHPR3System Handler Priority Register 3

Address
0xE000ED20
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
PRI_1423:16Priority of system handler 14, PendSV
PRI_1531:24Priority of system handler 15, SysTick exception

SHCSRSystem Handler Control and State Register

Address
0xE000ED24
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
USGFAULTENA18no description available
  • 0 disable the exception
  • 1 enable the exception
BUSFAULTENA17no description available
  • 0 disable the exception
  • 1 enable the exception
MEMFAULTENA16no description available
  • 0 disable the exception
  • 1 enable the exception
SVCALLPENDED15no description available
  • 0 exception is not pending
  • 1 exception is pending
BUSFAULTPENDED14no description available
  • 0 exception is not pending
  • 1 exception is pending
MEMFAULTPENDED13no description available
  • 0 exception is not pending
  • 1 exception is pending
USGFAULTPENDED12no description available
  • 0 exception is not pending
  • 1 exception is pending
SYSTICKACT11no description available
  • 0 exception is not active
  • 1 exception is active
PENDSVACT10no description available
  • 0 exception is not active
  • 1 exception is active
MONITORACT8no description available
  • 0 exception is not active
  • 1 exception is active
SVCALLACT7no description available
  • 0 exception is not active
  • 1 exception is active
USGFAULTACT3no description available
  • 0 exception is not active
  • 1 exception is active
BUSFAULTACT1no description available
  • 0 exception is not active
  • 1 exception is active
MEMFAULTACT0no description available
  • 0 exception is not active
  • 1 exception is active

CFSRConfigurable Fault Status Registers

Address
0xE000ED28
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
DIVBYZERO25no description available
  • 0 no divide by zero fault, or divide by zero trapping not enabled
  • 1 the processor has executed an SDIV or UDIV instruction with a divisor of 0
UNALIGNED24no description available
  • 0 no unaligned access fault, or unaligned access trapping not enabled
  • 1 the processor has made an unaligned memory access
NOCP19no description available
  • 0 no UsageFault caused by attempting to access a coprocessor
  • 1 the processor has attempted to access a coprocessor
INVPC18no description available
  • 0 no invalid PC load UsageFault
  • 1 the processor has attempted an illegal load of EXC_RETURN to the PC
INVSTATE17no description available
  • 0 no invalid state UsageFault
  • 1 the processor has attempted to execute an instruction that makes illegal use of the EPSR
UNDEFINSTR16no description available
  • 0 no undefined instruction UsageFault
  • 1 the processor has attempted to execute an undefined instruction
BFARVALID15no description available
  • 0 value in BFAR is not a valid fault address
  • 1 BFAR holds a valid fault address
LSPERR13no description available
  • 0 No bus fault occurred during floating-point lazy state preservation
  • 1 A bus fault occurred during floating-point lazy state preservation
STKERR12no description available
  • 0 no stacking fault
  • 1 stacking for an exception entry has caused one or more BusFaults
UNSTKERR11no description available
  • 0 no unstacking fault
  • 1 unstack for an exception return has caused one or more BusFaults
IMPRECISERR10no description available
  • 0 no imprecise data bus error
  • 1 a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error
PRECISERR9no description available
  • 0 no precise data bus error
  • 1 a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault
IBUSERR8no description available
  • 0 no instruction bus error
  • 1 instruction bus error
MMARVALID7no description available
  • 0 value in MMAR is not a valid fault address
  • 1 MMAR holds a valid fault address
MLSPERR5no description available
  • 0 No MemManage fault occurred during floating-point lazy state preservation
  • 1 A MemManage fault occurred during floating-point lazy state preservation
MSTKERR4no description available
  • 0 no stacking fault
  • 1 stacking for an exception entry has caused one or more access violations
MUNSTKERR3no description available
  • 0 no unstacking fault
  • 1 unstack for an exception return has caused one or more access violations
DACCVIOL1no description available
  • 0 no data access violation fault
  • 1 the processor attempted a load or store at a location that does not permit the operation
IACCVIOL0no description available
  • 0 no instruction access violation fault
  • 1 the processor attempted an instruction fetch from a location that does not permit execution

HFSRHardFault Status register

Address
0xE000ED2C
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
FORCED30no description available
  • 0 no forced HardFault
  • 1 forced HardFault
VECTTBL1no description available
  • 0 no BusFault on vector table read
  • 1 BusFault on vector table read
DEBUGEVT31no description available

DFSRDebug Fault Status Register

Address
0xE000ED30
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EXTERNAL4no description available
  • 0 No EDBGRQ debug event
  • 1 EDBGRQ debug event
VCATCH3no description available
  • 0 No Vector catch triggered
  • 1 Vector catch triggered
DWTTRAP2no description available
  • 0 No current debug events generated by the DWT
  • 1 At least one current debug event generated by the DWT
BKPT1no description available
  • 0 No current breakpoint debug event
  • 1 At least one current breakpoint debug event
HALTED0no description available
  • 0 No active halt request debug event
  • 1 Halt request debug event active

MMFARMemManage Address Register

Address
0xE000ED34
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADDRESS31:0Address of MemManage fault location

BFARBusFault Address Register

Address
0xE000ED38
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADDRESS31:0Address of the BusFault location

AFSRAuxiliary Fault Status Register

Address
0xE000ED3C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
AUXFAULT31:0Latched version of the AUXFAULT inputs