The 30 registers of I2SC1 (Inter-IC Sound Controller), from 0x40004000, with their reset value and every field. The ATSAMG53G19 has 718 registers in 31 peripherals, one page each.
I2SC1 Inter-IC Sound Controller
I2SC_CRControl Register
Address
0x40004000
Reset
0x00000000
Access
write only
Size
32-bit
7 fields
Field
Bits
What it does
SWRST
7
Software Reset
TXDIS
5
Transmitter Disable
TXEN
4
Transmitter Enable
CKDIS
3
Clocks Disable
CKEN
2
Clocks Enable
RXDIS
1
Receiver Disable
RXEN
0
Receiver Enable
I2SC_MRMode Register
Address
0x40004004
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
IMCKMODE
30
Master Clock Mode
IMCKFS
29:24
Master Clock to fs Ratio
0 Sample frequency ratio set to 16
1 Sample frequency ratio set to 32
2 Sample frequency ratio set to 48
3 Sample frequency ratio set to 64
5 Sample frequency ratio set to 96
7 Sample frequency ratio set to 128
11 Sample frequency ratio set to 192
15 Sample frequency ratio set to 256
23 Sample frequency ratio set to 384
31 Sample frequency ratio set to 512
47 Sample frequency ratio set to 768
63 Sample frequency ratio set to 1024
IMCKDIV
21:16
Peripheral Clock to I2SC Master Clock Ratio
TXSAME
14
Transmit Data when Underrun
TXDMA
13
Single or Multiple PDC Channels for Transmitter
TXMONO
12
Transmit Mono
RXLOOP
10
Loop-back Test Mode
RXDMA
9
Single or Multiple PDC Channels for Receiver
RXMONO
8
Receive Mono
DATALENGTH
4:2
Data Word Length
0 Data length is set to 32 bits
1 Data length is set to 24 bits
2 Data length is set to 20 bits
3 Data length is set to 18 bits
4 Data length is set to 16 bits
5 Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word.
6 Data length is set to 8 bits
7 Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word.
MODE
0
Inter-IC Sound Controller Mode
0 I2SCK and i2SWS pin inputs used as bit clock and word select/frame synchronization.
1 Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SCK and I2SWS pins. MCK is output as master clock on I2SMCK if I2SC_MR.IMCKMODE is set.
IWS
31
I2SWS TDM Slot Width
I2SC_SRStatus Register
Address
0x40004008
Reset
0x00000000
Access
read only
Size
32-bit
12 fields
Field
Bits
What it does
TXURCH
21:20
Transmit Underrun Channel
RXBUFF
19
Receive Buffer Full
RXORCH
9:8
Receive Overrun Channel
ENDTX
7
End of Transmitter Transfer
TXUR
6
Transmit Underrun
TXRDY
5
Transmit Ready
TXEN
4
Transmitter Enabled
ENDRX
3
End of Receiver Transfer
RXOR
2
Receive Overrun
RXRDY
1
Receive Ready
RXEN
0
Receiver Enabled
TXBUFE
31
Transmit Buffer Empty
I2SC_SCRStatus Clear Register
Address
0x4000400C
Reset
0x00000000
Access
write only
Size
32-bit
4 fields
Field
Bits
What it does
TXURCH
21:20
Transmit Underrun Per Channel Status Clear
RXORCH
9:8
Receive Overrun Per Channel Status Clear
TXUR
6
Transmit Underrun Status Clear
RXOR
2
Receive Overrun Status Clear
I2SC_SSRStatus Set Register
Address
0x40004010
Reset
0x00000000
Access
write only
Size
32-bit
4 fields
Field
Bits
What it does
TXURCH
21:20
Transmit Underrun Per Channel Status Set
RXORCH
9:8
Receive Overrun Per Channel Status Set
TXUR
6
Transmit Underrun Status Set
RXOR
2
Receive Overrun Status Set
I2SC_IERInterrupt Enable Register
Address
0x40004014
Reset
0x00000000
Access
write only
Size
32-bit
8 fields
Field
Bits
What it does
RXFULL
19
Receive Buffer Full Interrupt Enable
ENDTX
7
End of Transmission Interrupt Enable
TXUR
6
Transmit Underflow Interrupt Enable
TXRDY
5
Transmit Ready Interrupt Enable
ENDRX
3
End of Reception Interrupt Enable
RXOR
2
Receiver Overrun Interrupt Enable
RXRDY
1
Receiver Ready Interrupt Enable
TXEMPTY
31
Transmit Buffer Empty Interrupt Enable
I2SC_IDRInterrupt Disable Register
Address
0x40004018
Reset
0x00000000
Access
write only
Size
32-bit
8 fields
Field
Bits
What it does
RXFULL
19
Receive Buffer Full Interrupt Disable
ENDTX
7
End of Transmission Interrupt Disable
TXUR
6
Transmit Underflow Interrupt Disable
TXRDY
5
Transmit Ready Interrupt Disable
ENDRX
3
End of Reception Interrupt Disable
RXOR
2
Receiver Overrun Interrupt Disable
RXRDY
1
Receiver Ready Interrupt Disable
TXEMPTY
31
Transmit Buffer Empty Interrupt Disable
I2SC_IMRInterrupt Mask Register
Address
0x4000401C
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
Field
Bits
What it does
RXFULL
19
Receive Buffer Full Interrupt Disable
ENDTX
7
End of Transmission Interrupt Disable
TXUR
6
Transmit Underflow Interrupt Disable
TXRDY
5
Transmit Ready Interrupt Disable
ENDRX
3
End of Reception Interrupt Disable
RXOR
2
Receiver Overrun Interrupt Disable
RXRDY
1
Receiver Ready Interrupt Disable
TXEMPTY
31
Transmit Buffer Empty Interrupt Disable
I2SC_RHRReceiver Holding Register
Address
0x40004020
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
RHR
31:0
Receiver Holding Register
I2SC_THRTransmitter Holding Register
Address
0x40004024
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
THR
31:0
Transmitter Holding Register
I2SC_RPRReceive Pointer Register - Left side
Address
0x40004100
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXPTR
31:0
Receive Pointer Register
I2SC_RCRReceive Counter Register - Left side
Address
0x40004104
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXCTR
15:0
Receive Counter Register
I2SC_TPRTransmit Pointer Register - Left side
Address
0x40004108
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXPTR
31:0
Transmit Counter Register
I2SC_TCRTransmit Counter Register - Left side
Address
0x4000410C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXCTR
15:0
Transmit Counter Register
I2SC_RNPRReceive Next Pointer Register - Left side
Address
0x40004110
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXNPTR
31:0
Receive Next Pointer
I2SC_RNCRReceive Next Counter Register - Left side
Address
0x40004114
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXNCTR
15:0
Receive Next Counter
I2SC_TNPRTransmit Next Pointer Register - Left side
Address
0x40004118
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXNPTR
31:0
Transmit Next Pointer
I2SC_TNCRTransmit Next Counter Register - Left side
Address
0x4000411C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXNCTR
15:0
Transmit Counter Next
I2SC_PTCRTransfer Control Register - Left side
Address
0x40004120
Reset
0x00000000
Access
write only
Size
32-bit
9 fields
Field
Bits
What it does
ERRCLR
24
Transfer Bus Error Clear
TXCBDIS
19
Transmitter Circular Buffer Disable
TXCBEN
18
Transmitter Circular Buffer Enable
RXCBDIS
17
Receiver Circular Buffer Disable
RXCBEN
16
Receiver Circular Buffer Enable
TXTDIS
9
Transmitter Transfer Disable
TXTEN
8
Transmitter Transfer Enable
RXTDIS
1
Receiver Transfer Disable
RXTEN
0
Receiver Transfer Enable
I2SC_PTSRTransfer Status Register - Left side
Address
0x40004124
Reset
0x00000000
Access
read only
Size
32-bit
5 fields
Field
Bits
What it does
ERR
24
Transfer Bus Error
TXCBEN
18
Transmitter Circular Buffer Enable
RXCBEN
16
Receiver Circular Buffer Enable
TXTEN
8
Transmitter Transfer Enable
RXTEN
0
Receiver Transfer Enable
I2SC_RPR_RIGHTReceive Pointer Register - Right side
Address
0x40004200
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXPTR
31:0
Receive Pointer Register
I2SC_RCR_RIGHTReceive Counter Register - Right side
Address
0x40004204
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXCTR
15:0
Receive Counter Register
I2SC_TPR_RIGHTTransmit Pointer Register - Right side
Address
0x40004208
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXPTR
31:0
Transmit Counter Register
I2SC_TCR_RIGHTTransmit Counter Register - Right side
Address
0x4000420C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXCTR
15:0
Transmit Counter Register
I2SC_RNPR_RIGHTReceive Next Pointer Register - Right side
Address
0x40004210
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXNPTR
31:0
Receive Next Pointer
I2SC_RNCR_RIGHTReceive Next Counter Register - Right side
Address
0x40004214
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXNCTR
15:0
Receive Next Counter
I2SC_TNPR_RIGHTTransmit Next Pointer Register - Right side
Address
0x40004218
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXNPTR
31:0
Transmit Next Pointer
I2SC_TNCR_RIGHTTransmit Next Counter Register - Right side
Address
0x4000421C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXNCTR
15:0
Transmit Counter Next
I2SC_PTCR_RIGHTTransfer Control Register - Right side
Address
0x40004220
Reset
0x00000000
Access
write only
Size
32-bit
9 fields
Field
Bits
What it does
ERRCLR
24
Transfer Bus Error Clear
TXCBDIS
19
Transmitter Circular Buffer Disable
TXCBEN
18
Transmitter Circular Buffer Enable
RXCBDIS
17
Receiver Circular Buffer Disable
RXCBEN
16
Receiver Circular Buffer Enable
TXTDIS
9
Transmitter Transfer Disable
TXTEN
8
Transmitter Transfer Enable
RXTDIS
1
Receiver Transfer Disable
RXTEN
0
Receiver Transfer Enable
I2SC_PTSR_RIGHTTransfer Status Register - Right side
BETA