ATSAMG53N19 TC0 registers The 44 registers of TC0 (Timer Counter), from 0x40010000, with their reset value and every field. The ATSAMG53N19 has 718 registers in 31 peripherals, one page each.
TC0 Timer Counter TC_CHANNEL0.TC_CCRChannel Control Register (channel = 0)
Address 0x40010000
Reset 0x00000000
Access write only
Size 32-bit 3 fields
Field Bits What it does SWTRG 2 Software Trigger Command CLKDIS 1 Counter Clock Disable Command CLKEN 0 Counter Clock Enable Command
TC_CHANNEL0.TC_CMRChannel Mode Register (channel = 0)
Address 0x40010004
Reset 0x00000000
Access read/write
Size 32-bit 26 fields
Field Bits What it does BEEVT 29:28 External Event Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE BCPC 27:26 RC Compare Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE BCPB 25:24 RB Compare Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE ASWTRG 23:22 Software Trigger Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE SBSMPLR 22:20 Loading Edge Subsampling Ratio0 Load a Capture Register each selected edge1 Load a Capture Register every 2 selected edges2 Load a Capture Register every 4 selected edges3 Load a Capture Register every 8 selected edges4 Load a Capture Register every 16 selected edges AEEVT 21:20 External Event Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE ACPC 19:18 RC Compare Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE LDRB 19:18 RB Loading Edge Selection0 None1 Rising edge of TIOA2 Falling edge of TIOA3 Each edge of TIOA ACPA 17:16 RA Compare Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE LDRA 17:16 RA Loading Edge Selection0 None1 Rising edge of TIOA2 Falling edge of TIOA3 Each edge of TIOA WAVE 15 Waveform Mode WAVSEL 14:13 Waveform Selection0 UP mode without automatic trigger on RC Compare1 UPDOWN mode without automatic trigger on RC Compare2 UP mode with automatic trigger on RC Compare3 UPDOWN mode with automatic trigger on RC Compare CPCTRG 14 RC Compare Trigger Enable ENETRG 12 External Event Trigger Enable EEVT 11:10 External Event Selection ABETRG 10 TIOAx or TIOBx External Trigger Selection EEVTEDG 9:8 External Event Edge Selection0 None1 Rising edge2 Falling edge3 Each edges ETRGEDG 9:8 External Trigger Edge Selection0 The clock is not gated by an external signal.1 Rising edge2 Falling edge3 Each edge CPCDIS 7 Counter Clock Disable with RC Loading LDBDIS 7 Counter Clock Disable with RB Loading CPCSTOP 6 Counter Clock Stopped with RC Compare LDBSTOP 6 Counter Clock Stopped with RB Loading BURST 5:4 Burst Signal Selection0 The clock is not gated by an external signal.1 XC0 is ANDed with the selected clock.2 XC1 is ANDed with the selected clock.3 XC2 is ANDed with the selected clock. CLKI 3 Clock Invert TCCLKS 2:0 Clock Selection0 Clock selected: internal MCK/2 clock signal (from PMC)1 Clock selected: internal MCK/8 clock signal (from PMC)2 Clock selected: internal MCK/32 clock signal (from PMC)3 Clock selected: internal MCK/128 clock signal (from PMC)4 Clock selected: internal SLCK clock signal (from PMC)5 Clock selected: XC06 Clock selected: XC17 Clock selected: XC2 BSWTRG 31:30 Software Trigger Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE
TC_CHANNEL0.TC_SMMRStepper Motor Mode Register (channel = 0)
Address 0x40010008
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does DOWN 1 Down Count GCEN 0 Gray Count Enable
TC_CHANNEL0.TC_RABRegister AB (channel = 0)
Address 0x4001000C
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does RAB 31:0 Register A or Register B
TC_CHANNEL0.TC_CVCounter Value (channel = 0)
Address 0x40010010
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CV 31:0 Counter Value
TC_CHANNEL0.TC_RARegister A (channel = 0)
Address 0x40010014
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RA 31:0 Register A
TC_CHANNEL0.TC_RBRegister B (channel = 0)
Address 0x40010018
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RB 31:0 Register B
TC_CHANNEL0.TC_RCRegister C (channel = 0)
Address 0x4001001C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RC 31:0 Register C
TC_CHANNEL0.TC_SRStatus Register (channel = 0)
Address 0x40010020
Reset 0x00000000
Access read only
Size 32-bit 13 fields
Field Bits What it does MTIOB 18 TIOB Mirror MTIOA 17 TIOA Mirror CLKSTA 16 Clock Enabling Status RXBUFF 9 Reception Buffer Full (cleared by writing TC_RCR or TC_RNCR) ENDRX 8 End of Receiver Transfer (cleared by writing TC_RCR or TC_RNCR) ETRGS 7 External Trigger Status (cleared on read) LDRBS 6 RB Loading Status (cleared on read) LDRAS 5 RA Loading Status (cleared on read) CPCS 4 RC Compare Status (cleared on read) CPBS 3 RB Compare Status (cleared on read) CPAS 2 RA Compare Status (cleared on read) LOVRS 1 Load Overrun Status (cleared on read) COVFS 0 Counter Overflow Status (cleared on read)
TC_CHANNEL0.TC_IERInterrupt Enable Register (channel = 0)
Address 0x40010024
Reset 0x00000000
Access write only
Size 32-bit 10 fields
Field Bits What it does RXBUFF 9 Reception Buffer Full ENDRX 8 End of Receiver Transfer ETRGS 7 External Trigger LDRBS 6 RB Loading LDRAS 5 RA Loading CPCS 4 RC Compare CPBS 3 RB Compare CPAS 2 RA Compare LOVRS 1 Load Overrun COVFS 0 Counter Overflow
TC_CHANNEL0.TC_IDRInterrupt Disable Register (channel = 0)
Address 0x40010028
Reset 0x00000000
Access write only
Size 32-bit 10 fields
Field Bits What it does RXBUFF 9 Reception Buffer Full ENDRX 8 End of Receiver Transfer ETRGS 7 External Trigger LDRBS 6 RB Loading LDRAS 5 RA Loading CPCS 4 RC Compare CPBS 3 RB Compare CPAS 2 RA Compare LOVRS 1 Load Overrun COVFS 0 Counter Overflow
TC_CHANNEL0.TC_IMRInterrupt Mask Register (channel = 0)
Address 0x4001002C
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does RXBUFF 9 Reception Buffer Full ENDRX 8 End of Receiver Transfer ETRGS 7 External Trigger LDRBS 6 RB Loading LDRAS 5 RA Loading CPCS 4 RC Compare CPBS 3 RB Compare CPAS 2 RA Compare LOVRS 1 Load Overrun COVFS 0 Counter Overflow
TC_CHANNEL1.TC_CCRChannel Control Register (channel = 0)
Address 0x40010040
Reset 0x00000000
Access write only
Size 32-bit 3 fields
Field Bits What it does SWTRG 2 Software Trigger Command CLKDIS 1 Counter Clock Disable Command CLKEN 0 Counter Clock Enable Command
TC_CHANNEL1.TC_CMRChannel Mode Register (channel = 0)
Address 0x40010044
Reset 0x00000000
Access read/write
Size 32-bit 26 fields
Field Bits What it does BEEVT 29:28 External Event Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE BCPC 27:26 RC Compare Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE BCPB 25:24 RB Compare Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE ASWTRG 23:22 Software Trigger Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE SBSMPLR 22:20 Loading Edge Subsampling Ratio0 Load a Capture Register each selected edge1 Load a Capture Register every 2 selected edges2 Load a Capture Register every 4 selected edges3 Load a Capture Register every 8 selected edges4 Load a Capture Register every 16 selected edges AEEVT 21:20 External Event Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE ACPC 19:18 RC Compare Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE LDRB 19:18 RB Loading Edge Selection0 None1 Rising edge of TIOA2 Falling edge of TIOA3 Each edge of TIOA ACPA 17:16 RA Compare Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE LDRA 17:16 RA Loading Edge Selection0 None1 Rising edge of TIOA2 Falling edge of TIOA3 Each edge of TIOA WAVE 15 Waveform Mode WAVSEL 14:13 Waveform Selection0 UP mode without automatic trigger on RC Compare1 UPDOWN mode without automatic trigger on RC Compare2 UP mode with automatic trigger on RC Compare3 UPDOWN mode with automatic trigger on RC Compare CPCTRG 14 RC Compare Trigger Enable ENETRG 12 External Event Trigger Enable EEVT 11:10 External Event Selection ABETRG 10 TIOAx or TIOBx External Trigger Selection EEVTEDG 9:8 External Event Edge Selection0 None1 Rising edge2 Falling edge3 Each edges ETRGEDG 9:8 External Trigger Edge Selection0 The clock is not gated by an external signal.1 Rising edge2 Falling edge3 Each edge CPCDIS 7 Counter Clock Disable with RC Loading LDBDIS 7 Counter Clock Disable with RB Loading CPCSTOP 6 Counter Clock Stopped with RC Compare LDBSTOP 6 Counter Clock Stopped with RB Loading BURST 5:4 Burst Signal Selection0 The clock is not gated by an external signal.1 XC0 is ANDed with the selected clock.2 XC1 is ANDed with the selected clock.3 XC2 is ANDed with the selected clock. CLKI 3 Clock Invert TCCLKS 2:0 Clock Selection0 Clock selected: internal MCK/2 clock signal (from PMC)1 Clock selected: internal MCK/8 clock signal (from PMC)2 Clock selected: internal MCK/32 clock signal (from PMC)3 Clock selected: internal MCK/128 clock signal (from PMC)4 Clock selected: internal SLCK clock signal (from PMC)5 Clock selected: XC06 Clock selected: XC17 Clock selected: XC2 BSWTRG 31:30 Software Trigger Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE
TC_CHANNEL1.TC_SMMRStepper Motor Mode Register (channel = 0)
Address 0x40010048
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does DOWN 1 Down Count GCEN 0 Gray Count Enable
TC_CHANNEL1.TC_RABRegister AB (channel = 0)
Address 0x4001004C
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does RAB 31:0 Register A or Register B
TC_CHANNEL1.TC_CVCounter Value (channel = 0)
Address 0x40010050
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CV 31:0 Counter Value
TC_CHANNEL1.TC_RARegister A (channel = 0)
Address 0x40010054
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RA 31:0 Register A
TC_CHANNEL1.TC_RBRegister B (channel = 0)
Address 0x40010058
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RB 31:0 Register B
TC_CHANNEL1.TC_RCRegister C (channel = 0)
Address 0x4001005C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RC 31:0 Register C
TC_CHANNEL1.TC_SRStatus Register (channel = 0)
Address 0x40010060
Reset 0x00000000
Access read only
Size 32-bit 13 fields
Field Bits What it does MTIOB 18 TIOB Mirror MTIOA 17 TIOA Mirror CLKSTA 16 Clock Enabling Status RXBUFF 9 Reception Buffer Full (cleared by writing TC_RCR or TC_RNCR) ENDRX 8 End of Receiver Transfer (cleared by writing TC_RCR or TC_RNCR) ETRGS 7 External Trigger Status (cleared on read) LDRBS 6 RB Loading Status (cleared on read) LDRAS 5 RA Loading Status (cleared on read) CPCS 4 RC Compare Status (cleared on read) CPBS 3 RB Compare Status (cleared on read) CPAS 2 RA Compare Status (cleared on read) LOVRS 1 Load Overrun Status (cleared on read) COVFS 0 Counter Overflow Status (cleared on read)
TC_CHANNEL1.TC_IERInterrupt Enable Register (channel = 0)
Address 0x40010064
Reset 0x00000000
Access write only
Size 32-bit 10 fields
Field Bits What it does RXBUFF 9 Reception Buffer Full ENDRX 8 End of Receiver Transfer ETRGS 7 External Trigger LDRBS 6 RB Loading LDRAS 5 RA Loading CPCS 4 RC Compare CPBS 3 RB Compare CPAS 2 RA Compare LOVRS 1 Load Overrun COVFS 0 Counter Overflow
TC_CHANNEL1.TC_IDRInterrupt Disable Register (channel = 0)
Address 0x40010068
Reset 0x00000000
Access write only
Size 32-bit 10 fields
Field Bits What it does RXBUFF 9 Reception Buffer Full ENDRX 8 End of Receiver Transfer ETRGS 7 External Trigger LDRBS 6 RB Loading LDRAS 5 RA Loading CPCS 4 RC Compare CPBS 3 RB Compare CPAS 2 RA Compare LOVRS 1 Load Overrun COVFS 0 Counter Overflow
TC_CHANNEL1.TC_IMRInterrupt Mask Register (channel = 0)
Address 0x4001006C
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does RXBUFF 9 Reception Buffer Full ENDRX 8 End of Receiver Transfer ETRGS 7 External Trigger LDRBS 6 RB Loading LDRAS 5 RA Loading CPCS 4 RC Compare CPBS 3 RB Compare CPAS 2 RA Compare LOVRS 1 Load Overrun COVFS 0 Counter Overflow
TC_CHANNEL2.TC_CCRChannel Control Register (channel = 0)
Address 0x40010080
Reset 0x00000000
Access write only
Size 32-bit 3 fields
Field Bits What it does SWTRG 2 Software Trigger Command CLKDIS 1 Counter Clock Disable Command CLKEN 0 Counter Clock Enable Command
TC_CHANNEL2.TC_CMRChannel Mode Register (channel = 0)
Address 0x40010084
Reset 0x00000000
Access read/write
Size 32-bit 26 fields
Field Bits What it does BEEVT 29:28 External Event Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE BCPC 27:26 RC Compare Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE BCPB 25:24 RB Compare Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE ASWTRG 23:22 Software Trigger Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE SBSMPLR 22:20 Loading Edge Subsampling Ratio0 Load a Capture Register each selected edge1 Load a Capture Register every 2 selected edges2 Load a Capture Register every 4 selected edges3 Load a Capture Register every 8 selected edges4 Load a Capture Register every 16 selected edges AEEVT 21:20 External Event Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE ACPC 19:18 RC Compare Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE LDRB 19:18 RB Loading Edge Selection0 None1 Rising edge of TIOA2 Falling edge of TIOA3 Each edge of TIOA ACPA 17:16 RA Compare Effect on TIOAx0 NONE1 SET2 CLEAR3 TOGGLE LDRA 17:16 RA Loading Edge Selection0 None1 Rising edge of TIOA2 Falling edge of TIOA3 Each edge of TIOA WAVE 15 Waveform Mode WAVSEL 14:13 Waveform Selection0 UP mode without automatic trigger on RC Compare1 UPDOWN mode without automatic trigger on RC Compare2 UP mode with automatic trigger on RC Compare3 UPDOWN mode with automatic trigger on RC Compare CPCTRG 14 RC Compare Trigger Enable ENETRG 12 External Event Trigger Enable EEVT 11:10 External Event Selection ABETRG 10 TIOAx or TIOBx External Trigger Selection EEVTEDG 9:8 External Event Edge Selection0 None1 Rising edge2 Falling edge3 Each edges ETRGEDG 9:8 External Trigger Edge Selection0 The clock is not gated by an external signal.1 Rising edge2 Falling edge3 Each edge CPCDIS 7 Counter Clock Disable with RC Loading LDBDIS 7 Counter Clock Disable with RB Loading CPCSTOP 6 Counter Clock Stopped with RC Compare LDBSTOP 6 Counter Clock Stopped with RB Loading BURST 5:4 Burst Signal Selection0 The clock is not gated by an external signal.1 XC0 is ANDed with the selected clock.2 XC1 is ANDed with the selected clock.3 XC2 is ANDed with the selected clock. CLKI 3 Clock Invert TCCLKS 2:0 Clock Selection0 Clock selected: internal MCK/2 clock signal (from PMC)1 Clock selected: internal MCK/8 clock signal (from PMC)2 Clock selected: internal MCK/32 clock signal (from PMC)3 Clock selected: internal MCK/128 clock signal (from PMC)4 Clock selected: internal SLCK clock signal (from PMC)5 Clock selected: XC06 Clock selected: XC17 Clock selected: XC2 BSWTRG 31:30 Software Trigger Effect on TIOBx0 NONE1 SET2 CLEAR3 TOGGLE
TC_CHANNEL2.TC_SMMRStepper Motor Mode Register (channel = 0)
Address 0x40010088
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does DOWN 1 Down Count GCEN 0 Gray Count Enable
TC_CHANNEL2.TC_RABRegister AB (channel = 0)
Address 0x4001008C
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does RAB 31:0 Register A or Register B
TC_CHANNEL2.TC_CVCounter Value (channel = 0)
Address 0x40010090
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CV 31:0 Counter Value
TC_CHANNEL2.TC_RARegister A (channel = 0)
Address 0x40010094
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RA 31:0 Register A
TC_CHANNEL2.TC_RBRegister B (channel = 0)
Address 0x40010098
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RB 31:0 Register B
TC_CHANNEL2.TC_RCRegister C (channel = 0)
Address 0x4001009C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RC 31:0 Register C
TC_CHANNEL2.TC_SRStatus Register (channel = 0)
Address 0x400100A0
Reset 0x00000000
Access read only
Size 32-bit 13 fields
Field Bits What it does MTIOB 18 TIOB Mirror MTIOA 17 TIOA Mirror CLKSTA 16 Clock Enabling Status RXBUFF 9 Reception Buffer Full (cleared by writing TC_RCR or TC_RNCR) ENDRX 8 End of Receiver Transfer (cleared by writing TC_RCR or TC_RNCR) ETRGS 7 External Trigger Status (cleared on read) LDRBS 6 RB Loading Status (cleared on read) LDRAS 5 RA Loading Status (cleared on read) CPCS 4 RC Compare Status (cleared on read) CPBS 3 RB Compare Status (cleared on read) CPAS 2 RA Compare Status (cleared on read) LOVRS 1 Load Overrun Status (cleared on read) COVFS 0 Counter Overflow Status (cleared on read)
TC_CHANNEL2.TC_IERInterrupt Enable Register (channel = 0)
Address 0x400100A4
Reset 0x00000000
Access write only
Size 32-bit 10 fields
Field Bits What it does RXBUFF 9 Reception Buffer Full ENDRX 8 End of Receiver Transfer ETRGS 7 External Trigger LDRBS 6 RB Loading LDRAS 5 RA Loading CPCS 4 RC Compare CPBS 3 RB Compare CPAS 2 RA Compare LOVRS 1 Load Overrun COVFS 0 Counter Overflow
TC_CHANNEL2.TC_IDRInterrupt Disable Register (channel = 0)
Address 0x400100A8
Reset 0x00000000
Access write only
Size 32-bit 10 fields
Field Bits What it does RXBUFF 9 Reception Buffer Full ENDRX 8 End of Receiver Transfer ETRGS 7 External Trigger LDRBS 6 RB Loading LDRAS 5 RA Loading CPCS 4 RC Compare CPBS 3 RB Compare CPAS 2 RA Compare LOVRS 1 Load Overrun COVFS 0 Counter Overflow
TC_CHANNEL2.TC_IMRInterrupt Mask Register (channel = 0)
Address 0x400100AC
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does RXBUFF 9 Reception Buffer Full ENDRX 8 End of Receiver Transfer ETRGS 7 External Trigger LDRBS 6 RB Loading LDRAS 5 RA Loading CPCS 4 RC Compare CPBS 3 RB Compare CPAS 2 RA Compare LOVRS 1 Load Overrun COVFS 0 Counter Overflow
TC_BCRBlock Control Register
Address 0x400100C0
Reset 0x00000000
Access write only
Size 32-bit 1 field
Field Bits What it does SYNC 0 Synchro Command
TC_BMRBlock Mode Register
Address 0x400100C4
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does TC2XC2S 5:4 External Clock Signal 2 Selection0 Signal connected to XC2: TCLK22 Signal connected to XC2: TIOA03 Signal connected to XC2: TIOA1 TC1XC1S 3:2 External Clock Signal 1 Selection0 Signal connected to XC1: TCLK12 Signal connected to XC1: TIOA03 Signal connected to XC1: TIOA2 TC0XC0S 1:0 External Clock Signal 0 Selection0 Signal connected to XC0: TCLK02 Signal connected to XC0: TIOA13 Signal connected to XC0: TIOA2
TC_WPMRWrite Protection Mode Register
Address 0x400100E4
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does WPEN 0 Write Protection Enable WPKEY 31:8 Write Protection Key5523789 Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
TC_RPR0Receive Pointer Register (pdc = 0)
Address 0x40010100
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RXPTR 31:0 Receive Pointer Register
TC_RNPR0Receive Next Pointer Register (pdc = 0)
Address 0x40010110
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RXNPTR 31:0 Receive Next Pointer
TC_RNCR0Receive Next Counter Register (pdc = 0)
Address 0x40010114
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RXNCTR 15:0 Receive Next Counter
TC_PTCR0Transfer Control Register (pdc = 0)
Address 0x40010120
Reset 0x00000000
Access write only
Size 32-bit 9 fields
Field Bits What it does ERRCLR 24 Transfer Bus Error Clear TXCBDIS 19 Transmitter Circular Buffer Disable TXCBEN 18 Transmitter Circular Buffer Enable RXCBDIS 17 Receiver Circular Buffer Disable RXCBEN 16 Receiver Circular Buffer Enable TXTDIS 9 Transmitter Transfer Disable TXTEN 8 Transmitter Transfer Enable RXTDIS 1 Receiver Transfer Disable RXTEN 0 Receiver Transfer Enable
TC_PTSR0Transfer Status Register (pdc = 0)
Address 0x40010124
Reset 0x00000000
Access read only
Size 32-bit 5 fields
Field Bits What it does ERR 24 Transfer Bus Error TXCBEN 18 Transmitter Circular Buffer Enable RXCBEN 16 Receiver Circular Buffer Enable TXTEN 8 Transmitter Transfer Enable RXTEN 0 Receiver Transfer Enable
BETA