ATSAMG54J19 I2SC0 registers

The 30 registers of I2SC0 (Inter-IC Sound Controller), from 0x40000000, with their reset value and every field. The ATSAMG54J19 has 713 registers in 31 peripherals, one page each.

I2SC0 Inter-IC Sound Controller

I2SC_CRControl Register

Address
0x40000000
Reset
0x00000000
Access
write only
Size
32-bit
7 fields
FieldBitsWhat it does
SWRST7Software Reset
TXDIS5Transmitter Disable
TXEN4Transmitter Enable
CKDIS3Clocks Disable
CKEN2Clocks Enable
RXDIS1Receiver Disable
RXEN0Receiver Enable

I2SC_MRMode Register

Address
0x40000004
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
IMCKMODE30Master Clock Mode
IMCKFS29:24Master Clock to fs Ratio
  • 0 Sample frequency ratio set to 16
  • 1 Sample frequency ratio set to 32
  • 2 Sample frequency ratio set to 48
  • 3 Sample frequency ratio set to 64
  • 5 Sample frequency ratio set to 96
  • 7 Sample frequency ratio set to 128
  • 11 Sample frequency ratio set to 192
  • 15 Sample frequency ratio set to 256
  • 23 Sample frequency ratio set to 384
  • 31 Sample frequency ratio set to 512
  • 47 Sample frequency ratio set to 768
  • 63 Sample frequency ratio set to 1024
IMCKDIV21:16Peripheral Clock to I2SC Master Clock Ratio
TXSAME14Transmit Data when Underrun
TXDMA13Single or Multiple PDC Channels for Transmitter
TXMONO12Transmit Mono
RXLOOP10Loop-back Test Mode
RXDMA9Single or Multiple PDC Channels for Receiver
RXMONO8Receive Mono
DATALENGTH4:2Data Word Length
  • 0 Data length is set to 32 bits
  • 1 Data length is set to 24 bits
  • 2 Data length is set to 20 bits
  • 3 Data length is set to 18 bits
  • 4 Data length is set to 16 bits
  • 5 Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word.
  • 6 Data length is set to 8 bits
  • 7 Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word.
MODE0Inter-IC Sound Controller Mode
  • 0 I2SCK and i2SWS pin inputs used as bit clock and word select/frame synchronization.
  • 1 Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SCK and I2SWS pins. MCK is output as master clock on I2SMCK if I2SC_MR.IMCKMODE is set.
IWS31I2SWS TDM Slot Width

I2SC_SRStatus Register

Address
0x40000008
Reset
0x00000000
Access
read only
Size
32-bit
12 fields
FieldBitsWhat it does
TXURCH21:20Transmit Underrun Channel
RXBUFF19Receive Buffer Full
RXORCH9:8Receive Overrun Channel
ENDTX7End of Transmitter Transfer
TXUR6Transmit Underrun
TXRDY5Transmit Ready
TXEN4Transmitter Enabled
ENDRX3End of Receiver Transfer
RXOR2Receive Overrun
RXRDY1Receive Ready
RXEN0Receiver Enabled
TXBUFE31Transmit Buffer Empty

I2SC_SCRStatus Clear Register

Address
0x4000000C
Reset
0x00000000
Access
write only
Size
32-bit
4 fields
FieldBitsWhat it does
TXURCH21:20Transmit Underrun Per Channel Status Clear
RXORCH9:8Receive Overrun Per Channel Status Clear
TXUR6Transmit Underrun Status Clear
RXOR2Receive Overrun Status Clear

I2SC_SSRStatus Set Register

Address
0x40000010
Reset
0x00000000
Access
write only
Size
32-bit
4 fields
FieldBitsWhat it does
TXURCH21:20Transmit Underrun Per Channel Status Set
RXORCH9:8Receive Overrun Per Channel Status Set
TXUR6Transmit Underrun Status Set
RXOR2Receive Overrun Status Set

I2SC_IERInterrupt Enable Register

Address
0x40000014
Reset
0x00000000
Access
write only
Size
32-bit
8 fields
FieldBitsWhat it does
RXFULL19Receive Buffer Full Interrupt Enable
ENDTX7End of Transmission Interrupt Enable
TXUR6Transmit Underflow Interrupt Enable
TXRDY5Transmit Ready Interrupt Enable
ENDRX3End of Reception Interrupt Enable
RXOR2Receiver Overrun Interrupt Enable
RXRDY1Receiver Ready Interrupt Enable
TXEMPTY31Transmit Buffer Empty Interrupt Enable

I2SC_IDRInterrupt Disable Register

Address
0x40000018
Reset
0x00000000
Access
write only
Size
32-bit
8 fields
FieldBitsWhat it does
RXFULL19Receive Buffer Full Interrupt Disable
ENDTX7End of Transmission Interrupt Disable
TXUR6Transmit Underflow Interrupt Disable
TXRDY5Transmit Ready Interrupt Disable
ENDRX3End of Reception Interrupt Disable
RXOR2Receiver Overrun Interrupt Disable
RXRDY1Receiver Ready Interrupt Disable
TXEMPTY31Transmit Buffer Empty Interrupt Disable

I2SC_IMRInterrupt Mask Register

Address
0x4000001C
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
FieldBitsWhat it does
RXFULL19Receive Buffer Full Interrupt Disable
ENDTX7End of Transmission Interrupt Disable
TXUR6Transmit Underflow Interrupt Disable
TXRDY5Transmit Ready Interrupt Disable
ENDRX3End of Reception Interrupt Disable
RXOR2Receiver Overrun Interrupt Disable
RXRDY1Receiver Ready Interrupt Disable
TXEMPTY31Transmit Buffer Empty Interrupt Disable

I2SC_RHRReceiver Holding Register

Address
0x40000020
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
RHR31:0Receiver Holding Register

I2SC_THRTransmitter Holding Register

Address
0x40000024
Reset
0x00000000
Access
write only
Size
32-bit
1 field
FieldBitsWhat it does
THR31:0Transmitter Holding Register

I2SC_RPRReceive Pointer Register - Left side

Address
0x40000100
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXPTR31:0Receive Pointer Register

I2SC_RCRReceive Counter Register - Left side

Address
0x40000104
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXCTR15:0Receive Counter Register

I2SC_TPRTransmit Pointer Register - Left side

Address
0x40000108
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXPTR31:0Transmit Counter Register

I2SC_TCRTransmit Counter Register - Left side

Address
0x4000010C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXCTR15:0Transmit Counter Register

I2SC_RNPRReceive Next Pointer Register - Left side

Address
0x40000110
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXNPTR31:0Receive Next Pointer

I2SC_RNCRReceive Next Counter Register - Left side

Address
0x40000114
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXNCTR15:0Receive Next Counter

I2SC_TNPRTransmit Next Pointer Register - Left side

Address
0x40000118
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXNPTR31:0Transmit Next Pointer

I2SC_TNCRTransmit Next Counter Register - Left side

Address
0x4000011C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXNCTR15:0Transmit Counter Next

I2SC_PTCRTransfer Control Register - Left side

Address
0x40000120
Reset
0x00000000
Access
write only
Size
32-bit
9 fields
FieldBitsWhat it does
ERRCLR24Transfer Bus Error Clear
TXCBDIS19Transmitter Circular Buffer Disable
TXCBEN18Transmitter Circular Buffer Enable
RXCBDIS17Receiver Circular Buffer Disable
RXCBEN16Receiver Circular Buffer Enable
TXTDIS9Transmitter Transfer Disable
TXTEN8Transmitter Transfer Enable
RXTDIS1Receiver Transfer Disable
RXTEN0Receiver Transfer Enable

I2SC_PTSRTransfer Status Register - Left side

Address
0x40000124
Reset
0x00000000
Access
read only
Size
32-bit
5 fields
FieldBitsWhat it does
ERR24Transfer Bus Error
TXCBEN18Transmitter Circular Buffer Enable
RXCBEN16Receiver Circular Buffer Enable
TXTEN8Transmitter Transfer Enable
RXTEN0Receiver Transfer Enable

I2SC_RPR_RIGHTReceive Pointer Register - Right side

Address
0x40000200
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXPTR31:0Receive Pointer Register

I2SC_RCR_RIGHTReceive Counter Register - Right side

Address
0x40000204
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXCTR15:0Receive Counter Register

I2SC_TPR_RIGHTTransmit Pointer Register - Right side

Address
0x40000208
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXPTR31:0Transmit Counter Register

I2SC_TCR_RIGHTTransmit Counter Register - Right side

Address
0x4000020C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXCTR15:0Transmit Counter Register

I2SC_RNPR_RIGHTReceive Next Pointer Register - Right side

Address
0x40000210
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXNPTR31:0Receive Next Pointer

I2SC_RNCR_RIGHTReceive Next Counter Register - Right side

Address
0x40000214
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXNCTR15:0Receive Next Counter

I2SC_TNPR_RIGHTTransmit Next Pointer Register - Right side

Address
0x40000218
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXNPTR31:0Transmit Next Pointer

I2SC_TNCR_RIGHTTransmit Next Counter Register - Right side

Address
0x4000021C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXNCTR15:0Transmit Counter Next

I2SC_PTCR_RIGHTTransfer Control Register - Right side

Address
0x40000220
Reset
0x00000000
Access
write only
Size
32-bit
9 fields
FieldBitsWhat it does
ERRCLR24Transfer Bus Error Clear
TXCBDIS19Transmitter Circular Buffer Disable
TXCBEN18Transmitter Circular Buffer Enable
RXCBDIS17Receiver Circular Buffer Disable
RXCBEN16Receiver Circular Buffer Enable
TXTDIS9Transmitter Transfer Disable
TXTEN8Transmitter Transfer Enable
RXTDIS1Receiver Transfer Disable
RXTEN0Receiver Transfer Enable

I2SC_PTSR_RIGHTTransfer Status Register - Right side

Address
0x40000224
Reset
0x00000000
Access
read only
Size
32-bit
5 fields
FieldBitsWhat it does
ERR24Transfer Bus Error
TXCBEN18Transmitter Circular Buffer Enable
RXCBEN16Receiver Circular Buffer Enable
TXTEN8Transmitter Transfer Enable
RXTEN0Receiver Transfer Enable