The 17 registers of PDMIC1 (Pulse Density Modulation Interface Controller), from 0x40030000, with their reset value and every field. The ATSAMG54J19 has 713 registers in 31 peripherals, one page each.
PDMIC1 Pulse Density Modulation Interface Controller
PDMIC_CRControl Register
Address
0x40030000
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
ENPDM
4
Enable PDM
SWRST
0
Software Reset
PDMIC_MRMode Register
Address
0x40030004
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
PRESCAL
14:8
Prescaler Rate Selection
PDMIC_CDRConverted Data Register
Address
0x40030014
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
DATA
31:0
Data Converted
PDMIC_IERInterrupt Enable Register
Address
0x40030018
Reset
0x00000000
Access
write only
Size
32-bit
4 fields
Field
Bits
What it does
RXBUFF
28
Receive Buffer Full Interrupt Enable
ENDRX
27
End of Receive Buffer Interrupt Enable
OVRE
25
Overrun Error Interrupt Enable
DRDY
24
Data Ready Interrupt Enable
PDMIC_IDRInterrupt Disable Register
Address
0x4003001C
Reset
0x00000000
Access
write only
Size
32-bit
4 fields
Field
Bits
What it does
RXBUFF
28
Receive Buffer Full Interrupt Disable
ENDRX
27
End of Receive Buffer Interrupt Disable
OVRE
25
General Overrun Error Interrupt Disable
DRDY
24
Data Ready Interrupt Disable
PDMIC_IMRInterrupt Mask Register
Address
0x40030020
Reset
0x00000000
Access
read only
Size
32-bit
4 fields
Field
Bits
What it does
RXBUFF
28
Receive Buffer Full Interrupt Mask
ENDRX
27
End of Receive Buffer Interrupt Mask
OVRE
25
General Overrun Error Interrupt Mask
DRDY
24
Data Ready Interrupt Mask
PDMIC_ISRInterrupt Status Register
Address
0x40030024
Reset
0x00000000
Access
read only
Size
32-bit
5 fields
Field
Bits
What it does
RXBUFF
28
RX Buffer Full
ENDRX
27
End of RX Buffer
OVRE
25
Overrun Error
DRDY
24
Data Ready
FIFOCNT
23:16
FIFO Count
PDMIC_DSPR0DSP Configuration Register 0
Address
0x40030058
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
SHIFT
15:12
Data Shift
SCALE
11:8
Data Scale
OSR
6:4
Oversampling Ratio
0 Oversampling ratio is 128
1 Oversampling ratio is 64
SIZE
3
Data Size
SINBYP
2
SINCC Filter Bypass
HPFBYP
1
High-Pass Filter Bypass
PDMIC_DSPR1DSP Configuration Register 0
Address
0x4003005C
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
SHIFT
15:12
Data Shift
SCALE
11:8
Data Scale
OSR
6:4
Oversampling Ratio
0 Oversampling ratio is 128
1 Oversampling ratio is 64
SIZE
3
Data Size
SINBYP
2
SINCC Filter Bypass
HPFBYP
1
High-Pass Filter Bypass
PDMIC_WPMRWrite Protection Mode Register
Address
0x400300E4
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
WPEN
0
Write Protection Enable
WPKEY
31:8
Write Protect Key
4277315 Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.