ATSAMG54J19 SPI registers

The 22 registers of SPI (Serial Peripheral Interface), from 0x40008000, with their reset value and every field. The ATSAMG54J19 has 713 registers in 31 peripherals, one page each.

SPI Serial Peripheral Interface

SPI_CRControl Register

Address
0x40008000
Reset
0x00000000
Access
write only
Size
32-bit
4 fields
FieldBitsWhat it does
LASTXFER24Last Transfer
SWRST7SPI Software Reset
SPIDIS1SPI Disable
SPIEN0SPI Enable

SPI_MRMode Register

Address
0x40008004
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
PCS17:16Peripheral Chip Select
  • 1 NPCS1 as Chip Select
  • 2 NPCS0 as Chip Select
LLB7Local Loopback Enable
WDRBT5Wait Data Read Before Transfer
MODFDIS4Mode Fault Detection
PCSDEC2Chip Select Decode
PS1Peripheral Select
MSTR0Master/Slave Mode
  • 0 Slave
  • 1 Master
DLYBCS31:24Delay Between Chip Selects

SPI_RDRReceive Data Register

Address
0x40008008
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
PCS19:16Peripheral Chip Select
RD15:0Receive Data

SPI_TDRTransmit Data Register

Address
0x4000800C
Reset
0x00000000
Access
write only
Size
32-bit
3 fields
FieldBitsWhat it does
LASTXFER24Last Transfer
PCS19:16Peripheral Chip Select
  • 1 NPCS1 as Chip Select
  • 2 NPCS0 as Chip Select
TD15:0Transmit Data

SPI_SRStatus Register

Address
0x40008010
Reset
0x00000000
Access
read only
Size
32-bit
12 fields
FieldBitsWhat it does
SPIENS16SPI Enable Status
UNDES10Underrun Error Status (slave mode only) (cleared on read)
TXEMPTY9Transmission Registers Empty (cleared by writing SPI_TDR)
NSSR8NSS Rising (cleared on read)
TXBUFE7TX Buffer Empty (cleared by writing SPI_TCR or SPI_TNCR)
RXBUFF6RX Buffer Full (cleared by writing SPI_RCR or SPI_RNCR)
ENDTX5End of TX buffer (cleared by writing SPI_TCR or SPI_TNCR)
ENDRX4End of RX buffer (cleared by writing SPI_RCR or SPI_RNCR)
OVRES3Overrun Error Status (cleared on read)
MODF2Mode Fault Error (cleared on read)
TDRE1Transmit Data Register Empty (cleared by writing SPI_TDR)
RDRF0Receive Data Register Full (cleared by reading SPI_RDR)

SPI_IERInterrupt Enable Register

Address
0x40008014
Reset
0x00000000
Access
write only
Size
32-bit
11 fields
FieldBitsWhat it does
UNDES10Underrun Error Interrupt Enable
TXEMPTY9Transmission Registers Empty Enable
NSSR8NSS Rising Interrupt Enable
TXBUFE7Transmit Buffer Empty Interrupt Enable
RXBUFF6Receive Buffer Full Interrupt Enable
ENDTX5End of Transmit Buffer Interrupt Enable
ENDRX4End of Receive Buffer Interrupt Enable
OVRES3Overrun Error Interrupt Enable
MODF2Mode Fault Error Interrupt Enable
TDRE1SPI Transmit Data Register Empty Interrupt Enable
RDRF0Receive Data Register Full Interrupt Enable

SPI_IDRInterrupt Disable Register

Address
0x40008018
Reset
0x00000000
Access
write only
Size
32-bit
11 fields
FieldBitsWhat it does
UNDES10Underrun Error Interrupt Disable
TXEMPTY9Transmission Registers Empty Disable
NSSR8NSS Rising Interrupt Disable
TXBUFE7Transmit Buffer Empty Interrupt Disable
RXBUFF6Receive Buffer Full Interrupt Disable
ENDTX5End of Transmit Buffer Interrupt Disable
ENDRX4End of Receive Buffer Interrupt Disable
OVRES3Overrun Error Interrupt Disable
MODF2Mode Fault Error Interrupt Disable
TDRE1SPI Transmit Data Register Empty Interrupt Disable
RDRF0Receive Data Register Full Interrupt Disable

SPI_IMRInterrupt Mask Register

Address
0x4000801C
Reset
0x00000000
Access
read only
Size
32-bit
11 fields
FieldBitsWhat it does
UNDES10Underrun Error Interrupt Mask
TXEMPTY9Transmission Registers Empty Mask
NSSR8NSS Rising Interrupt Mask
TXBUFE7Transmit Buffer Empty Interrupt Mask
RXBUFF6Receive Buffer Full Interrupt Mask
ENDTX5End of Transmit Buffer Interrupt Mask
ENDRX4End of Receive Buffer Interrupt Mask
OVRES3Overrun Error Interrupt Mask
MODF2Mode Fault Error Interrupt Mask
TDRE1SPI Transmit Data Register Empty Interrupt Mask
RDRF0Receive Data Register Full Interrupt Mask

SPI_CSR0Chip Select Register 0

Address
0x40008030
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
DLYBS23:16Delay Before SPCK
SCBR15:8Serial Clock Baud Rate
BITS7:4Bits Per Transfer
  • 0 8 bits for transfer
  • 1 9 bits for transfer
  • 2 10 bits for transfer
  • 3 11 bits for transfer
  • 4 12 bits for transfer
  • 5 13 bits for transfer
  • 6 14 bits for transfer
  • 7 15 bits for transfer
  • 8 16 bits for transfer
CSAAT3Chip Select Active After Transfer
CSNAAT2Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
NCPHA1Clock Phase
  • 0 Data is valid on clock trailing edge (NCPHA=0)
  • 1 Data is valid on clock leading edge (NCPHA=1)
CPOL0Clock Polarity
  • 0 The inactive state value of SPCK is logic level zero
  • 1 The inactive state value of SPCK is logic level one
DLYBCT31:24Delay Between Consecutive Transfers

SPI_CSR1Chip Select Register 0

Address
0x40008034
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
DLYBS23:16Delay Before SPCK
SCBR15:8Serial Clock Baud Rate
BITS7:4Bits Per Transfer
  • 0 8 bits for transfer
  • 1 9 bits for transfer
  • 2 10 bits for transfer
  • 3 11 bits for transfer
  • 4 12 bits for transfer
  • 5 13 bits for transfer
  • 6 14 bits for transfer
  • 7 15 bits for transfer
  • 8 16 bits for transfer
CSAAT3Chip Select Active After Transfer
CSNAAT2Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
NCPHA1Clock Phase
  • 0 Data is valid on clock trailing edge (NCPHA=0)
  • 1 Data is valid on clock leading edge (NCPHA=1)
CPOL0Clock Polarity
  • 0 The inactive state value of SPCK is logic level zero
  • 1 The inactive state value of SPCK is logic level one
DLYBCT31:24Delay Between Consecutive Transfers

SPI_WPMRWrite Protection Mode Register

Address
0x400080E4
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
WPEN0Write Protection Enable
WPKEY31:8Write Protection Key
  • 5460041 Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

SPI_WPSRWrite Protection Status Register

Address
0x400080E8
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
WPVSRC15:8Write Protection Violation Source
WPVS0Write Protection Violation Status

SPI_RPRReceive Pointer Register

Address
0x40008100
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXPTR31:0Receive Pointer Register

SPI_RCRReceive Counter Register

Address
0x40008104
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXCTR15:0Receive Counter Register

SPI_TPRTransmit Pointer Register

Address
0x40008108
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXPTR31:0Transmit Counter Register

SPI_TCRTransmit Counter Register

Address
0x4000810C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXCTR15:0Transmit Counter Register

SPI_RNPRReceive Next Pointer Register

Address
0x40008110
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXNPTR31:0Receive Next Pointer

SPI_RNCRReceive Next Counter Register

Address
0x40008114
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXNCTR15:0Receive Next Counter

SPI_TNPRTransmit Next Pointer Register

Address
0x40008118
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXNPTR31:0Transmit Next Pointer

SPI_TNCRTransmit Next Counter Register

Address
0x4000811C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXNCTR15:0Transmit Counter Next

SPI_PTCRTransfer Control Register

Address
0x40008120
Reset
0x00000000
Access
write only
Size
32-bit
9 fields
FieldBitsWhat it does
ERRCLR24Transfer Bus Error Clear
TXCBDIS19Transmitter Circular Buffer Disable
TXCBEN18Transmitter Circular Buffer Enable
RXCBDIS17Receiver Circular Buffer Disable
RXCBEN16Receiver Circular Buffer Enable
TXTDIS9Transmitter Transfer Disable
TXTEN8Transmitter Transfer Enable
RXTDIS1Receiver Transfer Disable
RXTEN0Receiver Transfer Enable

SPI_PTSRTransfer Status Register

Address
0x40008124
Reset
0x00000000
Access
read only
Size
32-bit
5 fields
FieldBitsWhat it does
ERR24Transfer Bus Error
TXCBEN18Transmitter Circular Buffer Enable
RXCBEN16Receiver Circular Buffer Enable
TXTEN8Transmitter Transfer Enable
RXTEN0Receiver Transfer Enable