ATSAMG54J19 USART registers The 24 registers of USART (Universal Synchronous Asynchronous Receiver Transmitter), from 0x40024000, with their reset value and every field. The ATSAMG54J19 has 713 registers in 31 peripherals, one page each.
USART Universal Synchronous Asynchronous Receiver Transmitter US_CRControl Register
Address 0x40024000
Reset 0x00000000
Access write only
Size 32-bit 23 fields
Field Bits What it does RCS 19 Release SPI Chip Select RTSDIS 19 Request to Send Pin Control FCS 18 Force SPI Chip Select RTSEN 18 Request to Send Pin Control RETTO 15 Start Time-out Immediately SENDA 12 Send Address STTTO 11 Clear TIMEOUT Flag and Start Time-out After Next Character Received STPBRK 10 Stop Break STTBRK 9 Start Break RSTSTA 8 Reset Status Bits RSTSTA 8 Reset Status Bits TXDIS 7 Transmitter Disable TXDIS 7 Transmitter Disable TXEN 6 Transmitter Enable TXEN 6 Transmitter Enable RXDIS 5 Receiver Disable RXDIS 5 Receiver Disable RXEN 4 Receiver Enable RXEN 4 Receiver Enable RSTTX 3 Reset Transmitter RSTTX 3 Reset Transmitter RSTRX 2 Reset Receiver RSTRX 2 Reset Receiver
US_MRMode Register
Address 0x40024004
Reset 0x00000000
Access read/write
Size 32-bit 18 fields
Field Bits What it does FILTER 28 Receive Line Filter WRDBT 20 Wait Read Data Before Transfer OVER 19 Oversampling Mode CLKO 18 Clock Output Select CLKO 18 Clock Output Select MODE9 17 9-bit Character Length CPOL 16 SPI Clock Polarity CHMODE 15:14 Channel Mode0 Normal mode1 Automatic Echo. Receiver input is connected to the TXD pin.2 Local Loopback. Transmitter output is connected to the Receiver Input.3 Remote Loopback. RXD pin is internally connected to the TXD pin. NBSTOP 13:12 Number of Stop Bits0 1 stop bit1 1.5 stop bits (SYNC = 0) or reserved (SYNC = 1)2 2 stop bits PAR 11:9 Parity Type0 Even parity1 Odd parity2 Parity forced to 0 (Space)3 Parity forced to 1 (Mark)4 No parity6 Multidrop mode CPHA 8 SPI Clock Phase SYNC 8 Synchronous Mode Select CHRL 7:6 Character Length0 Character length is 5 bits1 Character length is 6 bits2 Character length is 7 bits3 Character length is 8 bits CHRL 7:6 Character Length0 Character length is 5 bits1 Character length is 6 bits2 Character length is 7 bits3 Character length is 8 bits USCLKS 5:4 Clock Selection0 Peripheral clock is selected1 Peripheral clock divided (DIV=8) is selected3 Serial clock (SCK) is selected USCLKS 5:4 Clock Selection0 Peripheral clock is selected1 Peripheral clock divided (DIV=8) is selected3 Serial clock (SCK) is selected USART_MODE 3:0 USART Mode of Operation0 Normal mode1 RS485 mode2 Hardware Handshaking14 SPI master mode15 SPI Slave mode USART_MODE 3:0 USART Mode of Operation0 Normal mode1 RS485 mode2 Hardware Handshaking14 SPI master mode15 SPI Slave mode
US_IERInterrupt Enable Register
Address 0x40024008
Reset 0x00000000
Access write only
Size 32-bit 22 fields
Field Bits What it does CTSIC 19 Clear to Send Input Change Interrupt Enable RXBUFF 12 Receive Buffer Full Interrupt Enable (available in all USART modes of operation) RXBUFF 12 Receive Buffer Full Interrupt Enable TXBUFE 11 Transmit Buffer Empty Interrupt Enable (available in all USART modes of operation) TXBUFE 11 Transmit Buffer Empty Interrupt Enable UNRE 10 SPI Underrun Error Interrupt Enable TXEMPTY 9 TXEMPTY Interrupt Enable TXEMPTY 9 TXEMPTY Interrupt Enable TIMEOUT 8 Time-out Interrupt Enable PARE 7 Parity Error Interrupt Enable FRAME 6 Framing Error Interrupt Enable OVRE 5 Overrun Error Interrupt Enable OVRE 5 Overrun Error Interrupt Enable ENDTX 4 End of Transmit Buffer Interrupt Enable (available in all USART modes of operation) ENDTX 4 End of Transmit Buffer Interrupt Enable ENDRX 3 End of Receive Buffer Interrupt Enable (available in all USART modes of operation) ENDRX 3 End of Receive Buffer Interrupt Enable RXBRK 2 Receiver Break Interrupt Enable TXRDY 1 TXRDY Interrupt Enable TXRDY 1 TXRDY Interrupt Enable RXRDY 0 RXRDY Interrupt Enable RXRDY 0 RXRDY Interrupt Enable
US_IDRInterrupt Disable Register
Address 0x4002400C
Reset 0x00000000
Access write only
Size 32-bit 22 fields
Field Bits What it does CTSIC 19 Clear to Send Input Change Interrupt Enable RXBUFF 12 Receive Buffer Full Interrupt Enable (available in all USART modes of operation) RXBUFF 12 Receive Buffer Full Interrupt Enable TXBUFE 11 Transmit Buffer Empty Interrupt Enable (available in all USART modes of operation) TXBUFE 11 Transmit Buffer Empty Interrupt Enable UNRE 10 SPI Underrun Error Interrupt Enable TXEMPTY 9 TXEMPTY Interrupt Enable TXEMPTY 9 TXEMPTY Interrupt Enable TIMEOUT 8 Time-out Interrupt Enable PARE 7 Parity Error Interrupt Enable FRAME 6 Framing Error Interrupt Enable OVRE 5 Overrun Error Interrupt Enable OVRE 5 Overrun Error Interrupt Enable ENDTX 4 End of Transmit Buffer Interrupt Enable (available in all USART modes of operation) ENDTX 4 End of Transmit Buffer Interrupt Enable ENDRX 3 End of Receive Buffer Interrupt Enable (available in all USART modes of operation) ENDRX 3 End of Receive Buffer Interrupt Enable RXBRK 2 Receiver Break Interrupt Enable TXRDY 1 TXRDY Interrupt Enable TXRDY 1 TXRDY Interrupt Enable RXRDY 0 RXRDY Interrupt Enable RXRDY 0 RXRDY Interrupt Enable
US_IMRInterrupt Mask Register
Address 0x40024010
Reset 0x00000000
Access read only
Size 32-bit 22 fields
Field Bits What it does CTSIC 19 Clear to Send Input Change Interrupt Enable RXBUFF 12 Receive Buffer Full Interrupt Enable (available in all USART modes of operation) RXBUFF 12 Receive Buffer Full Interrupt Enable TXBUFE 11 Transmit Buffer Empty Interrupt Enable (available in all USART modes of operation) TXBUFE 11 Transmit Buffer Empty Interrupt Enable UNRE 10 SPI Underrun Error Interrupt Enable TXEMPTY 9 TXEMPTY Interrupt Enable TXEMPTY 9 TXEMPTY Interrupt Enable TIMEOUT 8 Time-out Interrupt Enable PARE 7 Parity Error Interrupt Enable FRAME 6 Framing Error Interrupt Enable OVRE 5 Overrun Error Interrupt Enable OVRE 5 Overrun Error Interrupt Enable ENDTX 4 End of Transmit Buffer Interrupt Enable (available in all USART modes of operation) ENDTX 4 End of Transmit Buffer Interrupt Enable ENDRX 3 End of Receive Buffer Interrupt Enable (available in all USART modes of operation) ENDRX 3 End of Receive Buffer Interrupt Enable RXBRK 2 Receiver Break Interrupt Enable TXRDY 1 TXRDY Interrupt Enable TXRDY 1 TXRDY Interrupt Enable RXRDY 0 RXRDY Interrupt Enable RXRDY 0 RXRDY Interrupt Enable
US_CSRChannel Status Register
Address 0x40024014
Reset 0x00000000
Access read only
Size 32-bit 23 fields
Field Bits What it does CTS 23 Image of CTS Input CTSIC 19 Clear to Send Input Change Flag (cleared on read) RXBUFF 12 RX Buffer Full (cleared by writing US_RCR or US_RNCR) RXBUFF 12 RX Buffer Full (cleared by writing US_RCR or US_RNCR) TXBUFE 11 TX Buffer Empty (cleared by writing US_TCR or US_TNCR) TXBUFE 11 TX Buffer Empty (cleared by writing US_TCR or US_TNCR) UNRE 10 Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) TXEMPTY 9 Transmitter Empty (cleared by writing US_THR) TXEMPTY 9 Transmitter Empty (cleared by writing US_THR) TIMEOUT 8 Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) PARE 7 Parity Error (cleared by writing a one to bit US_CR.RSTSTA) FRAME 6 Framing Error (cleared by writing a one to bit US_CR.RSTSTA) OVRE 5 Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) OVRE 5 Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) ENDTX 4 End of TX Buffer (cleared by writing US_TCR or US_TNCR) ENDTX 4 End of TX Buffer (cleared by writing US_TCR or US_TNCR) ENDRX 3 End of RX Buffer (cleared by writing US_RCR or US_RNCR) ENDRX 3 End of RX Buffer (cleared by writing US_RCR or US_RNCR) RXBRK 2 Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) TXRDY 1 Transmitter Ready (cleared by writing US_THR) TXRDY 1 Transmitter Ready (cleared by writing US_THR) RXRDY 0 Receiver Ready (cleared by reading US_RHR) RXRDY 0 Receiver Ready (cleared by reading US_RHR)
US_RHRReceive Holding Register
Address 0x40024018
Reset 0x00000000
Access read only
Size 32-bit 2 fields
Field Bits What it does RXSYNH 15 Received Sync RXCHR 8:0 Received Character
US_THRTransmit Holding Register
Address 0x4002401C
Reset 0x00000000
Access write only
Size 32-bit 2 fields
Field Bits What it does TXSYNH 15 Sync Field to be Transmitted TXCHR 8:0 Character to be Transmitted
US_BRGRBaud Rate Generator Register
Address 0x40024020
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does FP 18:16 Fractional Part CD 15:0 Clock Divider
US_RTORReceiver Time-out Register
Address 0x40024024
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does TO 15:0 Time-out Value
US_TTGRTransmitter Timeguard Register
Address 0x40024028
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does TG 7:0 Timeguard Value
US_NERNumber of Errors Register
Address 0x40024044
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does NB_ERRORS 7:0 Number of Errors
US_WPMRWrite Protection Mode Register
Address 0x400240E4
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does WPEN 0 Write Protection Enable WPKEY 31:8 Write Protection Key5591873 Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
US_WPSRWrite Protection Status Register
Address 0x400240E8
Reset 0x00000000
Access read only
Size 32-bit 2 fields
Field Bits What it does WPVSRC 23:8 Write Protection Violation Source WPVS 0 Write Protection Violation Status
US_RPRReceive Pointer Register
Address 0x40024100
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RXPTR 31:0 Receive Pointer Register
US_RCRReceive Counter Register
Address 0x40024104
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RXCTR 15:0 Receive Counter Register
US_TPRTransmit Pointer Register
Address 0x40024108
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does TXPTR 31:0 Transmit Counter Register
US_TCRTransmit Counter Register
Address 0x4002410C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does TXCTR 15:0 Transmit Counter Register
US_RNPRReceive Next Pointer Register
Address 0x40024110
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RXNPTR 31:0 Receive Next Pointer
US_RNCRReceive Next Counter Register
Address 0x40024114
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RXNCTR 15:0 Receive Next Counter
US_TNPRTransmit Next Pointer Register
Address 0x40024118
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does TXNPTR 31:0 Transmit Next Pointer
US_TNCRTransmit Next Counter Register
Address 0x4002411C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does TXNCTR 15:0 Transmit Counter Next
US_PTCRTransfer Control Register
Address 0x40024120
Reset 0x00000000
Access write only
Size 32-bit 9 fields
Field Bits What it does ERRCLR 24 Transfer Bus Error Clear TXCBDIS 19 Transmitter Circular Buffer Disable TXCBEN 18 Transmitter Circular Buffer Enable RXCBDIS 17 Receiver Circular Buffer Disable RXCBEN 16 Receiver Circular Buffer Enable TXTDIS 9 Transmitter Transfer Disable TXTEN 8 Transmitter Transfer Enable RXTDIS 1 Receiver Transfer Disable RXTEN 0 Receiver Transfer Enable
US_PTSRTransfer Status Register
Address 0x40024124
Reset 0x00000000
Access read only
Size 32-bit 5 fields
Field Bits What it does ERR 24 Transfer Bus Error TXCBEN 18 Transmitter Circular Buffer Enable RXCBEN 16 Receiver Circular Buffer Enable TXTEN 8 Transmitter Transfer Enable RXTEN 0 Receiver Transfer Enable
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