ATSAML11E16A SCB registers

The 15 registers of SCB (System Control Block), from 0xE000ED00, with their reset value and every field. The ATSAML11E16A has 1295 registers in 47 peripherals, one page each.

SCB System Control Block

CPUIDCPUID base register

Address
0xE000ED00
Reset
0x00000000
Access
read only
Size
32-bit
5 fields
FieldBitsWhat it does
Variant23:20Variant number
Architecture19:16Architecture version, 0xC=ARMv8-M Base Line, 0xF=ARMv8-M Main Line
PartNo15:4Part number, 0xD20=Cortex-M23
Revision3:0Revision number
Implementer31:24Implementer code, ARM=0x41

ICSRInterrupt Control and State Register

Address
0xE000ED04
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
PENDNMICLR30Pend NMI clear
PENDSVSET28Pend PendSV set
  • 0 Write: no effect; read: PendSV exception is not pending
  • 1 Write: changes PendSV exception state to pending; read: PendSV exception is pending
PENDSVCLR27Pend PendSV clear
  • 0 No effect
  • 1 Removes the pending state from the PendSV exception
PENDSTSET26Pend SysTick set
  • 0 Write: no effect; read: SysTick exception is not pending
  • 1 Write: changes SysTick exception state to pending; read: SysTick exception is pending
PENDSTCLR25Pend SysTick clear
  • 0 No effect
  • 1 Removes the pending state from the SysTick exception
ISRPREEMPT23Interrupt preempt
ISRPENDING22Interrupt pending
VECTPENDING20:12Vector pending
RETTOBASE11Return to base
VECTACTIVE8:0Vector active
PENDNMISET31Pend NMI set
  • 0 Write: no effect; read: NMI exception is not pending
  • 1 Write: changes NMI exception state to pending; read: NMI exception is pending

VTORVector Table Offset Register

Address
0xE000ED08
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TBLOFF31:7Vector table base offset

AIRCRApplication Interrupt and Reset Control Register

Address
0xE000ED0C
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
ENDIANNESS15Data Endianness, 0=little, 1=big
  • 0 Little-endian
  • 1 Big-endian
PRIS14Prioritize Secure Exceptions
  • 0 Priority ranges of Secure and Non-secure exceptions are identical
  • 1 Non-secure exceptions are de-prioritized
BFHFNMINS13BusFault, HardFault and NMI Non-secure enable
  • 0 BusFault, HardFault, and NMI are Secure
  • 1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault
SYSRESETREQS3System Reset Request Secure only
  • 0 SYSRESETREQ functionality is available to both Security states
  • 1 SYSRESETREQ functionality is only available to Secure state
SYSRESETREQ2System Reset Request
  • 0 Do not request a system reset
  • 1 Request a system reset
VECTCLRACTIVE1Debug: Clear Active State
  • 0 Do not clear active state
  • 1 Clear active state
VECTKEY31:16Register Key (0x05FA)

SCRSystem Control Register

Address
0xE000ED10
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
SEVONPEND4Send Event on Pending bit
  • 0 Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
  • 1 Enabled events and all interrupts, including disabled interrupts, can wakeup the processor
SLEEPDEEPS3Sleep deep secure
SLEEPDEEP2Sleep deep
  • 0 Sleep
  • 1 Deep sleep
SLEEPONEXIT1Sleep on exit
  • 0 O not sleep when returning to Thread mode
  • 1 Enter sleep, or deep sleep, on return from an ISR

CCRConfiguration and Control Register

Address
0xE000ED14
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
BP18Branch prediction enable
IC17Instruction cache enable
DC16Data cache enable
STKOFHFNMIGN10Stack overflow in HardFault and NMI ignore
BFHFNMIGN8BusFault in HardFault or NMI ignore
DIV_0_TRP4Divide by zero trap
UNALIGN_TRP3Unaligned trap
  • 0 Do not trap unaligned halfword and word accesses
  • 1 Trap unaligned halfword and word accesses
USERSETMPEND1User set main pending

SHPR2System Handler Priority Register 2

Address
0xE000ED1C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PRI_1131:24Priority of system handler 11, SVCall

SHPR3System Handler Priority Register 3

Address
0xE000ED20
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
PRI_1423:16Priority of system handler 14, PendSV
PRI_127:0Priority of system handler 12, DebugMonitor
PRI_1531:24Priority of system handler 15, SysTick

SHCSRSystem Handler Control and State Register

Address
0xE000ED24
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
HARDFAULTPENDED21HardFault exception pended state
SVCALLPENDED15SVCall exception pended state
SYSTICKACT11SysTick exception active state
PENDSVACT10PendSV exception active state
SVCALLACT7SVCall exception active state
NMIACT5NMI exception active state
HARDFAULTACT2HardFault exception active state

DFSRDebug Fault Status Register

Address
0xE000ED30
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EXTERNAL4External event
VCATCH3Vector Catch event
DWTTRAP2Watchpoint event
BKPT1Breakpoint event
HALTED0Halt or step event

AFSRAuxiliary Fault Status Register

Address
0xE000ED3C
Reset
0x00000000
Access
read/write
Size
32-bit

CLIDRCache Level ID Register

Address
0xE000ED78
Reset
0x00000000
Access
read only
Size
32-bit
11 fields
FieldBitsWhat it does
LoUU29:27Level of Unification Uniprocessor
LoC26:24Level of Coherence
LoUIS23:21Level of Unification Inner Shareable
Ctype720:18Cache type at level 7
  • 0 No cache
  • 1 Instruction cache only
  • 2 Data cache only
  • 3 Separate instruction and data caches
  • 4 Unified cache
Ctype617:15Cache type at level 6
  • 0 No cache
  • 1 Instruction cache only
  • 2 Data cache only
  • 3 Separate instruction and data caches
  • 4 Unified cache
Ctype514:12Cache type at level 5
  • 0 No cache
  • 1 Instruction cache only
  • 2 Data cache only
  • 3 Separate instruction and data caches
  • 4 Unified cache
Ctype411:9Cache type at level 4
  • 0 No cache
  • 1 Instruction cache only
  • 2 Data cache only
  • 3 Separate instruction and data caches
  • 4 Unified cache
Ctype38:6Cache type at level 3
  • 0 No cache
  • 1 Instruction cache only
  • 2 Data cache only
  • 3 Separate instruction and data caches
  • 4 Unified cache
Ctype25:3Cache type at level 2
  • 0 No cache
  • 1 Instruction cache only
  • 2 Data cache only
  • 3 Separate instruction and data caches
  • 4 Unified cache
Ctype12:0Cache type at level 1
  • 0 No cache
  • 1 Instruction cache only
  • 2 Data cache only
  • 3 Separate instruction and data caches
  • 4 Unified cache
ICB31:30Inner cache boundary
  • 0 Not disclosed in this mechanism
  • 1 L1 cache is the highest inner level
  • 2 L2 cache is the highest inner level
  • 3 L3 cache is the highest inner level

CTRCache Type Register

Address
0xE000ED7C
Reset
0x00000000
Access
read only
Size
32-bit
5 fields
FieldBitsWhat it does
CWG27:24Cache Write-back Granule
ERG23:20Exclusives Reservation Granule
DminLine19:16Data cache minimum line length
IminLine3:0Instruction cache minimum line length
Format31:29Cache Type Register format
  • 0 No cache type information provided
  • 4 Cache type information is provided

CCSIDRCurrent Cache Size ID register

Address
0xE000ED80
Reset
0x00000000
Access
read only
Size
32-bit
7 fields
FieldBitsWhat it does
WB30Write-Back
RA29Read-Allocate
WA28Write-Allocate
NumSets27:13Number of sets - 1
Associativity12:3Associativity - 1
LineSize2:0log2(number of words per line) - 2
WT31Write-Through

CSSELRCache Size Selection Register

Address
0xE000ED84
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
Level3:1Cache level - 1
InD0Instruction not Data