CTRLAControl
- Address
0x40001800- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0SWRST
1 field
| Field | Bits | What it does |
|---|---|---|
| SWRST | 0 | Software Reset |
The 47 registers of GCLK (Generic Clock Generator), from 0x40001800, with their reset value and every field. The ATSAML21E18B has 1205 registers in 40 peripherals, one page each.
0x400018000x00| Field | Bits | What it does |
|---|---|---|
| SWRST | 0 | Software Reset |
0x400018040x00000000| Field | Bits | What it does |
|---|---|---|
| GENCTRL8 | 10 | Generic Clock Generator Control 8 Synchronization Busy bits |
| GENCTRL7 | 9 | Generic Clock Generator Control 7 Synchronization Busy bits |
| GENCTRL6 | 8 | Generic Clock Generator Control 6 Synchronization Busy bits |
| GENCTRL5 | 7 | Generic Clock Generator Control 5 Synchronization Busy bits |
| GENCTRL4 | 6 | Generic Clock Generator Control 4 Synchronization Busy bits |
| GENCTRL3 | 5 | Generic Clock Generator Control 3 Synchronization Busy bits |
| GENCTRL2 | 4 | Generic Clock Generator Control 2 Synchronization Busy bits |
| GENCTRL1 | 3 | Generic Clock Generator Control 1 Synchronization Busy bits |
| GENCTRL0 | 2 | Generic Clock Generator Control 0 Synchronization Busy bits |
| SWRST | 0 | Software Reset Synchroniation Busy bit |
0x400018200x00000000| Field | Bits | What it does |
|---|---|---|
| RUNSTDBY | 13 | Run in Standby |
| DIVSEL | 12 | Divide Selection
|
| OE | 11 | Output Enable |
| OOV | 10 | Output Off Value |
| IDC | 9 | Improve Duty Cycle |
| GENEN | 8 | Generic Clock Generator Enable |
| SRC | 3:0 | Source Select
|
| DIV | 31:16 | Division Factor |
0x400018240x00000000| Field | Bits | What it does |
|---|---|---|
| RUNSTDBY | 13 | Run in Standby |
| DIVSEL | 12 | Divide Selection
|
| OE | 11 | Output Enable |
| OOV | 10 | Output Off Value |
| IDC | 9 | Improve Duty Cycle |
| GENEN | 8 | Generic Clock Generator Enable |
| SRC | 3:0 | Source Select
|
| DIV | 31:16 | Division Factor |
0x400018280x00000000| Field | Bits | What it does |
|---|---|---|
| RUNSTDBY | 13 | Run in Standby |
| DIVSEL | 12 | Divide Selection
|
| OE | 11 | Output Enable |
| OOV | 10 | Output Off Value |
| IDC | 9 | Improve Duty Cycle |
| GENEN | 8 | Generic Clock Generator Enable |
| SRC | 3:0 | Source Select
|
| DIV | 31:16 | Division Factor |
0x4000182C0x00000000| Field | Bits | What it does |
|---|---|---|
| RUNSTDBY | 13 | Run in Standby |
| DIVSEL | 12 | Divide Selection
|
| OE | 11 | Output Enable |
| OOV | 10 | Output Off Value |
| IDC | 9 | Improve Duty Cycle |
| GENEN | 8 | Generic Clock Generator Enable |
| SRC | 3:0 | Source Select
|
| DIV | 31:16 | Division Factor |
0x400018300x00000000| Field | Bits | What it does |
|---|---|---|
| RUNSTDBY | 13 | Run in Standby |
| DIVSEL | 12 | Divide Selection
|
| OE | 11 | Output Enable |
| OOV | 10 | Output Off Value |
| IDC | 9 | Improve Duty Cycle |
| GENEN | 8 | Generic Clock Generator Enable |
| SRC | 3:0 | Source Select
|
| DIV | 31:16 | Division Factor |
0x400018340x00000000| Field | Bits | What it does |
|---|---|---|
| RUNSTDBY | 13 | Run in Standby |
| DIVSEL | 12 | Divide Selection
|
| OE | 11 | Output Enable |
| OOV | 10 | Output Off Value |
| IDC | 9 | Improve Duty Cycle |
| GENEN | 8 | Generic Clock Generator Enable |
| SRC | 3:0 | Source Select
|
| DIV | 31:16 | Division Factor |
0x400018380x00000000| Field | Bits | What it does |
|---|---|---|
| RUNSTDBY | 13 | Run in Standby |
| DIVSEL | 12 | Divide Selection
|
| OE | 11 | Output Enable |
| OOV | 10 | Output Off Value |
| IDC | 9 | Improve Duty Cycle |
| GENEN | 8 | Generic Clock Generator Enable |
| SRC | 3:0 | Source Select
|
| DIV | 31:16 | Division Factor |
0x4000183C0x00000000| Field | Bits | What it does |
|---|---|---|
| RUNSTDBY | 13 | Run in Standby |
| DIVSEL | 12 | Divide Selection
|
| OE | 11 | Output Enable |
| OOV | 10 | Output Off Value |
| IDC | 9 | Improve Duty Cycle |
| GENEN | 8 | Generic Clock Generator Enable |
| SRC | 3:0 | Source Select
|
| DIV | 31:16 | Division Factor |
0x400018400x00000000| Field | Bits | What it does |
|---|---|---|
| RUNSTDBY | 13 | Run in Standby |
| DIVSEL | 12 | Divide Selection
|
| OE | 11 | Output Enable |
| OOV | 10 | Output Off Value |
| IDC | 9 | Improve Duty Cycle |
| GENEN | 8 | Generic Clock Generator Enable |
| SRC | 3:0 | Source Select
|
| DIV | 31:16 | Division Factor |
0x400018800x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018840x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018880x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x4000188C0x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018900x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018940x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018980x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x4000189C0x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018A00x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018A40x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018A80x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018AC0x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018B00x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018B40x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018B80x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018BC0x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018C00x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018C40x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018C80x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018CC0x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018D00x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018D40x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018D80x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018DC0x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018E00x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018E40x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018E80x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018EC0x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018F00x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018F40x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018F80x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400018FC0x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400019000x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400019040x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x400019080x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x4000190C0x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|