The 23 registers of DMAC (Direct Memory Access Controller), from 0x44000400, with their reset value and every field. The ATSAML21G18B has 1265 registers in 40 peripherals, one page each.
DMAC Direct Memory Access Controller
CTRLControl
Address
0x44000400
Reset
0x0000
Access
read/write
Size
16-bit
7 fields
Field
Bits
What it does
LVLEN3
11
Priority Level 3 Enable
LVLEN2
10
Priority Level 2 Enable
LVLEN1
9
Priority Level 1 Enable
LVLEN0
8
Priority Level 0 Enable
CRCENABLE
2
CRC Enable
DMAENABLE
1
DMA Enable
SWRST
0
Software Reset
CRCCTRLCRC Control
Address
0x44000402
Reset
0x0000
Access
read/write
Size
16-bit
3 fields
Field
Bits
What it does
CRCSRC
13:8
CRC Input Source
0 No action
1 I/O interface
CRCPOLY
3:2
CRC Polynomial Type
0 CRC-16 (CRC-CCITT)
1 CRC32 (IEEE 802.3)
CRCBEATSIZE
1:0
CRC Beat Size
0 8-bit bus transfer
1 16-bit bus transfer
2 32-bit bus transfer
CRCDATAINCRC Data Input
Address
0x44000404
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CRCDATAIN
31:0
CRC Data Input
CRCCHKSUMCRC Checksum
Address
0x44000408
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CRCCHKSUM
31:0
CRC Checksum
CRCSTATUSCRC Status
Address
0x4400040C
Reset
0x00
Access
read/write
7–
6–
5–
4–
3–
2–
1CRCZERO
0CRCBUSY
2 fields
Field
Bits
What it does
CRCZERO
1
CRC Zero
CRCBUSY
0
CRC Module Busy
DBGCTRLDebug Control
Address
0x4400040D
Reset
0x00
Access
read/write
7–
6–
5–
4–
3–
2–
1–
0DBGRUN
1 field
Field
Bits
What it does
DBGRUN
0
Debug Run
QOSCTRLQOS Control
Address
0x4400040E
Reset
0x2A
Access
read/write
7–
6–
5DQOS1
4DQOS0
3FQOS1
2FQOS0
1WRBQOS1
0WRBQOS0
3 fields
Field
Bits
What it does
DQOS
5:4
Data Transfer Quality of Service
0 Background (no sensitive operation)
1 Sensitive Bandwidth
2 Sensitive Latency
3 Critical Latency
FQOS
3:2
Fetch Quality of Service
0 Background (no sensitive operation)
1 Sensitive Bandwidth
2 Sensitive Latency
3 Critical Latency
WRBQOS
1:0
Write-Back Quality of Service
0 Background (no sensitive operation)
1 Sensitive Bandwidth
2 Sensitive Latency
3 Critical Latency
SWTRIGCTRLSoftware Trigger Control
Address
0x44000410
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
SWTRIG15
15
Channel 15 Software Trigger
SWTRIG14
14
Channel 14 Software Trigger
SWTRIG13
13
Channel 13 Software Trigger
SWTRIG12
12
Channel 12 Software Trigger
SWTRIG11
11
Channel 11 Software Trigger
SWTRIG10
10
Channel 10 Software Trigger
SWTRIG9
9
Channel 9 Software Trigger
SWTRIG8
8
Channel 8 Software Trigger
SWTRIG7
7
Channel 7 Software Trigger
SWTRIG6
6
Channel 6 Software Trigger
SWTRIG5
5
Channel 5 Software Trigger
SWTRIG4
4
Channel 4 Software Trigger
SWTRIG3
3
Channel 3 Software Trigger
SWTRIG2
2
Channel 2 Software Trigger
SWTRIG1
1
Channel 1 Software Trigger
SWTRIG0
0
Channel 0 Software Trigger
PRICTRL0Priority Control 0
Address
0x44000414
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
LVLPRI3
27:24
Level 3 Channel Priority Number
RRLVLEN2
23
Level 2 Round-Robin Scheduling Enable
LVLPRI2
19:16
Level 2 Channel Priority Number
RRLVLEN1
15
Level 1 Round-Robin Scheduling Enable
LVLPRI1
11:8
Level 1 Channel Priority Number
RRLVLEN0
7
Level 0 Round-Robin Scheduling Enable
0 Static arbitration scheme for channels with level 3 priority
1 Round-robin arbitration scheme for channels with level 3 priority