The 9 registers of NVMCTRL (Non-Volatile Memory Controller), from 0x41004000, with their reset value and every field. The ATSAML21J18B has 1323 registers in 42 peripherals, one page each.
NVMCTRL Non-Volatile Memory Controller
CTRLAControl A
Address
0x41004000
Reset
0x0000
Access
read/write
Size
16-bit
2 fields
Field
Bits
What it does
CMDEX
15:8
Command Execution
165 Execution Key
CMD
6:0
Command
2 Erase Row - Erases the row addressed by the ADDR register.
4 Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.
5 Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.
6 Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.
10 Security Flow Command
15 Write lockbits
26 RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register.
28 RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.
64 Lock Region - Locks the region containing the address location in the ADDR register.
65 Unlock Region - Unlocks the region containing the address location in the ADDR register.
66 Sets the power reduction mode.
67 Clears the power reduction mode.
68 Page Buffer Clear - Clears the page buffer.
69 Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row.
70 Invalidate all cache lines.
CTRLBControl B
Address
0x41004004
Reset
0x00000080
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
CACHEDIS
18
Cache Disable
READMODE
17:16
NVMCTRL Read Mode
0 The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.
1 Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.
2 The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.
FWUP
11
fast wake-up
SLEEPPRM
9:8
Power Reduction Mode during Sleep
0 NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.
1 NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.
BETA