ATSAMRH707F18A CoreDebug registers

The 4 registers of CoreDebug (Core Debug Register), from 0xE000EDF0, with their reset value and every field. The ATSAMRH707F18A has 2578 registers in 50 peripherals, one page each.

CoreDebug Core Debug Register

DHCSRDebug Halting Control and Status Register

Address
0xE000EDF0
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
S_RESET_ST25Reset Status
S_RETIRE_ST24Retire Status
S_LOCKUP19Locked up status
S_SLEEP18Sleep status
S_HALT17Debug state status
S_REGRDY16Transfer complete flag
C_SNAPSTALL5Allow imprecise entry to Debug state
C_MASKINTS3Mask PendSV, SysTick and external configurable interrupts
C_STEP2Processor step bit
C_HALT1Processor halt bit
C_DEBUGEN0Halting debug enable bit
DBGKEY31:16Debug key, must write 0xA05F to enable writes

DCRSRDebug Core Register Selector Register

Address
0xE000EDF4
Reset
0x00000000
Access
write only
Size
32-bit
2 fields
FieldBitsWhat it does
REGWnR16Specifies the access type for the transfer
REGSEL4:0Specifies the Arm core register, special-purpose register, or Floating-point Extension register, to transfer

DCRDRDebug Core Register Data Register

Address
0xE000EDF8
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DBGTMP31:0Data temporary cache

DEMCRDebug Exception and Monitor Control Register

Address
0xE000EDFC
Reset
0x00000000
Access
read/write
Size
32-bit
13 fields
FieldBitsWhat it does
TRCENA24Global enable for all DWT and ITM features
MON_REQ19DebugMonitor semaphore bit
MON_STEP18Enable DebugMonitor stepping
MON_PEND17Set DebugMonitor exception pending
MON_EN16Enable DebugMonitor exception
VC_HARDERR10HardFault exception catch
VC_INTERR9Interrupt/exception service error catch
VC_BUSERR8BusFault exception catch
VC_STATERR7State error catch
VC_CHKERR6Checking error catch
VC_NOCPERR5Coprocessor access error catch
VC_MMERR4MemManage exception catch
VC_CORERESET0Reset Vector Catch