ATSAMRH71F20C FLEXCOM1 registers

The 81 registers of FLEXCOM1 (Flexible Serial Communication), from 0x40014000, with their reset value and every field. The ATSAMRH71F20C has 3366 registers in 56 peripherals, one page each.

FLEXCOM1 Flexible Serial Communication

FLEX_MRFLEXCOM Mode Register

Address: 0x40014000
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
OPMODE	1:0	FLEXCOM Operating Mode `0` No communication `1` All UART related protocols are selected (RS232, RS485, IrDA, ISO7816, LIN, LON)SPI/TWI related registers are not accessible and have no impact on IOs. `2` SPI operating mode is selected.USART/TWI related registers are not accessible and have no impact on IOs. `3` All TWI related protocols are selected (TWI, SMBus).USART/SPI related registers are not accessible and have no impact on IOs.

FLEX_RHRFLEXCOM Receive Holding Register

Address: 0x40014010
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
RXDATA	15:0	Receive Data

FLEX_THRFLEXCOM Transmit Holding Register

Address: 0x40014020
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TXDATA	15:0	Transmit Data

FLEX_US_CRUSART Control Register

Address: 0x40014200
Reset: 0x00000000
Access: write only
Size: 32-bit

24 fields

Field	Bits	What it does
FIFOEN	30	FIFO Enable
REQCLR	28	Request to Clear the Comparison Trigger
TXFLCLR	26	Transmit FIFO Lock CLEAR
RXFCLR	25	Receive FIFO Clear
TXFCLR	24	Transmit FIFO Clear
LINWKUP	21	Send LIN Wakeup Signal
LINABT	20	Abort LIN Transmission
RTSDIS	19	Request to Send Disable
RTSEN	18	Request to Send Enable
RETTO	15	Start Timeout Immediately
RSTNACK	14	Reset Non Acknowledge
RSTIT	13	Reset Iterations
SENDA	12	Send Address
STTTO	11	Clear TIMEOUT Flag and Start Timeout After Next Character Received
STPBRK	10	Stop Break
STTBRK	9	Start Break
RSTSTA	8	Reset Status Bits
TXDIS	7	Transmitter Disable
TXEN	6	Transmitter Enable
RXDIS	5	Receiver Disable
RXEN	4	Receiver Enable
RSTTX	3	Reset Transmitter
RSTRX	2	Reset Receiver
FIFODIS	31	FIFO Disable

FLEX_US_MRUSART Mode Register

Address: 0x40014204
Reset: 0x00000000
Access: read/write
Size: 32-bit

20 fields

Field	Bits	What it does
MODSYNC	30	Manchester Synchronization Mode
MAN	29	Manchester Encoder/Decoder Enable
FILTER	28	Receive Line Filter
MAX_ITERATION	26:24	Maximum Number of Automatic Iteration
INVDATA	23	Inverted Data
VAR_SYNC	22	Variable Synchronization of Command/Data Sync Start Frame Delimiter
DSNACK	21	Disable Successive NACK
INACK	20	Inhibit Non Acknowledge
OVER	19	Oversampling Mode
CLKO	18	Clock Output Select
MODE9	17	9-bit Character Length
MSBF	16	Bit Order
CHMODE	15:14	Channel Mode `0` Normal mode `1` Automatic Echo. Receiver input is connected to the TXD pin. `2` Local Loopback. Transmitter output is connected to the Receiver Input. `3` Remote Loopback. RXD pin is internally connected to the TXD pin.
NBSTOP	13:12	Number of Stop Bits `0` 1 stop bit `1` 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) `2` 2 stop bits
PAR	11:9	Parity Type `0` Even parity `1` Odd parity `2` Parity forced to 0 (Space) `3` Parity forced to 1 (Mark) `4` No parity `6` Multidrop mode
SYNC	8	Synchronous Mode Select
CHRL	7:6	Character Length `0` Character length is 5 bits `1` Character length is 6 bits `2` Character length is 7 bits `3` Character length is 8 bits
USCLKS	5:4	Clock Selection `0` Peripheral clock is selected `1` Peripheral clock divided (DIV = 8) is selected `2` PMC generic clock is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. `3` External pin SCK is selected
USART_MODE	3:0	USART Mode of Operation `0` Normal mode `1` RS485 `2` Hardware handshaking `4` IS07816 Protocol: T = 0 `6` IS07816 Protocol: T = 1 `8` IrDA `9` LON `10` LIN Master mode `11` LIN Slave mode
ONEBIT	31	Start Frame Delimiter Selector

FLEX_US_IERUSART Interrupt Enable Register

Address: 0x40014208
Reset: 0x00000000
Access: write only
Size: 32-bit

30 fields

Field	Bits	What it does
LINSTE	30	LIN Synch Tolerance Error Interrupt Enable
LINSNRE	29	LIN Slave Not Responding Error Interrupt Enable
LINCE	28	LIN Checksum Error Interrupt Enable
LINIPE	27	LIN Identifier Parity Interrupt Enable
LINISFE	26	LIN Inconsistent Synch Field Error Interrupt Enable
LINBE	25	LIN Bus Error Interrupt Enable
MANE	24	Manchester Error Interrupt Enable
CMP	22	Comparison Interrupt Enable
CTSIC	19	Clear to Send Input Change Interrupt Enable
LINTC	15	LIN Transfer Completed Interrupt Enable
LINID	14	LIN Identifier Sent or LIN Identifier Received Interrupt Enable
LINBK	13	LIN Break Sent or LIN Break Received Interrupt Enable
NACK	13	Non Acknowledge Interrupt Enable
ITER	10	Max number of Repetitions Reached Interrupt Enable
TXEMPTY	9	TXEMPTY Interrupt Enable
TXEMPTY	9	TXEMPTY Interrupt Enable
TIMEOUT	8	Timeout Interrupt Enable
TIMEOUT	8	Timeout Interrupt Enable
PARE	7	Parity Error Interrupt Enable
PARE	7	Parity Error Interrupt Enable
FRAME	6	Framing Error Interrupt Enable
FRAME	6	Framing Error Interrupt Enable
OVRE	5	Overrun Error Interrupt Enable
OVRE	5	Overrun Error Interrupt Enable
RXBRK	2	Receiver Break Interrupt Enable
TXRDY	1	TXRDY Interrupt Enable
TXRDY	1	TXRDY Interrupt Enable
RXRDY	0	RXRDY Interrupt Enable
RXRDY	0	RXRDY Interrupt Enable
LINHTE	31	LIN Header Timeout Error Interrupt Enable

FLEX_US_IDRUSART Interrupt Disable Register

Address: 0x4001420C
Reset: 0x00000000
Access: write only
Size: 32-bit

30 fields

Field	Bits	What it does
LINSTE	30	LIN Synch Tolerance Error Interrupt Disable
LINSNRE	29	LIN Slave Not Responding Error Interrupt Disable
LINCE	28	LIN Checksum Error Interrupt Disable
LINIPE	27	LIN Identifier Parity Interrupt Disable
LINISFE	26	LIN Inconsistent Synch Field Error Interrupt Disable
LINBE	25	LIN Bus Error Interrupt Disable
MANE	24	Manchester Error Interrupt Disable
CMP	22	Comparison Interrupt Disable
CTSIC	19	Clear to Send Input Change Interrupt Disable
LINTC	15	LIN Transfer Completed Interrupt Disable
LINID	14	LIN Identifier Sent or LIN Identifier Received Interrupt Disable
LINBK	13	LIN Break Sent or LIN Break Received Interrupt Disable
NACK	13	Non Acknowledge Interrupt Disable
ITER	10	Max Number of Repetitions Reached Interrupt Disable
TXEMPTY	9	TXEMPTY Interrupt Disable
TXEMPTY	9	TXEMPTY Interrupt Disable
TIMEOUT	8	Timeout Interrupt Disable
TIMEOUT	8	Timeout Interrupt Disable
PARE	7	Parity Error Interrupt Disable
PARE	7	Parity Error Interrupt Disable
FRAME	6	Framing Error Interrupt Disable
FRAME	6	Framing Error Interrupt Disable
OVRE	5	Overrun Error Interrupt Enable
OVRE	5	Overrun Error Interrupt Disable
RXBRK	2	Receiver Break Interrupt Disable
TXRDY	1	TXRDY Interrupt Disable
TXRDY	1	TXRDY Interrupt Disable
RXRDY	0	RXRDY Interrupt Disable
RXRDY	0	RXRDY Interrupt Disable
LINHTE	31	LIN Header Timeout Error Interrupt Disable

FLEX_US_IMRUSART Interrupt Mask Register

Address: 0x40014210
Reset: 0x00000000
Access: read only
Size: 32-bit

30 fields

Field	Bits	What it does
LINSTE	30	LIN Synch Tolerance Error Interrupt Mask
LINSNRE	29	LIN Slave Not Responding Error Interrupt Mask
LINCE	28	LIN Checksum Error Interrupt Mask
LINIPE	27	LIN Identifier Parity Interrupt Mask
LINISFE	26	LIN Inconsistent Synch Field Error Interrupt Mask
LINBE	25	LIN Bus Error Interrupt Mask
MANE	24	Manchester Error Interrupt Mask
CMP	22	Comparison Interrupt Mask
CTSIC	19	Clear to Send Input Change Interrupt Mask
LINTC	15	LIN Transfer Completed Interrupt Mask
LINID	14	LIN Identifier Sent or LIN Identifier Received Interrupt Mask
LINBK	13	LIN Break Sent or LIN Break Received Interrupt Mask
NACK	13	Non Acknowledge Interrupt Mask
ITER	10	Max Number of Repetitions Reached Interrupt Mask
TXEMPTY	9	TXEMPTY Interrupt Mask
TXEMPTY	9	TXEMPTY Interrupt Mask
TIMEOUT	8	Timeout Interrupt Mask
TIMEOUT	8	Timeout Interrupt Mask
PARE	7	Parity Error Interrupt Mask
PARE	7	Parity Error Interrupt Mask
FRAME	6	Framing Error Interrupt Mask
FRAME	6	Framing Error Interrupt Mask
OVRE	5	Overrun Error Interrupt Mask
OVRE	5	Overrun Error Interrupt Mask
RXBRK	2	Receiver Break Interrupt Mask
TXRDY	1	TXRDY Interrupt Mask
TXRDY	1	TXRDY Interrupt Mask
RXRDY	0	RXRDY Interrupt Mask
RXRDY	0	RXRDY Interrupt Mask
LINHTE	31	LIN Header Timeout Error Interrupt Mask

FLEX_US_CSRUSART Channel Status Register

Address: 0x40014214
Reset: 0x00000000
Access: read only
Size: 32-bit

32 fields

Field	Bits	What it does
LINSTE	30	LIN Synch Tolerance Error
LINSNRE	29	LIN Slave Not Responding Error
LINCE	28	LIN Checksum Error
LINIPE	27	LIN Identifier Parity Error
LINISFE	26	LIN Inconsistent Synch Field Error
LINBE	25	LIN Bit Error
MANE	24	Manchester Error
CTS	23	Image of CTS Input
LINBLS	23	LIN Bus Line Status
CMP	22	Comparison Status
CTSIC	19	Clear to Send Input Change Flag
LINTC	15	LIN Transfer Completed
LINID	14	LIN Identifier Sent or LIN Identifier Received
LINBK	13	LIN Break Sent or LIN Break Received
NACK	13	Non Acknowledge Interrupt
ITER	10	Max Number of Repetitions Reached
TXEMPTY	9	Transmitter Empty (cleared by writing FLEX_US_THR)
TXEMPTY	9	Transmitter Empty (cleared by writing FLEX_US_THR)
TIMEOUT	8	Receiver Timeout
TIMEOUT	8	Receiver Timeout
PARE	7	Parity Error
PARE	7	Parity Error
FRAME	6	Framing Error
FRAME	6	Framing Error
OVRE	5	Overrun Error
OVRE	5	Overrun Error
RXBRK	2	Break Received/End of Break
TXRDY	1	Transmitter Ready (cleared by writing FLEX_US_THR)
TXRDY	1	Transmitter Ready (cleared by writing FLEX_US_THR)
RXRDY	0	Receiver Ready (cleared by reading FLEX_US_RHR)
RXRDY	0	Receiver Ready (cleared by reading FLEX_US_RHR)
LINHTE	31	LIN Header Timeout Error

FLEX_US_RHRUSART Receive Holding Register

Address: 0x40014218
Reset: 0x00000000
Access: read only
Size: 32-bit

6 fields

Field	Bits	What it does
RXCHR2	23:16	Received Character
RXCHR1	15:8	Received Character
RXSYNH	15	Received Sync
RXCHR	8:0	Received Character
RXCHR0	7:0	Received Character
RXCHR3	31:24	Received Character

FLEX_US_THRUSART Transmit Holding Register

Address: 0x4001421C
Reset: 0x00000000
Access: write only
Size: 32-bit

6 fields

Field	Bits	What it does
TXCHR2	23:16	Character to be Transmitted
TXCHR1	15:8	Character to be Transmitted
TXSYNH	15	Sync Field to be Transmitted
TXCHR	8:0	Character to be Transmitted
TXCHR0	7:0	Character to be Transmitted
TXCHR3	31:24	Character to be Transmitted

FLEX_US_BRGRUSART Baud Rate Generator Register

Address: 0x40014220
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
FP	18:16	Fractional Part
CD	15:0	Clock Divider

FLEX_US_RTORUSART Receiver Timeout Register

Address: 0x40014224
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TO	16:0	Timeout Value

FLEX_US_TTGRUSART Transmitter Timeguard Register

Address: 0x40014228
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TG	7:0	Timeguard Value

FLEX_US_FIDIUSART FI DI Ratio Register

Address: 0x40014240
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FI_DI_RATIO	15:0	FI Over DI Ratio Value

FLEX_US_NERUSART Number of Errors Register

Address: 0x40014244
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
NB_ERRORS	7:0	Number of Errors

FLEX_US_IFUSART IrDA Filter Register

Address: 0x4001424C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
IRDA_FILTER	7:0	IrDA Filter

FLEX_US_MANUSART Manchester Configuration Register

Address: 0x40014250
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
DRIFT	30	Drift Compensation
ONE	29	Must Be Set to 1
RX_MPOL	28	Receiver Manchester Polarity
RX_PP	25:24	Receiver Preamble Pattern detected `0` The preamble is composed of '1's `1` The preamble is composed of '0's `2` The preamble is composed of '01's `3` The preamble is composed of '10's
RX_PL	19:16	Receiver Preamble Length
TX_MPOL	12	Transmitter Manchester Polarity
TX_PP	9:8	Transmitter Preamble Pattern `0` The preamble is composed of '1's `1` The preamble is composed of '0's `2` The preamble is composed of '01's `3` The preamble is composed of '10's
TX_PL	3:0	Transmitter Preamble Length
RXIDLEV	31	Receiver Idle Value

FLEX_US_LINMRUSART LIN Mode Register

Address: 0x40014254
Reset: 0x00000000
Access: read/write
Size: 32-bit

10 fields

Field	Bits	What it does
SYNCDIS	17	Synchronization Disable
PDCM	16	DMAC Mode
DLC	15:8	Data Length Control
WKUPTYP	7	Wakeup Signal Type
FSDIS	6	Frame Slot Mode Disable
DLM	5	Data Length Mode
CHKTYP	4	Checksum Type
CHKDIS	3	Checksum Disable
PARDIS	2	Parity Disable
NACT	1:0	LIN Node Action `0` The USART transmits the response. `1` The USART receives the response. `2` The USART does not transmit and does not receive the response.

FLEX_US_LINIRUSART LIN Identifier Register

Address: 0x40014258
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
IDCHR	7:0	Identifier Character

FLEX_US_LINBRRUSART LIN Baud Rate Register

Address: 0x4001425C
Reset: 0x00000000
Access: read only
Size: 32-bit

2 fields

Field	Bits	What it does
LINFP	18:16	Fractional Part after Synchronization
LINCD	15:0	Clock Divider after Synchronization

FLEX_US_LONMRUSART LON Mode Register

Address: 0x40014260
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
EOFS	23:16	End of Frame Condition Size
LCDS	5	LON Collision Detection Source
DMAM	4	LON DMA Mode
CDTAIL	3	LON Collision Detection on Frame Tail
TCOL	2	Terminate Frame upon Collision Notification
COLDET	1	LON Collision Detection Feature
COMMT	0	LON comm_type Parameter Value

FLEX_US_LONPRUSART LON Preamble Register

Address: 0x40014264
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
LONPL	13:0	LON Preamble Length

FLEX_US_LONDLUSART LON Data Length Register

Address: 0x40014268
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
LONDL	7:0	LON Data Length

FLEX_US_LONL2HDRUSART LON L2HDR Register

Address: 0x4001426C
Reset: 0x00000000
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
PB	7	LON Priority Bit
ALTP	6	LON Alternate Path Bit
BLI	5:0	LON Backlog Increment

FLEX_US_LONBLUSART LON Backlog Register

Address: 0x40014270
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
LONBL	5:0	LON Node Backlog Value

FLEX_US_LONB1TXUSART LON Beta1 Tx Register

Address: 0x40014274
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
BETA1TX	23:0	LON Beta1 Length after Transmission

FLEX_US_LONB1RXUSART LON Beta1 Rx Register

Address: 0x40014278
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
BETA1RX	23:0	LON Beta1 Length after Reception

FLEX_US_LONPRIOUSART LON Priority Register

Address: 0x4001427C
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
NPS	14:8	LON Node Priority Slot
PSNB	6:0	LON Priority Slot Number

FLEX_US_IDTTXUSART LON IDT Tx Register

Address: 0x40014280
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
IDTTX	23:0	LON Indeterminate Time after Transmission (comm_type = 1 mode only)

FLEX_US_IDTRXUSART LON IDT Rx Register

Address: 0x40014284
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
IDTRX	23:0	LON Indeterminate Time after Reception (comm_type = 1 mode only)

FLEX_US_ICDIFFUSART IC DIFF Register

Address: 0x40014288
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ICDIFF	3:0	IC Differentiator Number

FLEX_US_CMPRUSART Comparison Register

Address: 0x40014290
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
VAL2	24:16	Second Comparison Value for Received Character
CMPPAR	14	Compare Parity
CMPMODE	12	Comparison Mode `0` Any character is received and comparison function drives CMP flag. `1` Comparison condition must be met to start reception.
VAL1	8:0	First Comparison Value for Received Character

FLEX_US_FMRUSART FIFO Mode Register

Address: 0x400142A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
RXFTHRES2	29:24	Receive FIFO Threshold 2
RXFTHRES	21:16	Receive FIFO Threshold
TXFTHRES	13:8	Transmit FIFO Threshold
FRTSC	7	FIFO RTS Pin Control enable (Hardware Handshaking mode only)
RXRDYM	5:4	Receiver Ready Mode `0` RXRDY will be at level '1' when at least one unread data is in the Receive FIFO `1` RXRDY will be at level '1' when at least two unread data are in the Receive FIFO `2` RXRDY will be at level '1' when at least four unread data are in the Receive FIFO
TXRDYM	1:0	Transmitter Ready Mode `0` TXRDY will be at level '1' when at least one data can be written in the Transmit FIFO `1` TXRDY will be at level '1' when at least two data can be written in the Transmit FIFO `2` TXRDY will be at level '1' when at least four data can be written in the Transmit FIFO

FLEX_US_FLRUSART FIFO Level Register

Address: 0x400142A4
Reset: 0x00000000
Access: read only
Size: 32-bit

2 fields

Field	Bits	What it does
RXFL	21:16	Receive FIFO Level
TXFL	5:0	Transmit FIFO Level

FLEX_US_FIERUSART FIFO Interrupt Enable Register

Address: 0x400142A8
Reset: 0x00000000
Access: write only
Size: 32-bit

9 fields

Field	Bits	What it does
RXFTHF2	9	RXFTHF2 Interrupt Enable
RXFPTEF	7	RXFPTEF Interrupt Enable
TXFPTEF	6	TXFPTEF Interrupt Enable
RXFTHF	5	RXFTHF Interrupt Enable
RXFFF	4	RXFFF Interrupt Enable
RXFEF	3	RXFEF Interrupt Enable
TXFTHF	2	TXFTHF Interrupt Enable
TXFFF	1	TXFFF Interrupt Enable
TXFEF	0	TXFEF Interrupt Enable

FLEX_US_FIDRUSART FIFO Interrupt Disable Register

Address: 0x400142AC
Reset: 0x00000000
Access: write only
Size: 32-bit

9 fields

Field	Bits	What it does
RXFTHF2	9	RXFTHF2 Interrupt Disable
RXFPTEF	7	RXFPTEF Interrupt Disable
TXFPTEF	6	TXFPTEF Interrupt Disable
RXFTHF	5	RXFTHF Interrupt Disable
RXFFF	4	RXFFF Interrupt Disable
RXFEF	3	RXFEF Interrupt Disable
TXFTHF	2	TXFTHF Interrupt Disable
TXFFF	1	TXFFF Interrupt Disable
TXFEF	0	TXFEF Interrupt Disable

FLEX_US_FIMRUSART FIFO Interrupt Mask Register

Address: 0x400142B0
Reset: 0x00000000
Access: read only
Size: 32-bit

9 fields

Field	Bits	What it does
RXFTHF2	9	RXFTHF2 Interrupt Mask
RXFPTEF	7	RXFPTEF Interrupt Mask
TXFPTEF	6	TXFPTEF Interrupt Mask
RXFTHF	5	RXFTHF Interrupt Mask
RXFFF	4	RXFFF Interrupt Mask
RXFEF	3	RXFEF Interrupt Mask
TXFTHF	2	TXFTHF Interrupt Mask
TXFFF	1	TXFFF Interrupt Mask
TXFEF	0	TXFEF Interrupt Mask

FLEX_US_FESRUSART FIFO Event Status Register

Address: 0x400142B4
Reset: 0x00000000
Access: read only
Size: 32-bit

10 fields

Field	Bits	What it does
RXFTHF2	9	Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)
TXFLOCK	8	Transmit FIFO Lock
RXFPTEF	7	Receive FIFO Pointer Error Flag
TXFPTEF	6	Transmit FIFO Pointer Error Flag
RXFTHF	5	Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)
RXFFF	4	Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)
RXFEF	3	Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)
TXFTHF	2	Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)
TXFFF	1	Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)
TXFEF	0	Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)

FLEX_US_WPMRUSART Write Protection Mode Register

Address: 0x400142E4
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
WPEN	0	Write Protection Enable
WPKEY	31:8	Write Protection Key `5591873` Writing any other value in this field aborts the write operation of bit WPEN. Always reads as 0.

FLEX_US_WPSRUSART Write Protection Status Register

Address: 0x400142E8
Reset: 0x00000000
Access: read only
Size: 32-bit

2 fields

Field	Bits	What it does
WPVSRC	23:8	Write Protection Violation Source
WPVS	0	Write Protection Violation Status

FLEX_SPI_CRSPI Control Register

Address: 0x40014400
Reset: 0x00000000
Access: write only
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOEN	30	FIFO Enable
LASTXFER	24	Last Transfer
RXFCLR	17	Receive FIFO Clear
TXFCLR	16	Transmit FIFO Clear
REQCLR	12	Request to Clear the Comparison Trigger
SWRST	7	SPI Software Reset
SPIDIS	1	SPI Disable
SPIEN	0	SPI Enable
FIFODIS	31	FIFO Disable

FLEX_SPI_MRSPI Mode Register

Address: 0x40014404
Reset: 0x00000000
Access: read/write
Size: 32-bit

11 fields

Field	Bits	What it does
PCS	19:16	Peripheral Chip Select
CMPMODE	12	Comparison Mode `0` Any character is received and comparison function drives CMP flag. `1` Comparison condition must be met to start reception of all incoming characters until REQCLR is set.
LBHPC	8	Last Bit Half Period Compatibility
LLB	7	Local Loopback Enable
WDRBT	5	Wait Data Read Before Transfer
MODFDIS	4	Mode Fault Detection
BRSRCCLK	3	Bit Rate Source Clock `0` The peripheral clock is the source clock for the bit rate generation. `1` GCLK is the source clock for the bit rate generation, thus the bit rate can be independent of the core/peripheral clock.
PCSDEC	2	Chip Select Decode
PS	1	Peripheral Select
MSTR	0	Master/Slave Mode
DLYBCS	31:24	Delay Between Chip Selects

FLEX_SPI_RDRSPI Receive Data Register

Address: 0x40014408
Reset: 0x00000000
Access: read only
Size: 32-bit

8 fields

Field	Bits	What it does
RD8_2	23:16	Receive Data
PCS	19:16	Peripheral Chip Select
RD	15:0	Receive Data
RD16_0	15:0	Receive Data
RD8_1	15:8	Receive Data
RD8_0	7:0	Receive Data
RD16_1	31:16	Receive Data
RD8_3	31:24	Receive Data

FLEX_SPI_TDRSPI Transmit Data Register

Address: 0x4001440C
Reset: 0x00000000
Access: write only
Size: 32-bit

5 fields

Field	Bits	What it does
LASTXFER	24	Last Transfer
PCS	19:16	Peripheral Chip Select
TD	15:0	Transmit Data
TD0	15:0	Transmit Data
TD1	31:16	Transmit Data

FLEX_SPI_SRSPI Status Register

Address: 0x40014410
Reset: 0x00000000
Access: read only
Size: 32-bit

18 fields

Field	Bits	What it does
TXFPTEF	30	Transmit FIFO Pointer Error Flag
RXFTHF	29	Receive FIFO Threshold Flag
RXFFF	28	Receive FIFO Full Flag
RXFEF	27	Receive FIFO Empty Flag
TXFTHF	26	Transmit FIFO Threshold Flag (cleared on read)
TXFFF	25	Transmit FIFO Full Flag (cleared on read)
TXFEF	24	Transmit FIFO Empty Flag (cleared on read)
SPIENS	16	SPI Enable Status
SFERR	12	Slave Frame Error (cleared on read)
CMP	11	Comparison Status (cleared on read)
UNDES	10	Underrun Error Status (Slave mode only) (cleared on read)
TXEMPTY	9	Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)
NSSR	8	NSS Rising (cleared on read)
OVRES	3	Overrun Error Status (cleared on read)
MODF	2	Mode Fault Error (cleared on read)
TDRE	1	Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)
RDRF	0	Receive Data Register Full (cleared by reading FLEX_SPI_RDR)
RXFPTEF	31	Receive FIFO Pointer Error Flag

FLEX_SPI_IERSPI Interrupt Enable Register

Address: 0x40014414
Reset: 0x00000000
Access: write only
Size: 32-bit

16 fields

Field	Bits	What it does
TXFPTEF	30	TXFPTEF Interrupt Enable
RXFTHF	29	RXFTHF Interrupt Enable
RXFFF	28	RXFFF Interrupt Enable
RXFEF	27	RXFEF Interrupt Enable
TXFTHF	26	TXFTHF Interrupt Enable
TXFFF	25	TXFFF Interrupt Enable
TXFEF	24	TXFEF Interrupt Enable
CMP	11	Comparison Interrupt Enable
UNDES	10	Underrun Error Interrupt Enable
TXEMPTY	9	Transmission Registers Empty Enable
NSSR	8	NSS Rising Interrupt Enable
OVRES	3	Overrun Error Interrupt Enable
MODF	2	Mode Fault Error Interrupt Enable
TDRE	1	SPI Transmit Data Register Empty Interrupt Enable
RDRF	0	Receive Data Register Full Interrupt Enable
RXFPTEF	31	RXFPTEF Interrupt Enable

FLEX_SPI_IDRSPI Interrupt Disable Register

Address: 0x40014418
Reset: 0x00000000
Access: write only
Size: 32-bit

16 fields

Field	Bits	What it does
TXFPTEF	30	TXFPTEF Interrupt Disable
RXFTHF	29	RXFTHF Interrupt Disable
RXFFF	28	RXFFF Interrupt Disable
RXFEF	27	RXFEF Interrupt Disable
TXFTHF	26	TXFTHF Interrupt Disable
TXFFF	25	TXFFF Interrupt Disable
TXFEF	24	TXFEF Interrupt Disable
CMP	11	Comparison Interrupt Disable
UNDES	10	Underrun Error Interrupt Disable
TXEMPTY	9	Transmission Registers Empty Disable
NSSR	8	NSS Rising Interrupt Disable
OVRES	3	Overrun Error Interrupt Disable
MODF	2	Mode Fault Error Interrupt Disable
TDRE	1	SPI Transmit Data Register Empty Interrupt Disable
RDRF	0	Receive Data Register Full Interrupt Disable
RXFPTEF	31	RXFPTEF Interrupt Disable

FLEX_SPI_IMRSPI Interrupt Mask Register

Address: 0x4001441C
Reset: 0x00000000
Access: read only
Size: 32-bit

16 fields

Field	Bits	What it does
TXFPTEF	30	TXFPTEF Interrupt Mask
RXFTHF	29	RXFTHF Interrupt Mask
RXFFF	28	RXFFF Interrupt Mask
RXFEF	27	RXFEF Interrupt Mask
TXFTHF	26	TXFTHF Interrupt Mask
TXFFF	25	TXFFF Interrupt Mask
TXFEF	24	TXFEF Interrupt Mask
CMP	11	Comparison Interrupt Mask
UNDES	10	Underrun Error Interrupt Mask
TXEMPTY	9	Transmission Registers Empty Mask
NSSR	8	NSS Rising Interrupt Mask
OVRES	3	Overrun Error Interrupt Mask
MODF	2	Mode Fault Error Interrupt Mask
TDRE	1	SPI Transmit Data Register Empty Interrupt Mask
RDRF	0	Receive Data Register Full Interrupt Mask
RXFPTEF	31	RXFPTEF Interrupt Mask

FLEX_SPI_CSR0SPI Chip Select Register

Address: 0x40014430
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
DLYBS	23:16	Delay Before SPCK
SCBR	15:8	Serial Clock Bit Rate
BITS	7:4	Bits Per Transfer `0` 8 bits for transfer `1` 9 bits for transfer `2` 10 bits for transfer `3` 11 bits for transfer `4` 12 bits for transfer `5` 13 bits for transfer `6` 14 bits for transfer `7` 15 bits for transfer `8` 16 bits for transfer
CSAAT	3	Chip Select Active After Transfer
CSNAAT	2	Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
NCPHA	1	Clock Phase
CPOL	0	Clock Polarity
DLYBCT	31:24	Delay Between Consecutive Transfers

FLEX_SPI_CSR1SPI Chip Select Register

Address: 0x40014434
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
DLYBS	23:16	Delay Before SPCK
SCBR	15:8	Serial Clock Bit Rate
BITS	7:4	Bits Per Transfer `0` 8 bits for transfer `1` 9 bits for transfer `2` 10 bits for transfer `3` 11 bits for transfer `4` 12 bits for transfer `5` 13 bits for transfer `6` 14 bits for transfer `7` 15 bits for transfer `8` 16 bits for transfer
CSAAT	3	Chip Select Active After Transfer
CSNAAT	2	Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
NCPHA	1	Clock Phase
CPOL	0	Clock Polarity
DLYBCT	31:24	Delay Between Consecutive Transfers

FLEX_SPI_CSR2SPI Chip Select Register

Address: 0x40014438
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
DLYBS	23:16	Delay Before SPCK
SCBR	15:8	Serial Clock Bit Rate
BITS	7:4	Bits Per Transfer `0` 8 bits for transfer `1` 9 bits for transfer `2` 10 bits for transfer `3` 11 bits for transfer `4` 12 bits for transfer `5` 13 bits for transfer `6` 14 bits for transfer `7` 15 bits for transfer `8` 16 bits for transfer
CSAAT	3	Chip Select Active After Transfer
CSNAAT	2	Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
NCPHA	1	Clock Phase
CPOL	0	Clock Polarity
DLYBCT	31:24	Delay Between Consecutive Transfers

FLEX_SPI_CSR3SPI Chip Select Register

Address: 0x4001443C
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
DLYBS	23:16	Delay Before SPCK
SCBR	15:8	Serial Clock Bit Rate
BITS	7:4	Bits Per Transfer `0` 8 bits for transfer `1` 9 bits for transfer `2` 10 bits for transfer `3` 11 bits for transfer `4` 12 bits for transfer `5` 13 bits for transfer `6` 14 bits for transfer `7` 15 bits for transfer `8` 16 bits for transfer
CSAAT	3	Chip Select Active After Transfer
CSNAAT	2	Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
NCPHA	1	Clock Phase
CPOL	0	Clock Polarity
DLYBCT	31:24	Delay Between Consecutive Transfers

FLEX_SPI_FMRSPI FIFO Mode Register

Address: 0x40014440
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
RXFTHRES	29:24	Receive FIFO Threshold
TXFTHRES	21:16	Transmit FIFO Threshold
RXRDYM	5:4	Receive Data Register Full Mode `0` RDRF will be at level '1' when at least one unread data is in the Receive FIFO. `1` RDRF will be at level '1' when at least two unread data are in the Receive FIFO. Cannot be used when FLEX_SPI_MR.MSTR =1, or if FLEX_SPI_MR.PS =1. `2` RDRF will be at level '1' when at least four unread data are in the Receive FIFO. Cannot be used when FLEX_SPI_CSRx.BITS is greater than 0, or if FLEX_SPI_MR.MSTR =1, or if FLEX_SPI_MR.PS =1.
TXRDYM	1:0	Transmit Data Register Empty Mode `0` TDRE will be at level '1' when at least one data can be written in the Transmit FIFO. `1` TDRE will be at level '1' when at least two data can be written in the Transmit FIFO. Cannot be used if FLEX_SPI_MR.PS =1.

FLEX_SPI_FLRSPI FIFO Level Register

Address: 0x40014444
Reset: 0x00000000
Access: read only
Size: 32-bit

2 fields

Field	Bits	What it does
RXFL	21:16	Receive FIFO Level
TXFL	5:0	Transmit FIFO Level

FLEX_SPI_CMPRSPI Comparison Register

Address: 0x40014448
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
VAL1	15:0	First Comparison Value for Received Character
VAL2	31:16	Second Comparison Value for Received Character

FLEX_SPI_WPMRSPI Write Protection Mode Register

Address: 0x400144E4
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
WPCREN	2	Write Protection Control Enable
WPITEN	1	Write Protection Interrupt Enable
WPEN	0	Write Protection Enable
WPKEY	31:8	Write Protection Key `5460041` Writing any other value in this field aborts the write operation of bits WPEN, WPITEN and WPCREN. Always reads as 0

FLEX_SPI_WPSRSPI Write Protection Status Register

Address: 0x400144E8
Reset: 0x00000000
Access: read only
Size: 32-bit

2 fields

Field	Bits	What it does
WPVSRC	15:8	Write Protection Violation Source
WPVS	0	Write Protection Violation Status

FLEX_TWI_CRTWI Control Register

Address: 0x40014600
Reset: 0x00000000
Access: write only
Size: 32-bit

45 fields

Field	Bits	What it does
FIFODIS	29	FIFO Disable
FIFODIS	29	FIFO Disable
FIFOEN	28	FIFO Enable
FIFOEN	28	FIFO Enable
LOCKCLR	26	Lock Clear
TXFLCLR	26	Transmit FIFO Lock CLEAR
RXFCLR	25	Receive FIFO Clear
THRCLR	24	Transmit Holding Register Clear
TXFCLR	24	Transmit FIFO Clear
ACMDIS	17	Alternative Command Mode Disable
ACMDIS	17	Alternative Command Mode Disable
ACMEN	16	Alternative Command Mode Enable
ACMEN	16	Alternative Command Mode Enable
CLEAR	15	Bus CLEAR Command
CLEAR	15	Bus CLEAR Command
PECRQ	14	PEC Request
PECRQ	14	PEC Request
PECDIS	13	Packet Error Checking Disable
PECDIS	13	Packet Error Checking Disable
PECEN	12	Packet Error Checking Enable
PECEN	12	Packet Error Checking Enable
SMBDIS	11	SMBus Mode Disabled
SMBDIS	11	SMBus Mode Disabled
SMBEN	10	SMBus Mode Enabled
SMBEN	10	SMBus Mode Enabled
HSDIS	9	TWI High-Speed Mode Disabled
HSDIS	9	TWI High-Speed Mode Disabled
HSEN	8	TWI High-Speed Mode Enabled
HSEN	8	TWI High-Speed Mode Enabled
SWRST	7	Software Reset
SWRST	7	Software Reset
QUICK	6	SMBus Quick Command
QUICK	6	SMBus Quick Command
SVDIS	5	TWI Slave Mode Disabled
SVDIS	5	TWI Slave Mode Disabled
SVEN	4	TWI Slave Mode Enabled
SVEN	4	TWI Slave Mode Enabled
MSDIS	3	TWI Master Mode Disabled
MSDIS	3	TWI Master Mode Disabled
MSEN	2	TWI Master Mode Enabled
MSEN	2	TWI Master Mode Enabled
STOP	1	Send a STOP Condition
STOP	1	Send a STOP Condition
START	0	Send a START Condition
START	0	Send a START Condition

FLEX_TWI_MMRTWI Master Mode Register

Address: 0x40014604
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
NOAP	24	No Auto-Stop On NACK Error
DADR	22:16	Device Address
MREAD	12	Master Read Direction
IADRSZ	9:8	Internal Device Address Size `0` No internal device address `1` One-byte internal device address `2` Two-byte internal device address `3` Three-byte internal device address

FLEX_TWI_SMRTWI Slave Mode Register

Address: 0x40014608
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
SADR	22:16	Slave Address
MASK	14:8	Slave Address Mask
SNIFF	7	Slave Sniffer Mode
SCLWSDIS	6	Clock Wait State Disable
BSEL	5	TWI Bus Selection
SADAT	4	Slave Address Treated as Data
SMHH	3	SMBus Host Header
SMDA	2	SMBus Default Address
NACKEN	0	Slave Receiver Data Phase NACK Enable

FLEX_TWI_IADRTWI Internal Address Register

Address: 0x4001460C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
IADR	23:0	Internal Address

FLEX_TWI_CWGRTWI Clock Waveform Generator Register

Address: 0x40014610
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
HOLD	29:24	TWD Hold Time Versus TWCK Falling
BRSRCCLK	20	Bit Rate Source Clock `0` The peripheral clock is the source clock for the bit rate generation. `1` GCLK is the source clock for the bit rate generation, thus the bit rate can be independent of the core/peripheral clock.
CKDIV	18:16	Clock Divider
CHDIV	15:8	Clock High Divider
CLDIV	7:0	Clock Low Divider

FLEX_TWI_SRTWI Status Register

Address: 0x40014620
Reset: 0x00000000
Access: read only
Size: 32-bit

44 fields

Field	Bits	What it does
SR	26	Start Repeated
SR	26	Start Repeated
SDA	25	SDA Line Value
SDA	25	SDA Line Value
SCL	24	SCL Line Value
SCL	24	SCL Line Value
LOCK	23	TWI Lock Due to Frame Errors
TXFLOCK	23	Transmit FIFO Lock
SMBHHM	21	SMBus Host Header Address Match (cleared on read)
SMBHHM	21	SMBus Host Header Address Match (cleared on read)
SMBDAM	20	SMBus Default Address Match (cleared on read)
SMBDAM	20	SMBus Default Address Match (cleared on read)
PECERR	19	PEC Error (cleared on read)
PECERR	19	PEC Error (cleared on read)
TOUT	18	Timeout Error (cleared on read)
TOUT	18	Timeout Error (cleared on read)
SMBAF	17	SMBus Alert Flag (cleared on read)
SMBAF	17	SMBus Alert Flag (cleared on read)
MCACK	16	Master Code Acknowledge (cleared on read)
MCACK	16	Master Code Acknowledge (cleared on read)
EOSACC	11	End Of Slave Access (cleared on read)
EOSACC	11	End Of Slave Access (cleared on read)
SCLWS	10	Clock Wait State
SCLWS	10	Clock Wait State
ARBLST	9	Arbitration Lost (cleared on read)
ARBLST	9	Arbitration Lost (cleared on read)
NACK	8	Not Acknowledged (cleared on read)
NACK	8	Not Acknowledged (cleared on read)
UNRE	7	Underrun Error (cleared on read)
UNRE	7	Underrun Error (cleared on read)
OVRE	6	Overrun Error (cleared on read)
OVRE	6	Overrun Error (cleared on read)
GACC	5	General Call Access (cleared on read)
GACC	5	General Call Access (cleared on read)
SVACC	4	Slave Access
SVACC	4	Slave Access
SVREAD	3	Slave Read
SVREAD	3	Slave Read
TXRDY	2	Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)
TXRDY	2	Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)
RXRDY	1	Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)
RXRDY	1	Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)
TXCOMP	0	Transmission Completed (cleared by writing FLEX_TWI_THR)
TXCOMP	0	Transmission Completed (cleared by writing FLEX_TWI_THR)

FLEX_TWI_IERTWI Interrupt Enable Register

Address: 0x40014624
Reset: 0x00000000
Access: write only
Size: 32-bit

20 fields

Field	Bits	What it does
SMBHHM	21	SMBus Host Header Address Match Interrupt Enable
SMBDAM	20	SMBus Default Address Match Interrupt Enable
PECERR	19	PEC Error Interrupt Enable
TOUT	18	Timeout Error Interrupt Enable
MCACK	16	Master Code Acknowledge Interrupt Enable
TXBUFE	15	Transmit Buffer Empty Interrupt Enable
RXBUFF	14	Receive Buffer Full Interrupt Enable
ENDTX	13	End of Transmit Buffer Interrupt Enable
ENDRX	12	End of Receive Buffer Interrupt Enable
EOSACC	11	End Of Slave Access Interrupt Enable
SCL_WS	10	Clock Wait State Interrupt Enable
ARBLST	9	Arbitration Lost Interrupt Enable
NACK	8	Not Acknowledge Interrupt Enable
UNRE	7	Underrun Error Interrupt Enable
OVRE	6	Overrun Error Interrupt Enable
GACC	5	General Call Access Interrupt Enable
SVACC	4	Slave Access Interrupt Enable
TXRDY	2	Transmit Holding Register Ready Interrupt Enable
RXRDY	1	Receive Holding Register Ready Interrupt Enable
TXCOMP	0	Transmission Completed Interrupt Enable

FLEX_TWI_IDRTWI Interrupt Disable Register

Address: 0x40014628
Reset: 0x00000000
Access: write only
Size: 32-bit

20 fields

Field	Bits	What it does
SMBHHM	21	SMBus Host Header Address Match Interrupt Disable
SMBDAM	20	SMBus Default Address Match Interrupt Disable
PECERR	19	PEC Error Interrupt Disable
TOUT	18	Timeout Error Interrupt Disable
MCACK	16	Master Code Acknowledge Interrupt Disable
TXBUFE	15	Transmit Buffer Empty Interrupt Disable
RXBUFF	14	Receive Buffer Full Interrupt Disable
ENDTX	13	End of Transmit Buffer Interrupt Disable
ENDRX	12	End of Receive Buffer Interrupt Disable
EOSACC	11	End Of Slave Access Interrupt Disable
SCL_WS	10	Clock Wait State Interrupt Disable
ARBLST	9	Arbitration Lost Interrupt Disable
NACK	8	Not Acknowledge Interrupt Disable
UNRE	7	Underrun Error Interrupt Disable
OVRE	6	Overrun Error Interrupt Disable
GACC	5	General Call Access Interrupt Disable
SVACC	4	Slave Access Interrupt Disable
TXRDY	2	Transmit Holding Register Ready Interrupt Disable
RXRDY	1	Receive Holding Register Ready Interrupt Disable
TXCOMP	0	Transmission Completed Interrupt Disable

FLEX_TWI_IMRTWI Interrupt Mask Register

Address: 0x4001462C
Reset: 0x00000000
Access: read only
Size: 32-bit

20 fields

Field	Bits	What it does
SMBHHM	21	SMBus Host Header Address Match Interrupt Mask
SMBDAM	20	SMBus Default Address Match Interrupt Mask
PECERR	19	PEC Error Interrupt Mask
TOUT	18	Timeout Error Interrupt Mask
MCACK	16	Master Code Acknowledge Interrupt Mask
TXBUFE	15	Transmit Buffer Empty Interrupt Mask
RXBUFF	14	Receive Buffer Full Interrupt Mask
ENDTX	13	End of Transmit Buffer Interrupt Mask
ENDRX	12	End of Receive Buffer Interrupt Mask
EOSACC	11	End Of Slave Access Interrupt Mask
SCL_WS	10	Clock Wait State Interrupt Mask
ARBLST	9	Arbitration Lost Interrupt Mask
NACK	8	Not Acknowledge Interrupt Mask
UNRE	7	Underrun Error Interrupt Mask
OVRE	6	Overrun Error Interrupt Mask
GACC	5	General Call Access Interrupt Mask
SVACC	4	Slave Access Interrupt Mask
TXRDY	2	Transmit Holding Register Ready Interrupt Mask
RXRDY	1	Receive Holding Register Ready Interrupt Mask
TXCOMP	0	Transmission Completed Interrupt Mask

FLEX_TWI_RHRTWI Receive Holding Register

Address: 0x40014630
Reset: 0x00000000
Access: read only
Size: 32-bit

8 fields

Field	Bits	What it does
RXDATA2	23:16	Master or Slave Receive Holding Data 2
RXDATA1	15:8	Master or Slave Receive Holding Data 1
ASTATE	12:11	Acknowledge State (Slave Sniffer Mode only) `0` No Acknowledge or Nacknowledge detected after previously logged data `1` Acknowledge (A) detected after previously logged data `2` Nacknowledge (NA) detected after previously logged data `3` Not defined
PSTATE	10	Stop State (Slave Sniffer Mode only)
SSTATE	9:8	Start State (Slave Sniffer Mode only) `0` No START detected with the logged data `1` START (S) detected with the logged data `2` Repeated START (Sr) detected with the logged data `3` Not defined
RXDATA	7:0	Master or Slave Receive Holding Data
RXDATA0	7:0	Master or Slave Receive Holding Data 0
RXDATA3	31:24	Master or Slave Receive Holding Data 3

FLEX_TWI_THRTWI Transmit Holding Register

Address: 0x40014634
Reset: 0x00000000
Access: write only
Size: 32-bit

5 fields

Field	Bits	What it does
TXDATA2	23:16	Master or Slave Transmit Holding Data 2
TXDATA1	15:8	Master or Slave Transmit Holding Data 1
TXDATA	7:0	Master or Slave Transmit Holding Data
TXDATA0	7:0	Master or Slave Transmit Holding Data 0
TXDATA3	31:24	Master or Slave Transmit Holding Data 3

FLEX_TWI_SMBTRTWI SMBus Timing Register

Address: 0x40014638
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TLOWM	23:16	Master Clock Stretch Maximum Cycles
TLOWS	15:8	Slave Clock Stretch Maximum Cycles
PRESC	3:0	SMBus Clock Prescaler
THMAX	31:24	Clock High Maximum Cycles

FLEX_TWI_ACRTWI Alternative Command Register

Address: 0x40014640
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
NPEC	25	Next PEC Request (SMBus Mode only)
NDIR	24	Next Transfer Direction
NDATAL	23:16	Next Data Length
PEC	9	PEC Request (SMBus Mode only)
DIR	8	Transfer Direction
DATAL	7:0	Data Length

FLEX_TWI_FILTRTWI Filter Register

Address: 0x40014644
Reset: 0x00000000
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
THRES	10:8	Digital Filter Threshold
PADFEN	1	PAD Filter Enable
FILT	0	RX Digital Filter

FLEX_TWI_FMRTWI FIFO Mode Register

Address: 0x40014650
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
RXFTHRES	29:24	Receive FIFO Threshold
TXFTHRES	21:16	Transmit FIFO Threshold
RXRDYM	5:4	Receiver Ready Mode `0` RXRDY will be at level '1' when at least one unread data is in the Receive FIFO `1` RXRDY will be at level '1' when at least two unread data are in the Receive FIFO `2` RXRDY will be at level '1' when at least four unread data are in the Receive FIFO
TXRDYM	1:0	Transmitter Ready Mode `0` TXRDY will be at level '1' when at least one data can be written in the Transmit FIFO `1` TXRDY will be at level '1' when at least two data can be written in the Transmit FIFO `2` TXRDY will be at level '1' when at least four data can be written in the Transmit FIFO

FLEX_TWI_FLRTWI FIFO Level Register

Address: 0x40014654
Reset: 0x00000000
Access: read only
Size: 32-bit

2 fields

Field	Bits	What it does
RXFL	21:16	Receive FIFO Level
TXFL	5:0	Transmit FIFO Level

FLEX_TWI_FSRTWI FIFO Status Register

Address: 0x40014660
Reset: 0x00000000
Access: read only
Size: 32-bit

8 fields

Field	Bits	What it does
RXFPTEF	7	Receive FIFO Pointer Error Flag
TXFPTEF	6	Transmit FIFO Pointer Error Flag
RXFTHF	5	Receive FIFO Threshold Flag
RXFFF	4	Receive FIFO Full Flag
RXFEF	3	Receive FIFO Empty Flag
TXFTHF	2	Transmit FIFO Threshold Flag (cleared on read)
TXFFF	1	Transmit FIFO Full Flag (cleared on read)
TXFEF	0	Transmit FIFO Empty Flag (cleared on read)

FLEX_TWI_FIERTWI FIFO Interrupt Enable Register

Address: 0x40014664
Reset: 0x00000000
Access: write only
Size: 32-bit

8 fields

Field	Bits	What it does
RXFPTEF	7	RXFPTEF Interrupt Enable
TXFPTEF	6	TXFPTEF Interrupt Enable
RXFTHF	5	RXFTHF Interrupt Enable
RXFFF	4	RXFFF Interrupt Enable
RXFEF	3	RXFEF Interrupt Enable
TXFTHF	2	TXFTHF Interrupt Enable
TXFFF	1	TXFFF Interrupt Enable
TXFEF	0	TXFEF Interrupt Enable

FLEX_TWI_FIDRTWI FIFO Interrupt Disable Register

Address: 0x40014668
Reset: 0x00000000
Access: write only
Size: 32-bit

8 fields

Field	Bits	What it does
RXFPTEF	7	RXFPTEF Interrupt Disable
TXFPTEF	6	TXFPTEF Interrupt Disable
RXFTHF	5	RXFTHF Interrupt Disable
RXFFF	4	RXFFF Interrupt Disable
RXFEF	3	RXFEF Interrupt Disable
TXFTHF	2	TXFTHF Interrupt Disable
TXFFF	1	TXFFF Interrupt Disable
TXFEF	0	TXFEF Interrupt Disable

FLEX_TWI_FIMRTWI FIFO Interrupt Mask Register

Address: 0x4001466C
Reset: 0x00000000
Access: read only
Size: 32-bit

8 fields

Field	Bits	What it does
RXFPTEF	7	RXFPTEF Interrupt Mask
TXFPTEF	6	TXFPTEF Interrupt Mask
RXFTHF	5	RXFTHF Interrupt Mask
RXFFF	4	RXFFF Interrupt Mask
RXFEF	3	RXFEF Interrupt Mask
TXFTHF	2	TXFTHF Interrupt Mask
TXFFF	1	TXFFF Interrupt Mask
TXFEF	0	TXFEF Interrupt Mask

FLEX_TWI_DRTWI Debug Register

Address: 0x400146D0
Reset: 0x00000000
Access: read only
Size: 32-bit

4 fields

Field	Bits	What it does
TRP	3	Transfer Pending
SWMATCH	2	SleepWalking Match
CLKRQ	1	Clock Request
SWEN	0	SleepWalking Enable

FLEX_TWI_WPMRTWI Write Protection Mode Register

Address: 0x400146E4
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
WPCREN	2	Write Protection Control Enable
WPITEN	1	Write Protection Interrupt Enable
WPEN	0	Write Protection Enable
WPKEY	31:8	Write Protection Key `5527369` Writing any other value in this field aborts the write operation of bits WPEN, WPITEN and WPCREN. Always reads as 0

FLEX_TWI_WPSRTWI Write Protection Status Register

Address: 0x400146E8
Reset: 0x00000000
Access: read only
Size: 32-bit

2 fields

Field	Bits	What it does
WPVS	0	Write Protect Violation Status
WPVSRC	31:8	Write Protection Violation Source