ATSAMRH71F20C SUPC registers

The 6 registers of SUPC (Supply Controller), from 0x40100210, with their reset value and every field. The ATSAMRH71F20C has 3366 registers in 56 peripherals, one page each.

SUPC Supply Controller

SUPC_CRSupply Controller Control Register

Address
0x40100210
Reset
0x00000000
Access
write only
Size
32-bit
4 fields
FieldBitsWhat it does
MDRCSEL5Monitoring Domain RC Oscillator Select
  • 0 No effect.
  • 1 If KEY is correct, XTALSEL switches the slow clock of the monitoring domain (MD_SLCK) on the slow RC oscillator output.
TDXTALSEL3Timing Domain Crystal Oscillator Select
  • 0 No effect.
  • 1 If KEY is correct, XTALSEL switches the slow clock of the timing domain (TD_SLCK) on the 32.768 kHz crystal oscillator output.
ZERO2Shall be always write at '0'
KEY31:24Password
  • 165 Writing any other value in this field aborts the write operation.

SUPC_SMMRSupply Controller Supply Monitor Mode Register

Address
0x40100214
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CORESMUSEL23Core Supply Monitor User Selection

SUPC_MRSupply Controller Mode Register

Address
0x40100218
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
FXTALSTUP22Fast Startup 32.768 kHz Crystal Oscillator
OSCBYPASS20Oscillator Bypass
  • 0 No effect. Clock selection depends on the value of XTALSEL (SUPC_CR).
  • 1 The 32.768 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL.
CORSMDIS13VDDCORE Supply Monitor Disable
  • 0 The VDDCORE supply monitor is enabled.
  • 1 The VDDCORE supply monitor is disabled.
CORSMRSTEN12VDDCORE Supply Monitor Reset Enable
  • 0 The core reset signal vddcore_nreset is not affected when a VDDCORE supply monitor detection occurs.
  • 1 The core reset signal, vddcore_nreset is asserted when a VDDCORE supply monitor detection occurs.
KEY31:24Password Key
  • 165 Writing any other value in this field aborts the write operation.

SUPC_SRSupply Controller Status Register

Address
0x40100224
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
TDOSCSEL732 kHz Oscillator Selection Status
  • 0 The timing domain slow clock, TD_SLCK, is generated by the slow RC oscillator.
  • 1 The timing domain slow clock, TD_SLCK, is generated by the 32.768 kHz crystal oscillator.
CORSMRSTS3VDDCORE Supply Monitor Reset Status (cleared on read)
  • 0 No VDDCORE Supply Monitor reset event has been detected since the last read of the SUPC_SR.
  • 1 At least one VDDCORE Supply Monitor reset event has been detected since the last read of the SUPC_SR.

SUPC_PWRSupply Controller Power Register

Address
0x4010022C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ZERO18MD_SLCK always generated by the slow RC oscillator

SYSC_WPMRWrite Protection Mode Register

Address
0x401002E4
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
WPEN0Write Protection Enable
WPKEY31:8Write Protection Key.
  • 5395523 Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.