ATSAMV71J19B SUPC registers

The 7 registers of SUPC (Supply Controller), from 0x400E1810, with their reset value and every field. The ATSAMV71J19B has 2417 registers in 55 peripherals, one page each.

SUPC Supply Controller

SUPC_CRSupply Controller Control Register

Address
0x400E1810
Reset
0x00000000
Access
write only
Size
32-bit
3 fields
FieldBitsWhat it does
XTALSEL3Crystal Oscillator Select
  • 0 No effect.
  • 1 If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output.
VROFF2Voltage Regulator Off
  • 0 No effect.
  • 1 If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator.
KEY31:24Password
  • 165 Writing any other value in this field aborts the write operation.

SUPC_SMMRSupply Controller Supply Monitor Mode Register

Address
0x400E1814
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
SMIEN13Supply Monitor Interrupt Enable
  • 0 The SUPC interrupt signal is not affected when a supply monitor detection occurs.
  • 1 The SUPC interrupt signal is asserted when a supply monitor detection occurs.
SMRSTEN12Supply Monitor Reset Enable
  • 0 The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs.
  • 1 The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs.
SMSMPL10:8Supply Monitor Sampling Period
  • 0 Supply Monitor disabled
  • 1 Continuous Supply Monitor
  • 2 Supply Monitor enabled one SLCK period every 32 SLCK periods
  • 3 Supply Monitor enabled one SLCK period every 256 SLCK periods
  • 4 Supply Monitor enabled one SLCK period every 2,048 SLCK periods
SMTH3:0Supply Monitor Threshold

SUPC_MRSupply Controller Mode Register

Address
0x400E1818
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
OSCBYPASS20Oscillator Bypass
  • 0 No effect. Clock selection depends on the value of XTALSEL (SUPC_CR).
  • 1 The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL.
BKUPRETON17SRAM On In Backup Mode
ONREG14Voltage Regulator Enable
  • 0 Internal voltage regulator is not used (external power supply is used).
  • 1 Internal voltage regulator is used.
BODDIS13Brownout Detector Disable
  • 0 The core brownout detector is enabled.
  • 1 The core brownout detector is disabled.
BODRSTEN12Brownout Detector Reset Enable
  • 0 The core reset signal vddcore_nreset is not affected when a brownout detection occurs.
  • 1 The core reset signal, vddcore_nreset is asserted when a brownout detection occurs.
KEY31:24Password Key
  • 165 Writing any other value in this field aborts the write operation.

SUPC_WUMRSupply Controller Wake-up Mode Register

Address
0x400E181C
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
LPDBC18:16Low-power Debouncer Period
  • 0 Disable the low-power debouncers.
  • 1 WKUP0/1 in active state for at least 2 RTCOUTx clock periods
  • 2 WKUP0/1 in active state for at least 3 RTCOUTx clock periods
  • 3 WKUP0/1 in active state for at least 4 RTCOUTx clock periods
  • 4 WKUP0/1 in active state for at least 5 RTCOUTx clock periods
  • 5 WKUP0/1 in active state for at least 6 RTCOUTx clock periods
  • 6 WKUP0/1 in active state for at least 7 RTCOUTx clock periods
  • 7 WKUP0/1 in active state for at least 8 RTCOUTx clock periods
WKUPDBC14:12Wake-up Inputs Debouncer Period
  • 0 Immediate, no debouncing, detected active at least on one Slow Clock edge.
  • 1 WKUPx shall be in its active state for at least 3 SLCK periods
  • 2 WKUPx shall be in its active state for at least 32 SLCK periods
  • 3 WKUPx shall be in its active state for at least 512 SLCK periods
  • 4 WKUPx shall be in its active state for at least 4,096 SLCK periods
  • 5 WKUPx shall be in its active state for at least 32,768 SLCK periods
LPDBCCLR7Low-power Debouncer Clear
  • 0 A low-power debounce event does not create an immediate clear on the first half of GPBR registers.
  • 1 A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers.
LPDBCEN16Low-power Debouncer Enable WKUP1
  • 0 The WKUP1 input pin is not connected to the low-power debouncer.
  • 1 The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up.
LPDBCEN05Low-power Debouncer Enable WKUP0
  • 0 The WKUP0 input pin is not connected to the low-power debouncer.
  • 1 The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up.
RTCEN3Real-time Clock Wake-up Enable
  • 0 The RTC alarm signal has no wake-up effect.
  • 1 The RTC alarm signal forces the wake-up of the core power supply.
RTTEN2Real-time Timer Wake-up Enable
  • 0 The RTT alarm signal has no wake-up effect.
  • 1 The RTT alarm signal forces the wake-up of the core power supply.
SMEN1Supply Monitor Wake-up Enable
  • 0 The supply monitor detection has no wake-up effect.
  • 1 The supply monitor detection forces the wake-up of the core power supply.

SUPC_WUIRSupply Controller Wake-up Inputs Register

Address
0x400E1820
Reset
0x00000000
Access
read/write
Size
32-bit
28 fields
FieldBitsWhat it does
WKUPT1329Wake-up Input Type 0 to 13
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
WKUPT1228Wake-up Input Type 0 to 12
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
WKUPT1127Wake-up Input Type 0 to 11
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
WKUPT1026Wake-up Input Type 0 to 10
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
WKUPT925Wake-up Input Type 0 to 9
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
WKUPT824Wake-up Input Type 0 to 8
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
WKUPT723Wake-up Input Type 0 to 7
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
WKUPT622Wake-up Input Type 0 to 6
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
WKUPT521Wake-up Input Type 0 to 5
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
WKUPT420Wake-up Input Type 0 to 4
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
WKUPT319Wake-up Input Type 0 to 3
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
WKUPT218Wake-up Input Type 0 to 2
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
WKUPT117Wake-up Input Type 0 to 1
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
WKUPT016Wake-up Input Type 0 to 0
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
WKUPEN1313Wake-up Input Enable 0 to 13
  • 0 The corresponding wake-up input has no wake-up effect.
  • 1 The corresponding wake-up input is enabled for a wake-up of the core power supply.
WKUPEN1212Wake-up Input Enable 0 to 12
  • 0 The corresponding wake-up input has no wake-up effect.
  • 1 The corresponding wake-up input is enabled for a wake-up of the core power supply.
WKUPEN1111Wake-up Input Enable 0 to 11
  • 0 The corresponding wake-up input has no wake-up effect.
  • 1 The corresponding wake-up input is enabled for a wake-up of the core power supply.
WKUPEN1010Wake-up Input Enable 0 to 10
  • 0 The corresponding wake-up input has no wake-up effect.
  • 1 The corresponding wake-up input is enabled for a wake-up of the core power supply.
WKUPEN99Wake-up Input Enable 0 to 9
  • 0 The corresponding wake-up input has no wake-up effect.
  • 1 The corresponding wake-up input is enabled for a wake-up of the core power supply.
WKUPEN88Wake-up Input Enable 0 to 8
  • 0 The corresponding wake-up input has no wake-up effect.
  • 1 The corresponding wake-up input is enabled for a wake-up of the core power supply.
WKUPEN77Wake-up Input Enable 0 to 7
  • 0 The corresponding wake-up input has no wake-up effect.
  • 1 The corresponding wake-up input is enabled for a wake-up of the core power supply.
WKUPEN66Wake-up Input Enable 0 to 6
  • 0 The corresponding wake-up input has no wake-up effect.
  • 1 The corresponding wake-up input is enabled for a wake-up of the core power supply.
WKUPEN55Wake-up Input Enable 0 to 5
  • 0 The corresponding wake-up input has no wake-up effect.
  • 1 The corresponding wake-up input is enabled for a wake-up of the core power supply.
WKUPEN44Wake-up Input Enable 0 to 4
  • 0 The corresponding wake-up input has no wake-up effect.
  • 1 The corresponding wake-up input is enabled for a wake-up of the core power supply.
WKUPEN33Wake-up Input Enable 0 to 3
  • 0 The corresponding wake-up input has no wake-up effect.
  • 1 The corresponding wake-up input is enabled for a wake-up of the core power supply.
WKUPEN22Wake-up Input Enable 0 to 2
  • 0 The corresponding wake-up input has no wake-up effect.
  • 1 The corresponding wake-up input is enabled for a wake-up of the core power supply.
WKUPEN11Wake-up Input Enable 0 to 1
  • 0 The corresponding wake-up input has no wake-up effect.
  • 1 The corresponding wake-up input is enabled for a wake-up of the core power supply.
WKUPEN00Wake-up Input Enable 0 to 0
  • 0 The corresponding wake-up input has no wake-up effect.
  • 1 The corresponding wake-up input is enabled for a wake-up of the core power supply.

SUPC_SRSupply Controller Status Register

Address
0x400E1824
Reset
0x00000000
Access
read only
Size
32-bit
23 fields
FieldBitsWhat it does
WKUPIS1329WKUPx Input Status (cleared on read)
  • 0 The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
  • 1 The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
WKUPIS1228WKUPx Input Status (cleared on read)
  • 0 The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
  • 1 The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
WKUPIS1127WKUPx Input Status (cleared on read)
  • 0 The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
  • 1 The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
WKUPIS1026WKUPx Input Status (cleared on read)
  • 0 The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
  • 1 The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
WKUPIS925WKUPx Input Status (cleared on read)
  • 0 The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
  • 1 The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
WKUPIS824WKUPx Input Status (cleared on read)
  • 0 The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
  • 1 The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
WKUPIS723WKUPx Input Status (cleared on read)
  • 0 The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
  • 1 The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
WKUPIS622WKUPx Input Status (cleared on read)
  • 0 The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
  • 1 The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
WKUPIS521WKUPx Input Status (cleared on read)
  • 0 The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
  • 1 The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
WKUPIS420WKUPx Input Status (cleared on read)
  • 0 The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
  • 1 The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
WKUPIS319WKUPx Input Status (cleared on read)
  • 0 The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
  • 1 The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
WKUPIS218WKUPx Input Status (cleared on read)
  • 0 The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
  • 1 The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
WKUPIS117WKUPx Input Status (cleared on read)
  • 0 The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
  • 1 The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
WKUPIS016WKUPx Input Status (cleared on read)
  • 0 The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
  • 1 The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
LPDBCS114Low-power Debouncer Wake-up Status on WKUP1 (cleared on read)
  • 0 No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.
  • 1 At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.
LPDBCS013Low-power Debouncer Wake-up Status on WKUP0 (cleared on read)
  • 0 No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.
  • 1 At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.
OSCSEL732-kHz Oscillator Selection Status
  • 0 The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator.
  • 1 The slow clock, SLCK, is generated by the 32 kHz crystal oscillator.
SMOS6Supply Monitor Output Status
  • 0 The supply monitor detected VDDIO higher than its threshold at its last measurement.
  • 1 The supply monitor detected VDDIO lower than its threshold at its last measurement.
SMS5Supply Monitor Status (cleared on read)
  • 0 No supply monitor detection since the last read of SUPC_SR.
  • 1 At least one supply monitor detection since the last read of SUPC_SR.
SMRSTS4Supply Monitor Reset Status (cleared on read)
  • 0 No supply monitor detection has generated a core reset since the last read of the SUPC_SR.
  • 1 At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR.
BODRSTS3Brownout Detector Reset Status (cleared on read)
  • 0 No core brownout rising edge event has been detected since the last read of the SUPC_SR.
  • 1 At least one brownout output rising edge event has been detected since the last read of the SUPC_SR.
SMWS2Supply Monitor Detection Wake-up Status (cleared on read)
  • 0 No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR.
  • 1 At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR.
WKUPS1WKUP Wake-up Status (cleared on read)
  • 0 No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.
  • 1 At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.

SYSC_WPMRWrite Protection Mode Register

Address
0x400E18E4
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
WPEN0Write Protection Enable
WPKEY31:8Write Protection Key
  • 5395523 Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.