ATSAMV71J19B USBHS registers The 241 registers of USBHS (USB High-Speed Interface), from 0x40038000, with their reset value and every field. The ATSAMV71J19B has 2417 registers in 55 peripherals, one page each.
USBHS USB High-Speed Interface USBHS_DEVCTRLDevice General Control Register
Address 0x40038000
Reset 0x00000000
Access read/write
Size 32-bit 10 fields
Field Bits What it does OPMODE2 16 Specific Operational mode TSTPCKT 15 Test packet mode TSTK 14 Test mode K TSTJ 13 Test mode J LS 12 Low-Speed Mode Force SPDCONF 11:10 Mode Configuration0 The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable.1 For a better consumption, if high speed is not needed.2 Forced high speed.3 The peripheral remains in Full-speed mode whatever the host speed capability. RMWKUP 9 Remote Wake-Up DETACH 8 Detach ADDEN 7 Address Enable UADD 6:0 USB Address
USBHS_DEVISRDevice Global Interrupt Status Register
Address 0x40038004
Reset 0x00000000
Access read only
Size 32-bit 24 fields
Field Bits What it does DMA_6 30 DMA Channel 6 Interrupt DMA_5 29 DMA Channel 5 Interrupt DMA_4 28 DMA Channel 4 Interrupt DMA_3 27 DMA Channel 3 Interrupt DMA_2 26 DMA Channel 2 Interrupt DMA_1 25 DMA Channel 1 Interrupt PEP_9 21 Endpoint 9 Interrupt PEP_8 20 Endpoint 8 Interrupt PEP_7 19 Endpoint 7 Interrupt PEP_6 18 Endpoint 6 Interrupt PEP_5 17 Endpoint 5 Interrupt PEP_4 16 Endpoint 4 Interrupt PEP_3 15 Endpoint 3 Interrupt PEP_2 14 Endpoint 2 Interrupt PEP_1 13 Endpoint 1 Interrupt PEP_0 12 Endpoint 0 Interrupt UPRSM 6 Upstream Resume Interrupt EORSM 5 End of Resume Interrupt WAKEUP 4 Wake-Up Interrupt EORST 3 End of Reset Interrupt SOF 2 Start of Frame Interrupt MSOF 1 Micro Start of Frame Interrupt SUSP 0 Suspend Interrupt DMA_7 31 DMA Channel 7 Interrupt
USBHS_DEVICRDevice Global Interrupt Clear Register
Address 0x40038008
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does UPRSMC 6 Upstream Resume Interrupt Clear EORSMC 5 End of Resume Interrupt Clear WAKEUPC 4 Wake-Up Interrupt Clear EORSTC 3 End of Reset Interrupt Clear SOFC 2 Start of Frame Interrupt Clear MSOFC 1 Micro Start of Frame Interrupt Clear SUSPC 0 Suspend Interrupt Clear
USBHS_DEVIFRDevice Global Interrupt Set Register
Address 0x4003800C
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does DMA_6 30 DMA Channel 6 Interrupt Set DMA_5 29 DMA Channel 5 Interrupt Set DMA_4 28 DMA Channel 4 Interrupt Set DMA_3 27 DMA Channel 3 Interrupt Set DMA_2 26 DMA Channel 2 Interrupt Set DMA_1 25 DMA Channel 1 Interrupt Set UPRSMS 6 Upstream Resume Interrupt Set EORSMS 5 End of Resume Interrupt Set WAKEUPS 4 Wake-Up Interrupt Set EORSTS 3 End of Reset Interrupt Set SOFS 2 Start of Frame Interrupt Set MSOFS 1 Micro Start of Frame Interrupt Set SUSPS 0 Suspend Interrupt Set DMA_7 31 DMA Channel 7 Interrupt Set
USBHS_DEVIMRDevice Global Interrupt Mask Register
Address 0x40038010
Reset 0x00000000
Access read only
Size 32-bit 24 fields
Field Bits What it does DMA_6 30 DMA Channel 6 Interrupt Mask DMA_5 29 DMA Channel 5 Interrupt Mask DMA_4 28 DMA Channel 4 Interrupt Mask DMA_3 27 DMA Channel 3 Interrupt Mask DMA_2 26 DMA Channel 2 Interrupt Mask DMA_1 25 DMA Channel 1 Interrupt Mask PEP_9 21 Endpoint 9 Interrupt Mask PEP_8 20 Endpoint 8 Interrupt Mask PEP_7 19 Endpoint 7 Interrupt Mask PEP_6 18 Endpoint 6 Interrupt Mask PEP_5 17 Endpoint 5 Interrupt Mask PEP_4 16 Endpoint 4 Interrupt Mask PEP_3 15 Endpoint 3 Interrupt Mask PEP_2 14 Endpoint 2 Interrupt Mask PEP_1 13 Endpoint 1 Interrupt Mask PEP_0 12 Endpoint 0 Interrupt Mask UPRSME 6 Upstream Resume Interrupt Mask EORSME 5 End of Resume Interrupt Mask WAKEUPE 4 Wake-Up Interrupt Mask EORSTE 3 End of Reset Interrupt Mask SOFE 2 Start of Frame Interrupt Mask MSOFE 1 Micro Start of Frame Interrupt Mask SUSPE 0 Suspend Interrupt Mask DMA_7 31 DMA Channel 7 Interrupt Mask
USBHS_DEVIDRDevice Global Interrupt Disable Register
Address 0x40038014
Reset 0x00000000
Access write only
Size 32-bit 24 fields
Field Bits What it does DMA_6 30 DMA Channel 6 Interrupt Disable DMA_5 29 DMA Channel 5 Interrupt Disable DMA_4 28 DMA Channel 4 Interrupt Disable DMA_3 27 DMA Channel 3 Interrupt Disable DMA_2 26 DMA Channel 2 Interrupt Disable DMA_1 25 DMA Channel 1 Interrupt Disable PEP_9 21 Endpoint 9 Interrupt Disable PEP_8 20 Endpoint 8 Interrupt Disable PEP_7 19 Endpoint 7 Interrupt Disable PEP_6 18 Endpoint 6 Interrupt Disable PEP_5 17 Endpoint 5 Interrupt Disable PEP_4 16 Endpoint 4 Interrupt Disable PEP_3 15 Endpoint 3 Interrupt Disable PEP_2 14 Endpoint 2 Interrupt Disable PEP_1 13 Endpoint 1 Interrupt Disable PEP_0 12 Endpoint 0 Interrupt Disable UPRSMEC 6 Upstream Resume Interrupt Disable EORSMEC 5 End of Resume Interrupt Disable WAKEUPEC 4 Wake-Up Interrupt Disable EORSTEC 3 End of Reset Interrupt Disable SOFEC 2 Start of Frame Interrupt Disable MSOFEC 1 Micro Start of Frame Interrupt Disable SUSPEC 0 Suspend Interrupt Disable DMA_7 31 DMA Channel 7 Interrupt Disable
USBHS_DEVIERDevice Global Interrupt Enable Register
Address 0x40038018
Reset 0x00000000
Access write only
Size 32-bit 24 fields
Field Bits What it does DMA_6 30 DMA Channel 6 Interrupt Enable DMA_5 29 DMA Channel 5 Interrupt Enable DMA_4 28 DMA Channel 4 Interrupt Enable DMA_3 27 DMA Channel 3 Interrupt Enable DMA_2 26 DMA Channel 2 Interrupt Enable DMA_1 25 DMA Channel 1 Interrupt Enable PEP_9 21 Endpoint 9 Interrupt Enable PEP_8 20 Endpoint 8 Interrupt Enable PEP_7 19 Endpoint 7 Interrupt Enable PEP_6 18 Endpoint 6 Interrupt Enable PEP_5 17 Endpoint 5 Interrupt Enable PEP_4 16 Endpoint 4 Interrupt Enable PEP_3 15 Endpoint 3 Interrupt Enable PEP_2 14 Endpoint 2 Interrupt Enable PEP_1 13 Endpoint 1 Interrupt Enable PEP_0 12 Endpoint 0 Interrupt Enable UPRSMES 6 Upstream Resume Interrupt Enable EORSMES 5 End of Resume Interrupt Enable WAKEUPES 4 Wake-Up Interrupt Enable EORSTES 3 End of Reset Interrupt Enable SOFES 2 Start of Frame Interrupt Enable MSOFES 1 Micro Start of Frame Interrupt Enable SUSPES 0 Suspend Interrupt Enable DMA_7 31 DMA Channel 7 Interrupt Enable
USBHS_DEVEPTDevice Endpoint Register
Address 0x4003801C
Reset 0x00000000
Access read/write
Size 32-bit 20 fields
Field Bits What it does EPRST9 25 Endpoint 9 Reset EPRST8 24 Endpoint 8 Reset EPRST7 23 Endpoint 7 Reset EPRST6 22 Endpoint 6 Reset EPRST5 21 Endpoint 5 Reset EPRST4 20 Endpoint 4 Reset EPRST3 19 Endpoint 3 Reset EPRST2 18 Endpoint 2 Reset EPRST1 17 Endpoint 1 Reset EPRST0 16 Endpoint 0 Reset EPEN9 9 Endpoint 9 Enable EPEN8 8 Endpoint 8 Enable EPEN7 7 Endpoint 7 Enable EPEN6 6 Endpoint 6 Enable EPEN5 5 Endpoint 5 Enable EPEN4 4 Endpoint 4 Enable EPEN3 3 Endpoint 3 Enable EPEN2 2 Endpoint 2 Enable EPEN1 1 Endpoint 1 Enable EPEN0 0 Endpoint 0 Enable
USBHS_DEVFNUMDevice Frame Number Register
Address 0x40038020
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does FNCERR 15 Frame Number CRC Error FNUM 13:3 Frame Number MFNUM 2:0 Micro Frame Number
USBHS_DEVEPTCFG0Device Endpoint Configuration Register
Address 0x40038100
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does NBTRANS 14:13 Number of transactions per microframe for isochronous endpoint0 Reserved to endpoint that does not have the high-bandwidth isochronous capability.1 Default value: one transaction per microframe.2 Two transactions per microframe. This endpoint should be configured as double-bank.3 Three transactions per microframe. This endpoint should be configured as triple-bank. EPTYPE 12:11 Endpoint Type0 Control1 Isochronous2 Bulk3 Interrupt AUTOSW 9 Automatic Switch EPDIR 8 Endpoint Direction0 The endpoint direction is OUT.1 The endpoint direction is IN (nor for control endpoints). EPSIZE 6:4 Endpoint Size0 8 bytes1 16 bytes2 32 bytes3 64 bytes4 128 bytes5 256 bytes6 512 bytes7 1024 bytes EPBK 3:2 Endpoint Banks0 Single-bank endpoint1 Double-bank endpoint2 Triple-bank endpoint ALLOC 1 Endpoint Memory Allocate
USBHS_DEVEPTCFG1Device Endpoint Configuration Register
Address 0x40038104
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does NBTRANS 14:13 Number of transactions per microframe for isochronous endpoint0 Reserved to endpoint that does not have the high-bandwidth isochronous capability.1 Default value: one transaction per microframe.2 Two transactions per microframe. This endpoint should be configured as double-bank.3 Three transactions per microframe. This endpoint should be configured as triple-bank. EPTYPE 12:11 Endpoint Type0 Control1 Isochronous2 Bulk3 Interrupt AUTOSW 9 Automatic Switch EPDIR 8 Endpoint Direction0 The endpoint direction is OUT.1 The endpoint direction is IN (nor for control endpoints). EPSIZE 6:4 Endpoint Size0 8 bytes1 16 bytes2 32 bytes3 64 bytes4 128 bytes5 256 bytes6 512 bytes7 1024 bytes EPBK 3:2 Endpoint Banks0 Single-bank endpoint1 Double-bank endpoint2 Triple-bank endpoint ALLOC 1 Endpoint Memory Allocate
USBHS_DEVEPTCFG2Device Endpoint Configuration Register
Address 0x40038108
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does NBTRANS 14:13 Number of transactions per microframe for isochronous endpoint0 Reserved to endpoint that does not have the high-bandwidth isochronous capability.1 Default value: one transaction per microframe.2 Two transactions per microframe. This endpoint should be configured as double-bank.3 Three transactions per microframe. This endpoint should be configured as triple-bank. EPTYPE 12:11 Endpoint Type0 Control1 Isochronous2 Bulk3 Interrupt AUTOSW 9 Automatic Switch EPDIR 8 Endpoint Direction0 The endpoint direction is OUT.1 The endpoint direction is IN (nor for control endpoints). EPSIZE 6:4 Endpoint Size0 8 bytes1 16 bytes2 32 bytes3 64 bytes4 128 bytes5 256 bytes6 512 bytes7 1024 bytes EPBK 3:2 Endpoint Banks0 Single-bank endpoint1 Double-bank endpoint2 Triple-bank endpoint ALLOC 1 Endpoint Memory Allocate
USBHS_DEVEPTCFG3Device Endpoint Configuration Register
Address 0x4003810C
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does NBTRANS 14:13 Number of transactions per microframe for isochronous endpoint0 Reserved to endpoint that does not have the high-bandwidth isochronous capability.1 Default value: one transaction per microframe.2 Two transactions per microframe. This endpoint should be configured as double-bank.3 Three transactions per microframe. This endpoint should be configured as triple-bank. EPTYPE 12:11 Endpoint Type0 Control1 Isochronous2 Bulk3 Interrupt AUTOSW 9 Automatic Switch EPDIR 8 Endpoint Direction0 The endpoint direction is OUT.1 The endpoint direction is IN (nor for control endpoints). EPSIZE 6:4 Endpoint Size0 8 bytes1 16 bytes2 32 bytes3 64 bytes4 128 bytes5 256 bytes6 512 bytes7 1024 bytes EPBK 3:2 Endpoint Banks0 Single-bank endpoint1 Double-bank endpoint2 Triple-bank endpoint ALLOC 1 Endpoint Memory Allocate
USBHS_DEVEPTCFG4Device Endpoint Configuration Register
Address 0x40038110
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does NBTRANS 14:13 Number of transactions per microframe for isochronous endpoint0 Reserved to endpoint that does not have the high-bandwidth isochronous capability.1 Default value: one transaction per microframe.2 Two transactions per microframe. This endpoint should be configured as double-bank.3 Three transactions per microframe. This endpoint should be configured as triple-bank. EPTYPE 12:11 Endpoint Type0 Control1 Isochronous2 Bulk3 Interrupt AUTOSW 9 Automatic Switch EPDIR 8 Endpoint Direction0 The endpoint direction is OUT.1 The endpoint direction is IN (nor for control endpoints). EPSIZE 6:4 Endpoint Size0 8 bytes1 16 bytes2 32 bytes3 64 bytes4 128 bytes5 256 bytes6 512 bytes7 1024 bytes EPBK 3:2 Endpoint Banks0 Single-bank endpoint1 Double-bank endpoint2 Triple-bank endpoint ALLOC 1 Endpoint Memory Allocate
USBHS_DEVEPTCFG5Device Endpoint Configuration Register
Address 0x40038114
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does NBTRANS 14:13 Number of transactions per microframe for isochronous endpoint0 Reserved to endpoint that does not have the high-bandwidth isochronous capability.1 Default value: one transaction per microframe.2 Two transactions per microframe. This endpoint should be configured as double-bank.3 Three transactions per microframe. This endpoint should be configured as triple-bank. EPTYPE 12:11 Endpoint Type0 Control1 Isochronous2 Bulk3 Interrupt AUTOSW 9 Automatic Switch EPDIR 8 Endpoint Direction0 The endpoint direction is OUT.1 The endpoint direction is IN (nor for control endpoints). EPSIZE 6:4 Endpoint Size0 8 bytes1 16 bytes2 32 bytes3 64 bytes4 128 bytes5 256 bytes6 512 bytes7 1024 bytes EPBK 3:2 Endpoint Banks0 Single-bank endpoint1 Double-bank endpoint2 Triple-bank endpoint ALLOC 1 Endpoint Memory Allocate
USBHS_DEVEPTCFG6Device Endpoint Configuration Register
Address 0x40038118
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does NBTRANS 14:13 Number of transactions per microframe for isochronous endpoint0 Reserved to endpoint that does not have the high-bandwidth isochronous capability.1 Default value: one transaction per microframe.2 Two transactions per microframe. This endpoint should be configured as double-bank.3 Three transactions per microframe. This endpoint should be configured as triple-bank. EPTYPE 12:11 Endpoint Type0 Control1 Isochronous2 Bulk3 Interrupt AUTOSW 9 Automatic Switch EPDIR 8 Endpoint Direction0 The endpoint direction is OUT.1 The endpoint direction is IN (nor for control endpoints). EPSIZE 6:4 Endpoint Size0 8 bytes1 16 bytes2 32 bytes3 64 bytes4 128 bytes5 256 bytes6 512 bytes7 1024 bytes EPBK 3:2 Endpoint Banks0 Single-bank endpoint1 Double-bank endpoint2 Triple-bank endpoint ALLOC 1 Endpoint Memory Allocate
USBHS_DEVEPTCFG7Device Endpoint Configuration Register
Address 0x4003811C
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does NBTRANS 14:13 Number of transactions per microframe for isochronous endpoint0 Reserved to endpoint that does not have the high-bandwidth isochronous capability.1 Default value: one transaction per microframe.2 Two transactions per microframe. This endpoint should be configured as double-bank.3 Three transactions per microframe. This endpoint should be configured as triple-bank. EPTYPE 12:11 Endpoint Type0 Control1 Isochronous2 Bulk3 Interrupt AUTOSW 9 Automatic Switch EPDIR 8 Endpoint Direction0 The endpoint direction is OUT.1 The endpoint direction is IN (nor for control endpoints). EPSIZE 6:4 Endpoint Size0 8 bytes1 16 bytes2 32 bytes3 64 bytes4 128 bytes5 256 bytes6 512 bytes7 1024 bytes EPBK 3:2 Endpoint Banks0 Single-bank endpoint1 Double-bank endpoint2 Triple-bank endpoint ALLOC 1 Endpoint Memory Allocate
USBHS_DEVEPTCFG8Device Endpoint Configuration Register
Address 0x40038120
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does NBTRANS 14:13 Number of transactions per microframe for isochronous endpoint0 Reserved to endpoint that does not have the high-bandwidth isochronous capability.1 Default value: one transaction per microframe.2 Two transactions per microframe. This endpoint should be configured as double-bank.3 Three transactions per microframe. This endpoint should be configured as triple-bank. EPTYPE 12:11 Endpoint Type0 Control1 Isochronous2 Bulk3 Interrupt AUTOSW 9 Automatic Switch EPDIR 8 Endpoint Direction0 The endpoint direction is OUT.1 The endpoint direction is IN (nor for control endpoints). EPSIZE 6:4 Endpoint Size0 8 bytes1 16 bytes2 32 bytes3 64 bytes4 128 bytes5 256 bytes6 512 bytes7 1024 bytes EPBK 3:2 Endpoint Banks0 Single-bank endpoint1 Double-bank endpoint2 Triple-bank endpoint ALLOC 1 Endpoint Memory Allocate
USBHS_DEVEPTCFG9Device Endpoint Configuration Register
Address 0x40038124
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does NBTRANS 14:13 Number of transactions per microframe for isochronous endpoint0 Reserved to endpoint that does not have the high-bandwidth isochronous capability.1 Default value: one transaction per microframe.2 Two transactions per microframe. This endpoint should be configured as double-bank.3 Three transactions per microframe. This endpoint should be configured as triple-bank. EPTYPE 12:11 Endpoint Type0 Control1 Isochronous2 Bulk3 Interrupt AUTOSW 9 Automatic Switch EPDIR 8 Endpoint Direction0 The endpoint direction is OUT.1 The endpoint direction is IN (nor for control endpoints). EPSIZE 6:4 Endpoint Size0 8 bytes1 16 bytes2 32 bytes3 64 bytes4 128 bytes5 256 bytes6 512 bytes7 1024 bytes EPBK 3:2 Endpoint Banks0 Single-bank endpoint1 Double-bank endpoint2 Triple-bank endpoint ALLOC 1 Endpoint Memory Allocate
USBHS_DEVEPTISR0Device Endpoint Interrupt Status Register
Address 0x40038130
Reset 0x00000000
Access read only
Size 32-bit 20 fields
Field Bits What it does BYCT 30:20 Byte Count CFGOK 18 Configuration OK Status CTRLDIR 17 Control Direction RWALL 16 Read/Write Allowed CURRBK 15:14 Current Bank0 Current bank is bank01 Current bank is bank12 Current bank is bank2 NBUSYBK 13:12 Number of Busy Banks0 0 busy bank (all banks free)1 1 busy bank2 2 busy banks3 3 busy banks ERRORTRANS 10 High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt DTSEQ 9:8 Data Toggle Sequence0 Data0 toggle sequence1 Data1 toggle sequence2 Reserved for high-bandwidth isochronous endpoint3 Reserved for high-bandwidth isochronous endpoint SHORTPACKET 7 Short Packet Interrupt CRCERRI 6 CRC Error Interrupt STALLEDI 6 STALLed Interrupt OVERFI 5 Overflow Interrupt HBISOFLUSHI 4 High Bandwidth Isochronous IN Flush Interrupt NAKINI 4 NAKed IN Interrupt HBISOINERRI 3 High Bandwidth Isochronous IN Underflow Error Interrupt NAKOUTI 3 NAKed OUT Interrupt RXSTPI 2 Received SETUP Interrupt UNDERFI 2 Underflow Interrupt RXOUTI 1 Received OUT Data Interrupt TXINI 0 Transmitted IN Data Interrupt
USBHS_DEVEPTISR1Device Endpoint Interrupt Status Register
Address 0x40038134
Reset 0x00000000
Access read only
Size 32-bit 20 fields
Field Bits What it does BYCT 30:20 Byte Count CFGOK 18 Configuration OK Status CTRLDIR 17 Control Direction RWALL 16 Read/Write Allowed CURRBK 15:14 Current Bank0 Current bank is bank01 Current bank is bank12 Current bank is bank2 NBUSYBK 13:12 Number of Busy Banks0 0 busy bank (all banks free)1 1 busy bank2 2 busy banks3 3 busy banks ERRORTRANS 10 High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt DTSEQ 9:8 Data Toggle Sequence0 Data0 toggle sequence1 Data1 toggle sequence2 Reserved for high-bandwidth isochronous endpoint3 Reserved for high-bandwidth isochronous endpoint SHORTPACKET 7 Short Packet Interrupt CRCERRI 6 CRC Error Interrupt STALLEDI 6 STALLed Interrupt OVERFI 5 Overflow Interrupt HBISOFLUSHI 4 High Bandwidth Isochronous IN Flush Interrupt NAKINI 4 NAKed IN Interrupt HBISOINERRI 3 High Bandwidth Isochronous IN Underflow Error Interrupt NAKOUTI 3 NAKed OUT Interrupt RXSTPI 2 Received SETUP Interrupt UNDERFI 2 Underflow Interrupt RXOUTI 1 Received OUT Data Interrupt TXINI 0 Transmitted IN Data Interrupt
USBHS_DEVEPTISR2Device Endpoint Interrupt Status Register
Address 0x40038138
Reset 0x00000000
Access read only
Size 32-bit 20 fields
Field Bits What it does BYCT 30:20 Byte Count CFGOK 18 Configuration OK Status CTRLDIR 17 Control Direction RWALL 16 Read/Write Allowed CURRBK 15:14 Current Bank0 Current bank is bank01 Current bank is bank12 Current bank is bank2 NBUSYBK 13:12 Number of Busy Banks0 0 busy bank (all banks free)1 1 busy bank2 2 busy banks3 3 busy banks ERRORTRANS 10 High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt DTSEQ 9:8 Data Toggle Sequence0 Data0 toggle sequence1 Data1 toggle sequence2 Reserved for high-bandwidth isochronous endpoint3 Reserved for high-bandwidth isochronous endpoint SHORTPACKET 7 Short Packet Interrupt CRCERRI 6 CRC Error Interrupt STALLEDI 6 STALLed Interrupt OVERFI 5 Overflow Interrupt HBISOFLUSHI 4 High Bandwidth Isochronous IN Flush Interrupt NAKINI 4 NAKed IN Interrupt HBISOINERRI 3 High Bandwidth Isochronous IN Underflow Error Interrupt NAKOUTI 3 NAKed OUT Interrupt RXSTPI 2 Received SETUP Interrupt UNDERFI 2 Underflow Interrupt RXOUTI 1 Received OUT Data Interrupt TXINI 0 Transmitted IN Data Interrupt
USBHS_DEVEPTISR3Device Endpoint Interrupt Status Register
Address 0x4003813C
Reset 0x00000000
Access read only
Size 32-bit 20 fields
Field Bits What it does BYCT 30:20 Byte Count CFGOK 18 Configuration OK Status CTRLDIR 17 Control Direction RWALL 16 Read/Write Allowed CURRBK 15:14 Current Bank0 Current bank is bank01 Current bank is bank12 Current bank is bank2 NBUSYBK 13:12 Number of Busy Banks0 0 busy bank (all banks free)1 1 busy bank2 2 busy banks3 3 busy banks ERRORTRANS 10 High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt DTSEQ 9:8 Data Toggle Sequence0 Data0 toggle sequence1 Data1 toggle sequence2 Reserved for high-bandwidth isochronous endpoint3 Reserved for high-bandwidth isochronous endpoint SHORTPACKET 7 Short Packet Interrupt CRCERRI 6 CRC Error Interrupt STALLEDI 6 STALLed Interrupt OVERFI 5 Overflow Interrupt HBISOFLUSHI 4 High Bandwidth Isochronous IN Flush Interrupt NAKINI 4 NAKed IN Interrupt HBISOINERRI 3 High Bandwidth Isochronous IN Underflow Error Interrupt NAKOUTI 3 NAKed OUT Interrupt RXSTPI 2 Received SETUP Interrupt UNDERFI 2 Underflow Interrupt RXOUTI 1 Received OUT Data Interrupt TXINI 0 Transmitted IN Data Interrupt
USBHS_DEVEPTISR4Device Endpoint Interrupt Status Register
Address 0x40038140
Reset 0x00000000
Access read only
Size 32-bit 20 fields
Field Bits What it does BYCT 30:20 Byte Count CFGOK 18 Configuration OK Status CTRLDIR 17 Control Direction RWALL 16 Read/Write Allowed CURRBK 15:14 Current Bank0 Current bank is bank01 Current bank is bank12 Current bank is bank2 NBUSYBK 13:12 Number of Busy Banks0 0 busy bank (all banks free)1 1 busy bank2 2 busy banks3 3 busy banks ERRORTRANS 10 High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt DTSEQ 9:8 Data Toggle Sequence0 Data0 toggle sequence1 Data1 toggle sequence2 Reserved for high-bandwidth isochronous endpoint3 Reserved for high-bandwidth isochronous endpoint SHORTPACKET 7 Short Packet Interrupt CRCERRI 6 CRC Error Interrupt STALLEDI 6 STALLed Interrupt OVERFI 5 Overflow Interrupt HBISOFLUSHI 4 High Bandwidth Isochronous IN Flush Interrupt NAKINI 4 NAKed IN Interrupt HBISOINERRI 3 High Bandwidth Isochronous IN Underflow Error Interrupt NAKOUTI 3 NAKed OUT Interrupt RXSTPI 2 Received SETUP Interrupt UNDERFI 2 Underflow Interrupt RXOUTI 1 Received OUT Data Interrupt TXINI 0 Transmitted IN Data Interrupt
USBHS_DEVEPTISR5Device Endpoint Interrupt Status Register
Address 0x40038144
Reset 0x00000000
Access read only
Size 32-bit 20 fields
Field Bits What it does BYCT 30:20 Byte Count CFGOK 18 Configuration OK Status CTRLDIR 17 Control Direction RWALL 16 Read/Write Allowed CURRBK 15:14 Current Bank0 Current bank is bank01 Current bank is bank12 Current bank is bank2 NBUSYBK 13:12 Number of Busy Banks0 0 busy bank (all banks free)1 1 busy bank2 2 busy banks3 3 busy banks ERRORTRANS 10 High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt DTSEQ 9:8 Data Toggle Sequence0 Data0 toggle sequence1 Data1 toggle sequence2 Reserved for high-bandwidth isochronous endpoint3 Reserved for high-bandwidth isochronous endpoint SHORTPACKET 7 Short Packet Interrupt CRCERRI 6 CRC Error Interrupt STALLEDI 6 STALLed Interrupt OVERFI 5 Overflow Interrupt HBISOFLUSHI 4 High Bandwidth Isochronous IN Flush Interrupt NAKINI 4 NAKed IN Interrupt HBISOINERRI 3 High Bandwidth Isochronous IN Underflow Error Interrupt NAKOUTI 3 NAKed OUT Interrupt RXSTPI 2 Received SETUP Interrupt UNDERFI 2 Underflow Interrupt RXOUTI 1 Received OUT Data Interrupt TXINI 0 Transmitted IN Data Interrupt
USBHS_DEVEPTISR6Device Endpoint Interrupt Status Register
Address 0x40038148
Reset 0x00000000
Access read only
Size 32-bit 20 fields
Field Bits What it does BYCT 30:20 Byte Count CFGOK 18 Configuration OK Status CTRLDIR 17 Control Direction RWALL 16 Read/Write Allowed CURRBK 15:14 Current Bank0 Current bank is bank01 Current bank is bank12 Current bank is bank2 NBUSYBK 13:12 Number of Busy Banks0 0 busy bank (all banks free)1 1 busy bank2 2 busy banks3 3 busy banks ERRORTRANS 10 High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt DTSEQ 9:8 Data Toggle Sequence0 Data0 toggle sequence1 Data1 toggle sequence2 Reserved for high-bandwidth isochronous endpoint3 Reserved for high-bandwidth isochronous endpoint SHORTPACKET 7 Short Packet Interrupt CRCERRI 6 CRC Error Interrupt STALLEDI 6 STALLed Interrupt OVERFI 5 Overflow Interrupt HBISOFLUSHI 4 High Bandwidth Isochronous IN Flush Interrupt NAKINI 4 NAKed IN Interrupt HBISOINERRI 3 High Bandwidth Isochronous IN Underflow Error Interrupt NAKOUTI 3 NAKed OUT Interrupt RXSTPI 2 Received SETUP Interrupt UNDERFI 2 Underflow Interrupt RXOUTI 1 Received OUT Data Interrupt TXINI 0 Transmitted IN Data Interrupt
USBHS_DEVEPTISR7Device Endpoint Interrupt Status Register
Address 0x4003814C
Reset 0x00000000
Access read only
Size 32-bit 20 fields
Field Bits What it does BYCT 30:20 Byte Count CFGOK 18 Configuration OK Status CTRLDIR 17 Control Direction RWALL 16 Read/Write Allowed CURRBK 15:14 Current Bank0 Current bank is bank01 Current bank is bank12 Current bank is bank2 NBUSYBK 13:12 Number of Busy Banks0 0 busy bank (all banks free)1 1 busy bank2 2 busy banks3 3 busy banks ERRORTRANS 10 High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt DTSEQ 9:8 Data Toggle Sequence0 Data0 toggle sequence1 Data1 toggle sequence2 Reserved for high-bandwidth isochronous endpoint3 Reserved for high-bandwidth isochronous endpoint SHORTPACKET 7 Short Packet Interrupt CRCERRI 6 CRC Error Interrupt STALLEDI 6 STALLed Interrupt OVERFI 5 Overflow Interrupt HBISOFLUSHI 4 High Bandwidth Isochronous IN Flush Interrupt NAKINI 4 NAKed IN Interrupt HBISOINERRI 3 High Bandwidth Isochronous IN Underflow Error Interrupt NAKOUTI 3 NAKed OUT Interrupt RXSTPI 2 Received SETUP Interrupt UNDERFI 2 Underflow Interrupt RXOUTI 1 Received OUT Data Interrupt TXINI 0 Transmitted IN Data Interrupt
USBHS_DEVEPTISR8Device Endpoint Interrupt Status Register
Address 0x40038150
Reset 0x00000000
Access read only
Size 32-bit 20 fields
Field Bits What it does BYCT 30:20 Byte Count CFGOK 18 Configuration OK Status CTRLDIR 17 Control Direction RWALL 16 Read/Write Allowed CURRBK 15:14 Current Bank0 Current bank is bank01 Current bank is bank12 Current bank is bank2 NBUSYBK 13:12 Number of Busy Banks0 0 busy bank (all banks free)1 1 busy bank2 2 busy banks3 3 busy banks ERRORTRANS 10 High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt DTSEQ 9:8 Data Toggle Sequence0 Data0 toggle sequence1 Data1 toggle sequence2 Reserved for high-bandwidth isochronous endpoint3 Reserved for high-bandwidth isochronous endpoint SHORTPACKET 7 Short Packet Interrupt CRCERRI 6 CRC Error Interrupt STALLEDI 6 STALLed Interrupt OVERFI 5 Overflow Interrupt HBISOFLUSHI 4 High Bandwidth Isochronous IN Flush Interrupt NAKINI 4 NAKed IN Interrupt HBISOINERRI 3 High Bandwidth Isochronous IN Underflow Error Interrupt NAKOUTI 3 NAKed OUT Interrupt RXSTPI 2 Received SETUP Interrupt UNDERFI 2 Underflow Interrupt RXOUTI 1 Received OUT Data Interrupt TXINI 0 Transmitted IN Data Interrupt
USBHS_DEVEPTISR9Device Endpoint Interrupt Status Register
Address 0x40038154
Reset 0x00000000
Access read only
Size 32-bit 20 fields
Field Bits What it does BYCT 30:20 Byte Count CFGOK 18 Configuration OK Status CTRLDIR 17 Control Direction RWALL 16 Read/Write Allowed CURRBK 15:14 Current Bank0 Current bank is bank01 Current bank is bank12 Current bank is bank2 NBUSYBK 13:12 Number of Busy Banks0 0 busy bank (all banks free)1 1 busy bank2 2 busy banks3 3 busy banks ERRORTRANS 10 High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt DTSEQ 9:8 Data Toggle Sequence0 Data0 toggle sequence1 Data1 toggle sequence2 Reserved for high-bandwidth isochronous endpoint3 Reserved for high-bandwidth isochronous endpoint SHORTPACKET 7 Short Packet Interrupt CRCERRI 6 CRC Error Interrupt STALLEDI 6 STALLed Interrupt OVERFI 5 Overflow Interrupt HBISOFLUSHI 4 High Bandwidth Isochronous IN Flush Interrupt NAKINI 4 NAKed IN Interrupt HBISOINERRI 3 High Bandwidth Isochronous IN Underflow Error Interrupt NAKOUTI 3 NAKed OUT Interrupt RXSTPI 2 Received SETUP Interrupt UNDERFI 2 Underflow Interrupt RXOUTI 1 Received OUT Data Interrupt TXINI 0 Transmitted IN Data Interrupt
USBHS_DEVEPTICR0Device Endpoint Interrupt Clear Register
Address 0x40038160
Reset 0x00000000
Access write only
Size 32-bit 12 fields
Field Bits What it does SHORTPACKETC 7 Short Packet Interrupt Clear CRCERRIC 6 CRC Error Interrupt Clear STALLEDIC 6 STALLed Interrupt Clear OVERFIC 5 Overflow Interrupt Clear HBISOFLUSHIC 4 High Bandwidth Isochronous IN Flush Interrupt Clear NAKINIC 4 NAKed IN Interrupt Clear HBISOINERRIC 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear NAKOUTIC 3 NAKed OUT Interrupt Clear RXSTPIC 2 Received SETUP Interrupt Clear UNDERFIC 2 Underflow Interrupt Clear RXOUTIC 1 Received OUT Data Interrupt Clear TXINIC 0 Transmitted IN Data Interrupt Clear
USBHS_DEVEPTICR1Device Endpoint Interrupt Clear Register
Address 0x40038164
Reset 0x00000000
Access write only
Size 32-bit 12 fields
Field Bits What it does SHORTPACKETC 7 Short Packet Interrupt Clear CRCERRIC 6 CRC Error Interrupt Clear STALLEDIC 6 STALLed Interrupt Clear OVERFIC 5 Overflow Interrupt Clear HBISOFLUSHIC 4 High Bandwidth Isochronous IN Flush Interrupt Clear NAKINIC 4 NAKed IN Interrupt Clear HBISOINERRIC 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear NAKOUTIC 3 NAKed OUT Interrupt Clear RXSTPIC 2 Received SETUP Interrupt Clear UNDERFIC 2 Underflow Interrupt Clear RXOUTIC 1 Received OUT Data Interrupt Clear TXINIC 0 Transmitted IN Data Interrupt Clear
USBHS_DEVEPTICR2Device Endpoint Interrupt Clear Register
Address 0x40038168
Reset 0x00000000
Access write only
Size 32-bit 12 fields
Field Bits What it does SHORTPACKETC 7 Short Packet Interrupt Clear CRCERRIC 6 CRC Error Interrupt Clear STALLEDIC 6 STALLed Interrupt Clear OVERFIC 5 Overflow Interrupt Clear HBISOFLUSHIC 4 High Bandwidth Isochronous IN Flush Interrupt Clear NAKINIC 4 NAKed IN Interrupt Clear HBISOINERRIC 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear NAKOUTIC 3 NAKed OUT Interrupt Clear RXSTPIC 2 Received SETUP Interrupt Clear UNDERFIC 2 Underflow Interrupt Clear RXOUTIC 1 Received OUT Data Interrupt Clear TXINIC 0 Transmitted IN Data Interrupt Clear
USBHS_DEVEPTICR3Device Endpoint Interrupt Clear Register
Address 0x4003816C
Reset 0x00000000
Access write only
Size 32-bit 12 fields
Field Bits What it does SHORTPACKETC 7 Short Packet Interrupt Clear CRCERRIC 6 CRC Error Interrupt Clear STALLEDIC 6 STALLed Interrupt Clear OVERFIC 5 Overflow Interrupt Clear HBISOFLUSHIC 4 High Bandwidth Isochronous IN Flush Interrupt Clear NAKINIC 4 NAKed IN Interrupt Clear HBISOINERRIC 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear NAKOUTIC 3 NAKed OUT Interrupt Clear RXSTPIC 2 Received SETUP Interrupt Clear UNDERFIC 2 Underflow Interrupt Clear RXOUTIC 1 Received OUT Data Interrupt Clear TXINIC 0 Transmitted IN Data Interrupt Clear
USBHS_DEVEPTICR4Device Endpoint Interrupt Clear Register
Address 0x40038170
Reset 0x00000000
Access write only
Size 32-bit 12 fields
Field Bits What it does SHORTPACKETC 7 Short Packet Interrupt Clear CRCERRIC 6 CRC Error Interrupt Clear STALLEDIC 6 STALLed Interrupt Clear OVERFIC 5 Overflow Interrupt Clear HBISOFLUSHIC 4 High Bandwidth Isochronous IN Flush Interrupt Clear NAKINIC 4 NAKed IN Interrupt Clear HBISOINERRIC 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear NAKOUTIC 3 NAKed OUT Interrupt Clear RXSTPIC 2 Received SETUP Interrupt Clear UNDERFIC 2 Underflow Interrupt Clear RXOUTIC 1 Received OUT Data Interrupt Clear TXINIC 0 Transmitted IN Data Interrupt Clear
USBHS_DEVEPTICR5Device Endpoint Interrupt Clear Register
Address 0x40038174
Reset 0x00000000
Access write only
Size 32-bit 12 fields
Field Bits What it does SHORTPACKETC 7 Short Packet Interrupt Clear CRCERRIC 6 CRC Error Interrupt Clear STALLEDIC 6 STALLed Interrupt Clear OVERFIC 5 Overflow Interrupt Clear HBISOFLUSHIC 4 High Bandwidth Isochronous IN Flush Interrupt Clear NAKINIC 4 NAKed IN Interrupt Clear HBISOINERRIC 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear NAKOUTIC 3 NAKed OUT Interrupt Clear RXSTPIC 2 Received SETUP Interrupt Clear UNDERFIC 2 Underflow Interrupt Clear RXOUTIC 1 Received OUT Data Interrupt Clear TXINIC 0 Transmitted IN Data Interrupt Clear
USBHS_DEVEPTICR6Device Endpoint Interrupt Clear Register
Address 0x40038178
Reset 0x00000000
Access write only
Size 32-bit 12 fields
Field Bits What it does SHORTPACKETC 7 Short Packet Interrupt Clear CRCERRIC 6 CRC Error Interrupt Clear STALLEDIC 6 STALLed Interrupt Clear OVERFIC 5 Overflow Interrupt Clear HBISOFLUSHIC 4 High Bandwidth Isochronous IN Flush Interrupt Clear NAKINIC 4 NAKed IN Interrupt Clear HBISOINERRIC 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear NAKOUTIC 3 NAKed OUT Interrupt Clear RXSTPIC 2 Received SETUP Interrupt Clear UNDERFIC 2 Underflow Interrupt Clear RXOUTIC 1 Received OUT Data Interrupt Clear TXINIC 0 Transmitted IN Data Interrupt Clear
USBHS_DEVEPTICR7Device Endpoint Interrupt Clear Register
Address 0x4003817C
Reset 0x00000000
Access write only
Size 32-bit 12 fields
Field Bits What it does SHORTPACKETC 7 Short Packet Interrupt Clear CRCERRIC 6 CRC Error Interrupt Clear STALLEDIC 6 STALLed Interrupt Clear OVERFIC 5 Overflow Interrupt Clear HBISOFLUSHIC 4 High Bandwidth Isochronous IN Flush Interrupt Clear NAKINIC 4 NAKed IN Interrupt Clear HBISOINERRIC 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear NAKOUTIC 3 NAKed OUT Interrupt Clear RXSTPIC 2 Received SETUP Interrupt Clear UNDERFIC 2 Underflow Interrupt Clear RXOUTIC 1 Received OUT Data Interrupt Clear TXINIC 0 Transmitted IN Data Interrupt Clear
USBHS_DEVEPTICR8Device Endpoint Interrupt Clear Register
Address 0x40038180
Reset 0x00000000
Access write only
Size 32-bit 12 fields
Field Bits What it does SHORTPACKETC 7 Short Packet Interrupt Clear CRCERRIC 6 CRC Error Interrupt Clear STALLEDIC 6 STALLed Interrupt Clear OVERFIC 5 Overflow Interrupt Clear HBISOFLUSHIC 4 High Bandwidth Isochronous IN Flush Interrupt Clear NAKINIC 4 NAKed IN Interrupt Clear HBISOINERRIC 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear NAKOUTIC 3 NAKed OUT Interrupt Clear RXSTPIC 2 Received SETUP Interrupt Clear UNDERFIC 2 Underflow Interrupt Clear RXOUTIC 1 Received OUT Data Interrupt Clear TXINIC 0 Transmitted IN Data Interrupt Clear
USBHS_DEVEPTICR9Device Endpoint Interrupt Clear Register
Address 0x40038184
Reset 0x00000000
Access write only
Size 32-bit 12 fields
Field Bits What it does SHORTPACKETC 7 Short Packet Interrupt Clear CRCERRIC 6 CRC Error Interrupt Clear STALLEDIC 6 STALLed Interrupt Clear OVERFIC 5 Overflow Interrupt Clear HBISOFLUSHIC 4 High Bandwidth Isochronous IN Flush Interrupt Clear NAKINIC 4 NAKed IN Interrupt Clear HBISOINERRIC 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear NAKOUTIC 3 NAKed OUT Interrupt Clear RXSTPIC 2 Received SETUP Interrupt Clear UNDERFIC 2 Underflow Interrupt Clear RXOUTIC 1 Received OUT Data Interrupt Clear TXINIC 0 Transmitted IN Data Interrupt Clear
USBHS_DEVEPTIFR0Device Endpoint Interrupt Set Register
Address 0x40038190
Reset 0x00000000
Access write only
Size 32-bit 13 fields
Field Bits What it does NBUSYBKS 12 Number of Busy Banks Interrupt Set SHORTPACKETS 7 Short Packet Interrupt Set CRCERRIS 6 CRC Error Interrupt Set STALLEDIS 6 STALLed Interrupt Set OVERFIS 5 Overflow Interrupt Set HBISOFLUSHIS 4 High Bandwidth Isochronous IN Flush Interrupt Set NAKINIS 4 NAKed IN Interrupt Set HBISOINERRIS 3 High Bandwidth Isochronous IN Underflow Error Interrupt Set NAKOUTIS 3 NAKed OUT Interrupt Set RXSTPIS 2 Received SETUP Interrupt Set UNDERFIS 2 Underflow Interrupt Set RXOUTIS 1 Received OUT Data Interrupt Set TXINIS 0 Transmitted IN Data Interrupt Set
USBHS_DEVEPTIFR1Device Endpoint Interrupt Set Register
Address 0x40038194
Reset 0x00000000
Access write only
Size 32-bit 13 fields
Field Bits What it does NBUSYBKS 12 Number of Busy Banks Interrupt Set SHORTPACKETS 7 Short Packet Interrupt Set CRCERRIS 6 CRC Error Interrupt Set STALLEDIS 6 STALLed Interrupt Set OVERFIS 5 Overflow Interrupt Set HBISOFLUSHIS 4 High Bandwidth Isochronous IN Flush Interrupt Set NAKINIS 4 NAKed IN Interrupt Set HBISOINERRIS 3 High Bandwidth Isochronous IN Underflow Error Interrupt Set NAKOUTIS 3 NAKed OUT Interrupt Set RXSTPIS 2 Received SETUP Interrupt Set UNDERFIS 2 Underflow Interrupt Set RXOUTIS 1 Received OUT Data Interrupt Set TXINIS 0 Transmitted IN Data Interrupt Set
USBHS_DEVEPTIFR2Device Endpoint Interrupt Set Register
Address 0x40038198
Reset 0x00000000
Access write only
Size 32-bit 13 fields
Field Bits What it does NBUSYBKS 12 Number of Busy Banks Interrupt Set SHORTPACKETS 7 Short Packet Interrupt Set CRCERRIS 6 CRC Error Interrupt Set STALLEDIS 6 STALLed Interrupt Set OVERFIS 5 Overflow Interrupt Set HBISOFLUSHIS 4 High Bandwidth Isochronous IN Flush Interrupt Set NAKINIS 4 NAKed IN Interrupt Set HBISOINERRIS 3 High Bandwidth Isochronous IN Underflow Error Interrupt Set NAKOUTIS 3 NAKed OUT Interrupt Set RXSTPIS 2 Received SETUP Interrupt Set UNDERFIS 2 Underflow Interrupt Set RXOUTIS 1 Received OUT Data Interrupt Set TXINIS 0 Transmitted IN Data Interrupt Set
USBHS_DEVEPTIFR3Device Endpoint Interrupt Set Register
Address 0x4003819C
Reset 0x00000000
Access write only
Size 32-bit 13 fields
Field Bits What it does NBUSYBKS 12 Number of Busy Banks Interrupt Set SHORTPACKETS 7 Short Packet Interrupt Set CRCERRIS 6 CRC Error Interrupt Set STALLEDIS 6 STALLed Interrupt Set OVERFIS 5 Overflow Interrupt Set HBISOFLUSHIS 4 High Bandwidth Isochronous IN Flush Interrupt Set NAKINIS 4 NAKed IN Interrupt Set HBISOINERRIS 3 High Bandwidth Isochronous IN Underflow Error Interrupt Set NAKOUTIS 3 NAKed OUT Interrupt Set RXSTPIS 2 Received SETUP Interrupt Set UNDERFIS 2 Underflow Interrupt Set RXOUTIS 1 Received OUT Data Interrupt Set TXINIS 0 Transmitted IN Data Interrupt Set
USBHS_DEVEPTIFR4Device Endpoint Interrupt Set Register
Address 0x400381A0
Reset 0x00000000
Access write only
Size 32-bit 13 fields
Field Bits What it does NBUSYBKS 12 Number of Busy Banks Interrupt Set SHORTPACKETS 7 Short Packet Interrupt Set CRCERRIS 6 CRC Error Interrupt Set STALLEDIS 6 STALLed Interrupt Set OVERFIS 5 Overflow Interrupt Set HBISOFLUSHIS 4 High Bandwidth Isochronous IN Flush Interrupt Set NAKINIS 4 NAKed IN Interrupt Set HBISOINERRIS 3 High Bandwidth Isochronous IN Underflow Error Interrupt Set NAKOUTIS 3 NAKed OUT Interrupt Set RXSTPIS 2 Received SETUP Interrupt Set UNDERFIS 2 Underflow Interrupt Set RXOUTIS 1 Received OUT Data Interrupt Set TXINIS 0 Transmitted IN Data Interrupt Set
USBHS_DEVEPTIFR5Device Endpoint Interrupt Set Register
Address 0x400381A4
Reset 0x00000000
Access write only
Size 32-bit 13 fields
Field Bits What it does NBUSYBKS 12 Number of Busy Banks Interrupt Set SHORTPACKETS 7 Short Packet Interrupt Set CRCERRIS 6 CRC Error Interrupt Set STALLEDIS 6 STALLed Interrupt Set OVERFIS 5 Overflow Interrupt Set HBISOFLUSHIS 4 High Bandwidth Isochronous IN Flush Interrupt Set NAKINIS 4 NAKed IN Interrupt Set HBISOINERRIS 3 High Bandwidth Isochronous IN Underflow Error Interrupt Set NAKOUTIS 3 NAKed OUT Interrupt Set RXSTPIS 2 Received SETUP Interrupt Set UNDERFIS 2 Underflow Interrupt Set RXOUTIS 1 Received OUT Data Interrupt Set TXINIS 0 Transmitted IN Data Interrupt Set
USBHS_DEVEPTIFR6Device Endpoint Interrupt Set Register
Address 0x400381A8
Reset 0x00000000
Access write only
Size 32-bit 13 fields
Field Bits What it does NBUSYBKS 12 Number of Busy Banks Interrupt Set SHORTPACKETS 7 Short Packet Interrupt Set CRCERRIS 6 CRC Error Interrupt Set STALLEDIS 6 STALLed Interrupt Set OVERFIS 5 Overflow Interrupt Set HBISOFLUSHIS 4 High Bandwidth Isochronous IN Flush Interrupt Set NAKINIS 4 NAKed IN Interrupt Set HBISOINERRIS 3 High Bandwidth Isochronous IN Underflow Error Interrupt Set NAKOUTIS 3 NAKed OUT Interrupt Set RXSTPIS 2 Received SETUP Interrupt Set UNDERFIS 2 Underflow Interrupt Set RXOUTIS 1 Received OUT Data Interrupt Set TXINIS 0 Transmitted IN Data Interrupt Set
USBHS_DEVEPTIFR7Device Endpoint Interrupt Set Register
Address 0x400381AC
Reset 0x00000000
Access write only
Size 32-bit 13 fields
Field Bits What it does NBUSYBKS 12 Number of Busy Banks Interrupt Set SHORTPACKETS 7 Short Packet Interrupt Set CRCERRIS 6 CRC Error Interrupt Set STALLEDIS 6 STALLed Interrupt Set OVERFIS 5 Overflow Interrupt Set HBISOFLUSHIS 4 High Bandwidth Isochronous IN Flush Interrupt Set NAKINIS 4 NAKed IN Interrupt Set HBISOINERRIS 3 High Bandwidth Isochronous IN Underflow Error Interrupt Set NAKOUTIS 3 NAKed OUT Interrupt Set RXSTPIS 2 Received SETUP Interrupt Set UNDERFIS 2 Underflow Interrupt Set RXOUTIS 1 Received OUT Data Interrupt Set TXINIS 0 Transmitted IN Data Interrupt Set
USBHS_DEVEPTIFR8Device Endpoint Interrupt Set Register
Address 0x400381B0
Reset 0x00000000
Access write only
Size 32-bit 13 fields
Field Bits What it does NBUSYBKS 12 Number of Busy Banks Interrupt Set SHORTPACKETS 7 Short Packet Interrupt Set CRCERRIS 6 CRC Error Interrupt Set STALLEDIS 6 STALLed Interrupt Set OVERFIS 5 Overflow Interrupt Set HBISOFLUSHIS 4 High Bandwidth Isochronous IN Flush Interrupt Set NAKINIS 4 NAKed IN Interrupt Set HBISOINERRIS 3 High Bandwidth Isochronous IN Underflow Error Interrupt Set NAKOUTIS 3 NAKed OUT Interrupt Set RXSTPIS 2 Received SETUP Interrupt Set UNDERFIS 2 Underflow Interrupt Set RXOUTIS 1 Received OUT Data Interrupt Set TXINIS 0 Transmitted IN Data Interrupt Set
USBHS_DEVEPTIFR9Device Endpoint Interrupt Set Register
Address 0x400381B4
Reset 0x00000000
Access write only
Size 32-bit 13 fields
Field Bits What it does NBUSYBKS 12 Number of Busy Banks Interrupt Set SHORTPACKETS 7 Short Packet Interrupt Set CRCERRIS 6 CRC Error Interrupt Set STALLEDIS 6 STALLed Interrupt Set OVERFIS 5 Overflow Interrupt Set HBISOFLUSHIS 4 High Bandwidth Isochronous IN Flush Interrupt Set NAKINIS 4 NAKed IN Interrupt Set HBISOINERRIS 3 High Bandwidth Isochronous IN Underflow Error Interrupt Set NAKOUTIS 3 NAKed OUT Interrupt Set RXSTPIS 2 Received SETUP Interrupt Set UNDERFIS 2 Underflow Interrupt Set RXOUTIS 1 Received OUT Data Interrupt Set TXINIS 0 Transmitted IN Data Interrupt Set
USBHS_DEVEPTIMR0Device Endpoint Interrupt Mask Register
Address 0x400381C0
Reset 0x00000000
Access read only
Size 32-bit 22 fields
Field Bits What it does STALLRQ 19 STALL Request RSTDT 18 Reset Data Toggle NYETDIS 17 NYET Token Disable EPDISHDMA 16 Endpoint Interrupts Disable HDMA Request FIFOCON 14 FIFO Control KILLBK 13 Kill IN Bank NBUSYBKE 12 Number of Busy Banks Interrupt ERRORTRANSE 10 Transaction Error Interrupt DATAXE 9 DataX Interrupt MDATAE 8 MData Interrupt SHORTPACKETE 7 Short Packet Interrupt CRCERRE 6 CRC Error Interrupt STALLEDE 6 STALLed Interrupt OVERFE 5 Overflow Interrupt HBISOFLUSHE 4 High Bandwidth Isochronous IN Flush Interrupt NAKINE 4 NAKed IN Interrupt HBISOINERRE 3 High Bandwidth Isochronous IN Underflow Error Interrupt NAKOUTE 3 NAKed OUT Interrupt RXSTPE 2 Received SETUP Interrupt UNDERFE 2 Underflow Interrupt RXOUTE 1 Received OUT Data Interrupt TXINE 0 Transmitted IN Data Interrupt
USBHS_DEVEPTIMR1Device Endpoint Interrupt Mask Register
Address 0x400381C4
Reset 0x00000000
Access read only
Size 32-bit 22 fields
Field Bits What it does STALLRQ 19 STALL Request RSTDT 18 Reset Data Toggle NYETDIS 17 NYET Token Disable EPDISHDMA 16 Endpoint Interrupts Disable HDMA Request FIFOCON 14 FIFO Control KILLBK 13 Kill IN Bank NBUSYBKE 12 Number of Busy Banks Interrupt ERRORTRANSE 10 Transaction Error Interrupt DATAXE 9 DataX Interrupt MDATAE 8 MData Interrupt SHORTPACKETE 7 Short Packet Interrupt CRCERRE 6 CRC Error Interrupt STALLEDE 6 STALLed Interrupt OVERFE 5 Overflow Interrupt HBISOFLUSHE 4 High Bandwidth Isochronous IN Flush Interrupt NAKINE 4 NAKed IN Interrupt HBISOINERRE 3 High Bandwidth Isochronous IN Underflow Error Interrupt NAKOUTE 3 NAKed OUT Interrupt RXSTPE 2 Received SETUP Interrupt UNDERFE 2 Underflow Interrupt RXOUTE 1 Received OUT Data Interrupt TXINE 0 Transmitted IN Data Interrupt
USBHS_DEVEPTIMR2Device Endpoint Interrupt Mask Register
Address 0x400381C8
Reset 0x00000000
Access read only
Size 32-bit 22 fields
Field Bits What it does STALLRQ 19 STALL Request RSTDT 18 Reset Data Toggle NYETDIS 17 NYET Token Disable EPDISHDMA 16 Endpoint Interrupts Disable HDMA Request FIFOCON 14 FIFO Control KILLBK 13 Kill IN Bank NBUSYBKE 12 Number of Busy Banks Interrupt ERRORTRANSE 10 Transaction Error Interrupt DATAXE 9 DataX Interrupt MDATAE 8 MData Interrupt SHORTPACKETE 7 Short Packet Interrupt CRCERRE 6 CRC Error Interrupt STALLEDE 6 STALLed Interrupt OVERFE 5 Overflow Interrupt HBISOFLUSHE 4 High Bandwidth Isochronous IN Flush Interrupt NAKINE 4 NAKed IN Interrupt HBISOINERRE 3 High Bandwidth Isochronous IN Underflow Error Interrupt NAKOUTE 3 NAKed OUT Interrupt RXSTPE 2 Received SETUP Interrupt UNDERFE 2 Underflow Interrupt RXOUTE 1 Received OUT Data Interrupt TXINE 0 Transmitted IN Data Interrupt
USBHS_DEVEPTIMR3Device Endpoint Interrupt Mask Register
Address 0x400381CC
Reset 0x00000000
Access read only
Size 32-bit 22 fields
Field Bits What it does STALLRQ 19 STALL Request RSTDT 18 Reset Data Toggle NYETDIS 17 NYET Token Disable EPDISHDMA 16 Endpoint Interrupts Disable HDMA Request FIFOCON 14 FIFO Control KILLBK 13 Kill IN Bank NBUSYBKE 12 Number of Busy Banks Interrupt ERRORTRANSE 10 Transaction Error Interrupt DATAXE 9 DataX Interrupt MDATAE 8 MData Interrupt SHORTPACKETE 7 Short Packet Interrupt CRCERRE 6 CRC Error Interrupt STALLEDE 6 STALLed Interrupt OVERFE 5 Overflow Interrupt HBISOFLUSHE 4 High Bandwidth Isochronous IN Flush Interrupt NAKINE 4 NAKed IN Interrupt HBISOINERRE 3 High Bandwidth Isochronous IN Underflow Error Interrupt NAKOUTE 3 NAKed OUT Interrupt RXSTPE 2 Received SETUP Interrupt UNDERFE 2 Underflow Interrupt RXOUTE 1 Received OUT Data Interrupt TXINE 0 Transmitted IN Data Interrupt
USBHS_DEVEPTIMR4Device Endpoint Interrupt Mask Register
Address 0x400381D0
Reset 0x00000000
Access read only
Size 32-bit 22 fields
Field Bits What it does STALLRQ 19 STALL Request RSTDT 18 Reset Data Toggle NYETDIS 17 NYET Token Disable EPDISHDMA 16 Endpoint Interrupts Disable HDMA Request FIFOCON 14 FIFO Control KILLBK 13 Kill IN Bank NBUSYBKE 12 Number of Busy Banks Interrupt ERRORTRANSE 10 Transaction Error Interrupt DATAXE 9 DataX Interrupt MDATAE 8 MData Interrupt SHORTPACKETE 7 Short Packet Interrupt CRCERRE 6 CRC Error Interrupt STALLEDE 6 STALLed Interrupt OVERFE 5 Overflow Interrupt HBISOFLUSHE 4 High Bandwidth Isochronous IN Flush Interrupt NAKINE 4 NAKed IN Interrupt HBISOINERRE 3 High Bandwidth Isochronous IN Underflow Error Interrupt NAKOUTE 3 NAKed OUT Interrupt RXSTPE 2 Received SETUP Interrupt UNDERFE 2 Underflow Interrupt RXOUTE 1 Received OUT Data Interrupt TXINE 0 Transmitted IN Data Interrupt
USBHS_DEVEPTIMR5Device Endpoint Interrupt Mask Register
Address 0x400381D4
Reset 0x00000000
Access read only
Size 32-bit 22 fields
Field Bits What it does STALLRQ 19 STALL Request RSTDT 18 Reset Data Toggle NYETDIS 17 NYET Token Disable EPDISHDMA 16 Endpoint Interrupts Disable HDMA Request FIFOCON 14 FIFO Control KILLBK 13 Kill IN Bank NBUSYBKE 12 Number of Busy Banks Interrupt ERRORTRANSE 10 Transaction Error Interrupt DATAXE 9 DataX Interrupt MDATAE 8 MData Interrupt SHORTPACKETE 7 Short Packet Interrupt CRCERRE 6 CRC Error Interrupt STALLEDE 6 STALLed Interrupt OVERFE 5 Overflow Interrupt HBISOFLUSHE 4 High Bandwidth Isochronous IN Flush Interrupt NAKINE 4 NAKed IN Interrupt HBISOINERRE 3 High Bandwidth Isochronous IN Underflow Error Interrupt NAKOUTE 3 NAKed OUT Interrupt RXSTPE 2 Received SETUP Interrupt UNDERFE 2 Underflow Interrupt RXOUTE 1 Received OUT Data Interrupt TXINE 0 Transmitted IN Data Interrupt
USBHS_DEVEPTIMR6Device Endpoint Interrupt Mask Register
Address 0x400381D8
Reset 0x00000000
Access read only
Size 32-bit 22 fields
Field Bits What it does STALLRQ 19 STALL Request RSTDT 18 Reset Data Toggle NYETDIS 17 NYET Token Disable EPDISHDMA 16 Endpoint Interrupts Disable HDMA Request FIFOCON 14 FIFO Control KILLBK 13 Kill IN Bank NBUSYBKE 12 Number of Busy Banks Interrupt ERRORTRANSE 10 Transaction Error Interrupt DATAXE 9 DataX Interrupt MDATAE 8 MData Interrupt SHORTPACKETE 7 Short Packet Interrupt CRCERRE 6 CRC Error Interrupt STALLEDE 6 STALLed Interrupt OVERFE 5 Overflow Interrupt HBISOFLUSHE 4 High Bandwidth Isochronous IN Flush Interrupt NAKINE 4 NAKed IN Interrupt HBISOINERRE 3 High Bandwidth Isochronous IN Underflow Error Interrupt NAKOUTE 3 NAKed OUT Interrupt RXSTPE 2 Received SETUP Interrupt UNDERFE 2 Underflow Interrupt RXOUTE 1 Received OUT Data Interrupt TXINE 0 Transmitted IN Data Interrupt
USBHS_DEVEPTIMR7Device Endpoint Interrupt Mask Register
Address 0x400381DC
Reset 0x00000000
Access read only
Size 32-bit 22 fields
Field Bits What it does STALLRQ 19 STALL Request RSTDT 18 Reset Data Toggle NYETDIS 17 NYET Token Disable EPDISHDMA 16 Endpoint Interrupts Disable HDMA Request FIFOCON 14 FIFO Control KILLBK 13 Kill IN Bank NBUSYBKE 12 Number of Busy Banks Interrupt ERRORTRANSE 10 Transaction Error Interrupt DATAXE 9 DataX Interrupt MDATAE 8 MData Interrupt SHORTPACKETE 7 Short Packet Interrupt CRCERRE 6 CRC Error Interrupt STALLEDE 6 STALLed Interrupt OVERFE 5 Overflow Interrupt HBISOFLUSHE 4 High Bandwidth Isochronous IN Flush Interrupt NAKINE 4 NAKed IN Interrupt HBISOINERRE 3 High Bandwidth Isochronous IN Underflow Error Interrupt NAKOUTE 3 NAKed OUT Interrupt RXSTPE 2 Received SETUP Interrupt UNDERFE 2 Underflow Interrupt RXOUTE 1 Received OUT Data Interrupt TXINE 0 Transmitted IN Data Interrupt
USBHS_DEVEPTIMR8Device Endpoint Interrupt Mask Register
Address 0x400381E0
Reset 0x00000000
Access read only
Size 32-bit 22 fields
Field Bits What it does STALLRQ 19 STALL Request RSTDT 18 Reset Data Toggle NYETDIS 17 NYET Token Disable EPDISHDMA 16 Endpoint Interrupts Disable HDMA Request FIFOCON 14 FIFO Control KILLBK 13 Kill IN Bank NBUSYBKE 12 Number of Busy Banks Interrupt ERRORTRANSE 10 Transaction Error Interrupt DATAXE 9 DataX Interrupt MDATAE 8 MData Interrupt SHORTPACKETE 7 Short Packet Interrupt CRCERRE 6 CRC Error Interrupt STALLEDE 6 STALLed Interrupt OVERFE 5 Overflow Interrupt HBISOFLUSHE 4 High Bandwidth Isochronous IN Flush Interrupt NAKINE 4 NAKed IN Interrupt HBISOINERRE 3 High Bandwidth Isochronous IN Underflow Error Interrupt NAKOUTE 3 NAKed OUT Interrupt RXSTPE 2 Received SETUP Interrupt UNDERFE 2 Underflow Interrupt RXOUTE 1 Received OUT Data Interrupt TXINE 0 Transmitted IN Data Interrupt
USBHS_DEVEPTIMR9Device Endpoint Interrupt Mask Register
Address 0x400381E4
Reset 0x00000000
Access read only
Size 32-bit 22 fields
Field Bits What it does STALLRQ 19 STALL Request RSTDT 18 Reset Data Toggle NYETDIS 17 NYET Token Disable EPDISHDMA 16 Endpoint Interrupts Disable HDMA Request FIFOCON 14 FIFO Control KILLBK 13 Kill IN Bank NBUSYBKE 12 Number of Busy Banks Interrupt ERRORTRANSE 10 Transaction Error Interrupt DATAXE 9 DataX Interrupt MDATAE 8 MData Interrupt SHORTPACKETE 7 Short Packet Interrupt CRCERRE 6 CRC Error Interrupt STALLEDE 6 STALLed Interrupt OVERFE 5 Overflow Interrupt HBISOFLUSHE 4 High Bandwidth Isochronous IN Flush Interrupt NAKINE 4 NAKed IN Interrupt HBISOINERRE 3 High Bandwidth Isochronous IN Underflow Error Interrupt NAKOUTE 3 NAKed OUT Interrupt RXSTPE 2 Received SETUP Interrupt UNDERFE 2 Underflow Interrupt RXOUTE 1 Received OUT Data Interrupt TXINE 0 Transmitted IN Data Interrupt
USBHS_DEVEPTIER0Device Endpoint Interrupt Enable Register
Address 0x400381F0
Reset 0x00000000
Access write only
Size 32-bit 22 fields
Field Bits What it does STALLRQS 19 STALL Request Enable RSTDTS 18 Reset Data Toggle Enable NYETDISS 17 NYET Token Disable Enable EPDISHDMAS 16 Endpoint Interrupts Disable HDMA Request Enable FIFOCONS 14 FIFO Control KILLBKS 13 Kill IN Bank NBUSYBKES 12 Number of Busy Banks Interrupt Enable ERRORTRANSES 10 Transaction Error Interrupt Enable DATAXES 9 DataX Interrupt Enable MDATAES 8 MData Interrupt Enable SHORTPACKETES 7 Short Packet Interrupt Enable CRCERRES 6 CRC Error Interrupt Enable STALLEDES 6 STALLed Interrupt Enable OVERFES 5 Overflow Interrupt Enable HBISOFLUSHES 4 High Bandwidth Isochronous IN Flush Interrupt Enable NAKINES 4 NAKed IN Interrupt Enable HBISOINERRES 3 High Bandwidth Isochronous IN Underflow Error Interrupt Enable NAKOUTES 3 NAKed OUT Interrupt Enable RXSTPES 2 Received SETUP Interrupt Enable UNDERFES 2 Underflow Interrupt Enable RXOUTES 1 Received OUT Data Interrupt Enable TXINES 0 Transmitted IN Data Interrupt Enable
USBHS_DEVEPTIER1Device Endpoint Interrupt Enable Register
Address 0x400381F4
Reset 0x00000000
Access write only
Size 32-bit 22 fields
Field Bits What it does STALLRQS 19 STALL Request Enable RSTDTS 18 Reset Data Toggle Enable NYETDISS 17 NYET Token Disable Enable EPDISHDMAS 16 Endpoint Interrupts Disable HDMA Request Enable FIFOCONS 14 FIFO Control KILLBKS 13 Kill IN Bank NBUSYBKES 12 Number of Busy Banks Interrupt Enable ERRORTRANSES 10 Transaction Error Interrupt Enable DATAXES 9 DataX Interrupt Enable MDATAES 8 MData Interrupt Enable SHORTPACKETES 7 Short Packet Interrupt Enable CRCERRES 6 CRC Error Interrupt Enable STALLEDES 6 STALLed Interrupt Enable OVERFES 5 Overflow Interrupt Enable HBISOFLUSHES 4 High Bandwidth Isochronous IN Flush Interrupt Enable NAKINES 4 NAKed IN Interrupt Enable HBISOINERRES 3 High Bandwidth Isochronous IN Underflow Error Interrupt Enable NAKOUTES 3 NAKed OUT Interrupt Enable RXSTPES 2 Received SETUP Interrupt Enable UNDERFES 2 Underflow Interrupt Enable RXOUTES 1 Received OUT Data Interrupt Enable TXINES 0 Transmitted IN Data Interrupt Enable
USBHS_DEVEPTIER2Device Endpoint Interrupt Enable Register
Address 0x400381F8
Reset 0x00000000
Access write only
Size 32-bit 22 fields
Field Bits What it does STALLRQS 19 STALL Request Enable RSTDTS 18 Reset Data Toggle Enable NYETDISS 17 NYET Token Disable Enable EPDISHDMAS 16 Endpoint Interrupts Disable HDMA Request Enable FIFOCONS 14 FIFO Control KILLBKS 13 Kill IN Bank NBUSYBKES 12 Number of Busy Banks Interrupt Enable ERRORTRANSES 10 Transaction Error Interrupt Enable DATAXES 9 DataX Interrupt Enable MDATAES 8 MData Interrupt Enable SHORTPACKETES 7 Short Packet Interrupt Enable CRCERRES 6 CRC Error Interrupt Enable STALLEDES 6 STALLed Interrupt Enable OVERFES 5 Overflow Interrupt Enable HBISOFLUSHES 4 High Bandwidth Isochronous IN Flush Interrupt Enable NAKINES 4 NAKed IN Interrupt Enable HBISOINERRES 3 High Bandwidth Isochronous IN Underflow Error Interrupt Enable NAKOUTES 3 NAKed OUT Interrupt Enable RXSTPES 2 Received SETUP Interrupt Enable UNDERFES 2 Underflow Interrupt Enable RXOUTES 1 Received OUT Data Interrupt Enable TXINES 0 Transmitted IN Data Interrupt Enable
USBHS_DEVEPTIER3Device Endpoint Interrupt Enable Register
Address 0x400381FC
Reset 0x00000000
Access write only
Size 32-bit 22 fields
Field Bits What it does STALLRQS 19 STALL Request Enable RSTDTS 18 Reset Data Toggle Enable NYETDISS 17 NYET Token Disable Enable EPDISHDMAS 16 Endpoint Interrupts Disable HDMA Request Enable FIFOCONS 14 FIFO Control KILLBKS 13 Kill IN Bank NBUSYBKES 12 Number of Busy Banks Interrupt Enable ERRORTRANSES 10 Transaction Error Interrupt Enable DATAXES 9 DataX Interrupt Enable MDATAES 8 MData Interrupt Enable SHORTPACKETES 7 Short Packet Interrupt Enable CRCERRES 6 CRC Error Interrupt Enable STALLEDES 6 STALLed Interrupt Enable OVERFES 5 Overflow Interrupt Enable HBISOFLUSHES 4 High Bandwidth Isochronous IN Flush Interrupt Enable NAKINES 4 NAKed IN Interrupt Enable HBISOINERRES 3 High Bandwidth Isochronous IN Underflow Error Interrupt Enable NAKOUTES 3 NAKed OUT Interrupt Enable RXSTPES 2 Received SETUP Interrupt Enable UNDERFES 2 Underflow Interrupt Enable RXOUTES 1 Received OUT Data Interrupt Enable TXINES 0 Transmitted IN Data Interrupt Enable
USBHS_DEVEPTIER4Device Endpoint Interrupt Enable Register
Address 0x40038200
Reset 0x00000000
Access write only
Size 32-bit 22 fields
Field Bits What it does STALLRQS 19 STALL Request Enable RSTDTS 18 Reset Data Toggle Enable NYETDISS 17 NYET Token Disable Enable EPDISHDMAS 16 Endpoint Interrupts Disable HDMA Request Enable FIFOCONS 14 FIFO Control KILLBKS 13 Kill IN Bank NBUSYBKES 12 Number of Busy Banks Interrupt Enable ERRORTRANSES 10 Transaction Error Interrupt Enable DATAXES 9 DataX Interrupt Enable MDATAES 8 MData Interrupt Enable SHORTPACKETES 7 Short Packet Interrupt Enable CRCERRES 6 CRC Error Interrupt Enable STALLEDES 6 STALLed Interrupt Enable OVERFES 5 Overflow Interrupt Enable HBISOFLUSHES 4 High Bandwidth Isochronous IN Flush Interrupt Enable NAKINES 4 NAKed IN Interrupt Enable HBISOINERRES 3 High Bandwidth Isochronous IN Underflow Error Interrupt Enable NAKOUTES 3 NAKed OUT Interrupt Enable RXSTPES 2 Received SETUP Interrupt Enable UNDERFES 2 Underflow Interrupt Enable RXOUTES 1 Received OUT Data Interrupt Enable TXINES 0 Transmitted IN Data Interrupt Enable
USBHS_DEVEPTIER5Device Endpoint Interrupt Enable Register
Address 0x40038204
Reset 0x00000000
Access write only
Size 32-bit 22 fields
Field Bits What it does STALLRQS 19 STALL Request Enable RSTDTS 18 Reset Data Toggle Enable NYETDISS 17 NYET Token Disable Enable EPDISHDMAS 16 Endpoint Interrupts Disable HDMA Request Enable FIFOCONS 14 FIFO Control KILLBKS 13 Kill IN Bank NBUSYBKES 12 Number of Busy Banks Interrupt Enable ERRORTRANSES 10 Transaction Error Interrupt Enable DATAXES 9 DataX Interrupt Enable MDATAES 8 MData Interrupt Enable SHORTPACKETES 7 Short Packet Interrupt Enable CRCERRES 6 CRC Error Interrupt Enable STALLEDES 6 STALLed Interrupt Enable OVERFES 5 Overflow Interrupt Enable HBISOFLUSHES 4 High Bandwidth Isochronous IN Flush Interrupt Enable NAKINES 4 NAKed IN Interrupt Enable HBISOINERRES 3 High Bandwidth Isochronous IN Underflow Error Interrupt Enable NAKOUTES 3 NAKed OUT Interrupt Enable RXSTPES 2 Received SETUP Interrupt Enable UNDERFES 2 Underflow Interrupt Enable RXOUTES 1 Received OUT Data Interrupt Enable TXINES 0 Transmitted IN Data Interrupt Enable
USBHS_DEVEPTIER6Device Endpoint Interrupt Enable Register
Address 0x40038208
Reset 0x00000000
Access write only
Size 32-bit 22 fields
Field Bits What it does STALLRQS 19 STALL Request Enable RSTDTS 18 Reset Data Toggle Enable NYETDISS 17 NYET Token Disable Enable EPDISHDMAS 16 Endpoint Interrupts Disable HDMA Request Enable FIFOCONS 14 FIFO Control KILLBKS 13 Kill IN Bank NBUSYBKES 12 Number of Busy Banks Interrupt Enable ERRORTRANSES 10 Transaction Error Interrupt Enable DATAXES 9 DataX Interrupt Enable MDATAES 8 MData Interrupt Enable SHORTPACKETES 7 Short Packet Interrupt Enable CRCERRES 6 CRC Error Interrupt Enable STALLEDES 6 STALLed Interrupt Enable OVERFES 5 Overflow Interrupt Enable HBISOFLUSHES 4 High Bandwidth Isochronous IN Flush Interrupt Enable NAKINES 4 NAKed IN Interrupt Enable HBISOINERRES 3 High Bandwidth Isochronous IN Underflow Error Interrupt Enable NAKOUTES 3 NAKed OUT Interrupt Enable RXSTPES 2 Received SETUP Interrupt Enable UNDERFES 2 Underflow Interrupt Enable RXOUTES 1 Received OUT Data Interrupt Enable TXINES 0 Transmitted IN Data Interrupt Enable
USBHS_DEVEPTIER7Device Endpoint Interrupt Enable Register
Address 0x4003820C
Reset 0x00000000
Access write only
Size 32-bit 22 fields
Field Bits What it does STALLRQS 19 STALL Request Enable RSTDTS 18 Reset Data Toggle Enable NYETDISS 17 NYET Token Disable Enable EPDISHDMAS 16 Endpoint Interrupts Disable HDMA Request Enable FIFOCONS 14 FIFO Control KILLBKS 13 Kill IN Bank NBUSYBKES 12 Number of Busy Banks Interrupt Enable ERRORTRANSES 10 Transaction Error Interrupt Enable DATAXES 9 DataX Interrupt Enable MDATAES 8 MData Interrupt Enable SHORTPACKETES 7 Short Packet Interrupt Enable CRCERRES 6 CRC Error Interrupt Enable STALLEDES 6 STALLed Interrupt Enable OVERFES 5 Overflow Interrupt Enable HBISOFLUSHES 4 High Bandwidth Isochronous IN Flush Interrupt Enable NAKINES 4 NAKed IN Interrupt Enable HBISOINERRES 3 High Bandwidth Isochronous IN Underflow Error Interrupt Enable NAKOUTES 3 NAKed OUT Interrupt Enable RXSTPES 2 Received SETUP Interrupt Enable UNDERFES 2 Underflow Interrupt Enable RXOUTES 1 Received OUT Data Interrupt Enable TXINES 0 Transmitted IN Data Interrupt Enable
USBHS_DEVEPTIER8Device Endpoint Interrupt Enable Register
Address 0x40038210
Reset 0x00000000
Access write only
Size 32-bit 22 fields
Field Bits What it does STALLRQS 19 STALL Request Enable RSTDTS 18 Reset Data Toggle Enable NYETDISS 17 NYET Token Disable Enable EPDISHDMAS 16 Endpoint Interrupts Disable HDMA Request Enable FIFOCONS 14 FIFO Control KILLBKS 13 Kill IN Bank NBUSYBKES 12 Number of Busy Banks Interrupt Enable ERRORTRANSES 10 Transaction Error Interrupt Enable DATAXES 9 DataX Interrupt Enable MDATAES 8 MData Interrupt Enable SHORTPACKETES 7 Short Packet Interrupt Enable CRCERRES 6 CRC Error Interrupt Enable STALLEDES 6 STALLed Interrupt Enable OVERFES 5 Overflow Interrupt Enable HBISOFLUSHES 4 High Bandwidth Isochronous IN Flush Interrupt Enable NAKINES 4 NAKed IN Interrupt Enable HBISOINERRES 3 High Bandwidth Isochronous IN Underflow Error Interrupt Enable NAKOUTES 3 NAKed OUT Interrupt Enable RXSTPES 2 Received SETUP Interrupt Enable UNDERFES 2 Underflow Interrupt Enable RXOUTES 1 Received OUT Data Interrupt Enable TXINES 0 Transmitted IN Data Interrupt Enable
USBHS_DEVEPTIER9Device Endpoint Interrupt Enable Register
Address 0x40038214
Reset 0x00000000
Access write only
Size 32-bit 22 fields
Field Bits What it does STALLRQS 19 STALL Request Enable RSTDTS 18 Reset Data Toggle Enable NYETDISS 17 NYET Token Disable Enable EPDISHDMAS 16 Endpoint Interrupts Disable HDMA Request Enable FIFOCONS 14 FIFO Control KILLBKS 13 Kill IN Bank NBUSYBKES 12 Number of Busy Banks Interrupt Enable ERRORTRANSES 10 Transaction Error Interrupt Enable DATAXES 9 DataX Interrupt Enable MDATAES 8 MData Interrupt Enable SHORTPACKETES 7 Short Packet Interrupt Enable CRCERRES 6 CRC Error Interrupt Enable STALLEDES 6 STALLed Interrupt Enable OVERFES 5 Overflow Interrupt Enable HBISOFLUSHES 4 High Bandwidth Isochronous IN Flush Interrupt Enable NAKINES 4 NAKed IN Interrupt Enable HBISOINERRES 3 High Bandwidth Isochronous IN Underflow Error Interrupt Enable NAKOUTES 3 NAKed OUT Interrupt Enable RXSTPES 2 Received SETUP Interrupt Enable UNDERFES 2 Underflow Interrupt Enable RXOUTES 1 Received OUT Data Interrupt Enable TXINES 0 Transmitted IN Data Interrupt Enable
USBHS_DEVEPTIDR0Device Endpoint Interrupt Disable Register
Address 0x40038220
Reset 0x00000000
Access write only
Size 32-bit 19 fields
Field Bits What it does STALLRQC 19 STALL Request Clear NYETDISC 17 NYET Token Disable Clear EPDISHDMAC 16 Endpoint Interrupts Disable HDMA Request Clear FIFOCONC 14 FIFO Control Clear NBUSYBKEC 12 Number of Busy Banks Interrupt Clear ERRORTRANSEC 10 Transaction Error Interrupt Clear DATAXEC 9 DataX Interrupt Clear MDATAEC 8 MData Interrupt Clear SHORTPACKETEC 7 Shortpacket Interrupt Clear STALLEDEC 6 STALLed Interrupt Clear OVERFEC 5 Overflow Interrupt Clear HBISOFLUSHEC 4 High Bandwidth Isochronous IN Flush Interrupt Clear NAKINEC 4 NAKed IN Interrupt Clear HBISOINERREC 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear NAKOUTEC 3 NAKed OUT Interrupt Clear RXSTPEC 2 Received SETUP Interrupt Clear UNDERFEC 2 Underflow Interrupt Clear RXOUTEC 1 Received OUT Data Interrupt Clear TXINEC 0 Transmitted IN Interrupt Clear
USBHS_DEVEPTIDR1Device Endpoint Interrupt Disable Register
Address 0x40038224
Reset 0x00000000
Access write only
Size 32-bit 19 fields
Field Bits What it does STALLRQC 19 STALL Request Clear NYETDISC 17 NYET Token Disable Clear EPDISHDMAC 16 Endpoint Interrupts Disable HDMA Request Clear FIFOCONC 14 FIFO Control Clear NBUSYBKEC 12 Number of Busy Banks Interrupt Clear ERRORTRANSEC 10 Transaction Error Interrupt Clear DATAXEC 9 DataX Interrupt Clear MDATAEC 8 MData Interrupt Clear SHORTPACKETEC 7 Shortpacket Interrupt Clear STALLEDEC 6 STALLed Interrupt Clear OVERFEC 5 Overflow Interrupt Clear HBISOFLUSHEC 4 High Bandwidth Isochronous IN Flush Interrupt Clear NAKINEC 4 NAKed IN Interrupt Clear HBISOINERREC 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear NAKOUTEC 3 NAKed OUT Interrupt Clear RXSTPEC 2 Received SETUP Interrupt Clear UNDERFEC 2 Underflow Interrupt Clear RXOUTEC 1 Received OUT Data Interrupt Clear TXINEC 0 Transmitted IN Interrupt Clear
USBHS_DEVEPTIDR2Device Endpoint Interrupt Disable Register
Address 0x40038228
Reset 0x00000000
Access write only
Size 32-bit 19 fields
Field Bits What it does STALLRQC 19 STALL Request Clear NYETDISC 17 NYET Token Disable Clear EPDISHDMAC 16 Endpoint Interrupts Disable HDMA Request Clear FIFOCONC 14 FIFO Control Clear NBUSYBKEC 12 Number of Busy Banks Interrupt Clear ERRORTRANSEC 10 Transaction Error Interrupt Clear DATAXEC 9 DataX Interrupt Clear MDATAEC 8 MData Interrupt Clear SHORTPACKETEC 7 Shortpacket Interrupt Clear STALLEDEC 6 STALLed Interrupt Clear OVERFEC 5 Overflow Interrupt Clear HBISOFLUSHEC 4 High Bandwidth Isochronous IN Flush Interrupt Clear NAKINEC 4 NAKed IN Interrupt Clear HBISOINERREC 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear NAKOUTEC 3 NAKed OUT Interrupt Clear RXSTPEC 2 Received SETUP Interrupt Clear UNDERFEC 2 Underflow Interrupt Clear RXOUTEC 1 Received OUT Data Interrupt Clear TXINEC 0 Transmitted IN Interrupt Clear
USBHS_DEVEPTIDR3Device Endpoint Interrupt Disable Register
Address 0x4003822C
Reset 0x00000000
Access write only
Size 32-bit 19 fields
Field Bits What it does STALLRQC 19 STALL Request Clear NYETDISC 17 NYET Token Disable Clear EPDISHDMAC 16 Endpoint Interrupts Disable HDMA Request Clear FIFOCONC 14 FIFO Control Clear NBUSYBKEC 12 Number of Busy Banks Interrupt Clear ERRORTRANSEC 10 Transaction Error Interrupt Clear DATAXEC 9 DataX Interrupt Clear MDATAEC 8 MData Interrupt Clear SHORTPACKETEC 7 Shortpacket Interrupt Clear STALLEDEC 6 STALLed Interrupt Clear OVERFEC 5 Overflow Interrupt Clear HBISOFLUSHEC 4 High Bandwidth Isochronous IN Flush Interrupt Clear NAKINEC 4 NAKed IN Interrupt Clear HBISOINERREC 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear NAKOUTEC 3 NAKed OUT Interrupt Clear RXSTPEC 2 Received SETUP Interrupt Clear UNDERFEC 2 Underflow Interrupt Clear RXOUTEC 1 Received OUT Data Interrupt Clear TXINEC 0 Transmitted IN Interrupt Clear
USBHS_DEVEPTIDR4Device Endpoint Interrupt Disable Register
Address 0x40038230
Reset 0x00000000
Access write only
Size 32-bit 19 fields
Field Bits What it does STALLRQC 19 STALL Request Clear NYETDISC 17 NYET Token Disable Clear EPDISHDMAC 16 Endpoint Interrupts Disable HDMA Request Clear FIFOCONC 14 FIFO Control Clear NBUSYBKEC 12 Number of Busy Banks Interrupt Clear ERRORTRANSEC 10 Transaction Error Interrupt Clear DATAXEC 9 DataX Interrupt Clear MDATAEC 8 MData Interrupt Clear SHORTPACKETEC 7 Shortpacket Interrupt Clear STALLEDEC 6 STALLed Interrupt Clear OVERFEC 5 Overflow Interrupt Clear HBISOFLUSHEC 4 High Bandwidth Isochronous IN Flush Interrupt Clear NAKINEC 4 NAKed IN Interrupt Clear HBISOINERREC 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear NAKOUTEC 3 NAKed OUT Interrupt Clear RXSTPEC 2 Received SETUP Interrupt Clear UNDERFEC 2 Underflow Interrupt Clear RXOUTEC 1 Received OUT Data Interrupt Clear TXINEC 0 Transmitted IN Interrupt Clear
USBHS_DEVEPTIDR5Device Endpoint Interrupt Disable Register
Address 0x40038234
Reset 0x00000000
Access write only
Size 32-bit 19 fields
Field Bits What it does STALLRQC 19 STALL Request Clear NYETDISC 17 NYET Token Disable Clear EPDISHDMAC 16 Endpoint Interrupts Disable HDMA Request Clear FIFOCONC 14 FIFO Control Clear NBUSYBKEC 12 Number of Busy Banks Interrupt Clear ERRORTRANSEC 10 Transaction Error Interrupt Clear DATAXEC 9 DataX Interrupt Clear MDATAEC 8 MData Interrupt Clear SHORTPACKETEC 7 Shortpacket Interrupt Clear STALLEDEC 6 STALLed Interrupt Clear OVERFEC 5 Overflow Interrupt Clear HBISOFLUSHEC 4 High Bandwidth Isochronous IN Flush Interrupt Clear NAKINEC 4 NAKed IN Interrupt Clear HBISOINERREC 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear NAKOUTEC 3 NAKed OUT Interrupt Clear RXSTPEC 2 Received SETUP Interrupt Clear UNDERFEC 2 Underflow Interrupt Clear RXOUTEC 1 Received OUT Data Interrupt Clear TXINEC 0 Transmitted IN Interrupt Clear
USBHS_DEVEPTIDR6Device Endpoint Interrupt Disable Register
Address 0x40038238
Reset 0x00000000
Access write only
Size 32-bit 19 fields
Field Bits What it does STALLRQC 19 STALL Request Clear NYETDISC 17 NYET Token Disable Clear EPDISHDMAC 16 Endpoint Interrupts Disable HDMA Request Clear FIFOCONC 14 FIFO Control Clear NBUSYBKEC 12 Number of Busy Banks Interrupt Clear ERRORTRANSEC 10 Transaction Error Interrupt Clear DATAXEC 9 DataX Interrupt Clear MDATAEC 8 MData Interrupt Clear SHORTPACKETEC 7 Shortpacket Interrupt Clear STALLEDEC 6 STALLed Interrupt Clear OVERFEC 5 Overflow Interrupt Clear HBISOFLUSHEC 4 High Bandwidth Isochronous IN Flush Interrupt Clear NAKINEC 4 NAKed IN Interrupt Clear HBISOINERREC 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear NAKOUTEC 3 NAKed OUT Interrupt Clear RXSTPEC 2 Received SETUP Interrupt Clear UNDERFEC 2 Underflow Interrupt Clear RXOUTEC 1 Received OUT Data Interrupt Clear TXINEC 0 Transmitted IN Interrupt Clear
USBHS_DEVEPTIDR7Device Endpoint Interrupt Disable Register
Address 0x4003823C
Reset 0x00000000
Access write only
Size 32-bit 19 fields
Field Bits What it does STALLRQC 19 STALL Request Clear NYETDISC 17 NYET Token Disable Clear EPDISHDMAC 16 Endpoint Interrupts Disable HDMA Request Clear FIFOCONC 14 FIFO Control Clear NBUSYBKEC 12 Number of Busy Banks Interrupt Clear ERRORTRANSEC 10 Transaction Error Interrupt Clear DATAXEC 9 DataX Interrupt Clear MDATAEC 8 MData Interrupt Clear SHORTPACKETEC 7 Shortpacket Interrupt Clear STALLEDEC 6 STALLed Interrupt Clear OVERFEC 5 Overflow Interrupt Clear HBISOFLUSHEC 4 High Bandwidth Isochronous IN Flush Interrupt Clear NAKINEC 4 NAKed IN Interrupt Clear HBISOINERREC 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear NAKOUTEC 3 NAKed OUT Interrupt Clear RXSTPEC 2 Received SETUP Interrupt Clear UNDERFEC 2 Underflow Interrupt Clear RXOUTEC 1 Received OUT Data Interrupt Clear TXINEC 0 Transmitted IN Interrupt Clear
USBHS_DEVEPTIDR8Device Endpoint Interrupt Disable Register
Address 0x40038240
Reset 0x00000000
Access write only
Size 32-bit 19 fields
Field Bits What it does STALLRQC 19 STALL Request Clear NYETDISC 17 NYET Token Disable Clear EPDISHDMAC 16 Endpoint Interrupts Disable HDMA Request Clear FIFOCONC 14 FIFO Control Clear NBUSYBKEC 12 Number of Busy Banks Interrupt Clear ERRORTRANSEC 10 Transaction Error Interrupt Clear DATAXEC 9 DataX Interrupt Clear MDATAEC 8 MData Interrupt Clear SHORTPACKETEC 7 Shortpacket Interrupt Clear STALLEDEC 6 STALLed Interrupt Clear OVERFEC 5 Overflow Interrupt Clear HBISOFLUSHEC 4 High Bandwidth Isochronous IN Flush Interrupt Clear NAKINEC 4 NAKed IN Interrupt Clear HBISOINERREC 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear NAKOUTEC 3 NAKed OUT Interrupt Clear RXSTPEC 2 Received SETUP Interrupt Clear UNDERFEC 2 Underflow Interrupt Clear RXOUTEC 1 Received OUT Data Interrupt Clear TXINEC 0 Transmitted IN Interrupt Clear
USBHS_DEVEPTIDR9Device Endpoint Interrupt Disable Register
Address 0x40038244
Reset 0x00000000
Access write only
Size 32-bit 19 fields
Field Bits What it does STALLRQC 19 STALL Request Clear NYETDISC 17 NYET Token Disable Clear EPDISHDMAC 16 Endpoint Interrupts Disable HDMA Request Clear FIFOCONC 14 FIFO Control Clear NBUSYBKEC 12 Number of Busy Banks Interrupt Clear ERRORTRANSEC 10 Transaction Error Interrupt Clear DATAXEC 9 DataX Interrupt Clear MDATAEC 8 MData Interrupt Clear SHORTPACKETEC 7 Shortpacket Interrupt Clear STALLEDEC 6 STALLed Interrupt Clear OVERFEC 5 Overflow Interrupt Clear HBISOFLUSHEC 4 High Bandwidth Isochronous IN Flush Interrupt Clear NAKINEC 4 NAKed IN Interrupt Clear HBISOINERREC 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear NAKOUTEC 3 NAKed OUT Interrupt Clear RXSTPEC 2 Received SETUP Interrupt Clear UNDERFEC 2 Underflow Interrupt Clear RXOUTEC 1 Received OUT Data Interrupt Clear TXINEC 0 Transmitted IN Interrupt Clear
USBHS_DEVDMANXTDSC0Device DMA Channel Next Descriptor Address Register
Address 0x40038310
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT_DSC_ADD 31:0 Next Descriptor Address
USBHS_DEVDMAADDRESS0Device DMA Channel Address Register
Address 0x40038314
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BUFF_ADD 31:0 Buffer Address
USBHS_DEVDMACONTROL0Device DMA Channel Control Register
Address 0x40038318
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does BURST_LCK 7 Burst Lock Enable DESC_LD_IT 6 Descriptor Loaded Interrupt Enable END_BUFFIT 5 End of Buffer Interrupt Enable END_TR_IT 4 End of Transfer Interrupt Enable END_B_EN 3 End of Buffer Enable Control END_TR_EN 2 End of Transfer Enable Control (OUT transfers only) LDNXT_DSC 1 Load Next Channel Transfer Descriptor Enable Command CHANN_ENB 0 Channel Enable Command BUFF_LENGTH 31:16 Buffer Byte Length (Write-only)
USBHS_DEVDMASTATUS0Device DMA Channel Status Register
Address 0x4003831C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does DESC_LDST 6 Descriptor Loaded Status END_BF_ST 5 End of Channel Buffer Status END_TR_ST 4 End of Channel Transfer Status CHANN_ACT 1 Channel Active Status CHANN_ENB 0 Channel Enable Status BUFF_COUNT 31:16 Buffer Byte Count
USBHS_DEVDMANXTDSC1Device DMA Channel Next Descriptor Address Register
Address 0x40038320
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT_DSC_ADD 31:0 Next Descriptor Address
USBHS_DEVDMAADDRESS1Device DMA Channel Address Register
Address 0x40038324
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BUFF_ADD 31:0 Buffer Address
USBHS_DEVDMACONTROL1Device DMA Channel Control Register
Address 0x40038328
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does BURST_LCK 7 Burst Lock Enable DESC_LD_IT 6 Descriptor Loaded Interrupt Enable END_BUFFIT 5 End of Buffer Interrupt Enable END_TR_IT 4 End of Transfer Interrupt Enable END_B_EN 3 End of Buffer Enable Control END_TR_EN 2 End of Transfer Enable Control (OUT transfers only) LDNXT_DSC 1 Load Next Channel Transfer Descriptor Enable Command CHANN_ENB 0 Channel Enable Command BUFF_LENGTH 31:16 Buffer Byte Length (Write-only)
USBHS_DEVDMASTATUS1Device DMA Channel Status Register
Address 0x4003832C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does DESC_LDST 6 Descriptor Loaded Status END_BF_ST 5 End of Channel Buffer Status END_TR_ST 4 End of Channel Transfer Status CHANN_ACT 1 Channel Active Status CHANN_ENB 0 Channel Enable Status BUFF_COUNT 31:16 Buffer Byte Count
USBHS_DEVDMANXTDSC2Device DMA Channel Next Descriptor Address Register
Address 0x40038330
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT_DSC_ADD 31:0 Next Descriptor Address
USBHS_DEVDMAADDRESS2Device DMA Channel Address Register
Address 0x40038334
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BUFF_ADD 31:0 Buffer Address
USBHS_DEVDMACONTROL2Device DMA Channel Control Register
Address 0x40038338
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does BURST_LCK 7 Burst Lock Enable DESC_LD_IT 6 Descriptor Loaded Interrupt Enable END_BUFFIT 5 End of Buffer Interrupt Enable END_TR_IT 4 End of Transfer Interrupt Enable END_B_EN 3 End of Buffer Enable Control END_TR_EN 2 End of Transfer Enable Control (OUT transfers only) LDNXT_DSC 1 Load Next Channel Transfer Descriptor Enable Command CHANN_ENB 0 Channel Enable Command BUFF_LENGTH 31:16 Buffer Byte Length (Write-only)
USBHS_DEVDMASTATUS2Device DMA Channel Status Register
Address 0x4003833C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does DESC_LDST 6 Descriptor Loaded Status END_BF_ST 5 End of Channel Buffer Status END_TR_ST 4 End of Channel Transfer Status CHANN_ACT 1 Channel Active Status CHANN_ENB 0 Channel Enable Status BUFF_COUNT 31:16 Buffer Byte Count
USBHS_DEVDMANXTDSC3Device DMA Channel Next Descriptor Address Register
Address 0x40038340
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT_DSC_ADD 31:0 Next Descriptor Address
USBHS_DEVDMAADDRESS3Device DMA Channel Address Register
Address 0x40038344
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BUFF_ADD 31:0 Buffer Address
USBHS_DEVDMACONTROL3Device DMA Channel Control Register
Address 0x40038348
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does BURST_LCK 7 Burst Lock Enable DESC_LD_IT 6 Descriptor Loaded Interrupt Enable END_BUFFIT 5 End of Buffer Interrupt Enable END_TR_IT 4 End of Transfer Interrupt Enable END_B_EN 3 End of Buffer Enable Control END_TR_EN 2 End of Transfer Enable Control (OUT transfers only) LDNXT_DSC 1 Load Next Channel Transfer Descriptor Enable Command CHANN_ENB 0 Channel Enable Command BUFF_LENGTH 31:16 Buffer Byte Length (Write-only)
USBHS_DEVDMASTATUS3Device DMA Channel Status Register
Address 0x4003834C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does DESC_LDST 6 Descriptor Loaded Status END_BF_ST 5 End of Channel Buffer Status END_TR_ST 4 End of Channel Transfer Status CHANN_ACT 1 Channel Active Status CHANN_ENB 0 Channel Enable Status BUFF_COUNT 31:16 Buffer Byte Count
USBHS_DEVDMANXTDSC4Device DMA Channel Next Descriptor Address Register
Address 0x40038350
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT_DSC_ADD 31:0 Next Descriptor Address
USBHS_DEVDMAADDRESS4Device DMA Channel Address Register
Address 0x40038354
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BUFF_ADD 31:0 Buffer Address
USBHS_DEVDMACONTROL4Device DMA Channel Control Register
Address 0x40038358
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does BURST_LCK 7 Burst Lock Enable DESC_LD_IT 6 Descriptor Loaded Interrupt Enable END_BUFFIT 5 End of Buffer Interrupt Enable END_TR_IT 4 End of Transfer Interrupt Enable END_B_EN 3 End of Buffer Enable Control END_TR_EN 2 End of Transfer Enable Control (OUT transfers only) LDNXT_DSC 1 Load Next Channel Transfer Descriptor Enable Command CHANN_ENB 0 Channel Enable Command BUFF_LENGTH 31:16 Buffer Byte Length (Write-only)
USBHS_DEVDMASTATUS4Device DMA Channel Status Register
Address 0x4003835C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does DESC_LDST 6 Descriptor Loaded Status END_BF_ST 5 End of Channel Buffer Status END_TR_ST 4 End of Channel Transfer Status CHANN_ACT 1 Channel Active Status CHANN_ENB 0 Channel Enable Status BUFF_COUNT 31:16 Buffer Byte Count
USBHS_DEVDMANXTDSC5Device DMA Channel Next Descriptor Address Register
Address 0x40038360
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT_DSC_ADD 31:0 Next Descriptor Address
USBHS_DEVDMAADDRESS5Device DMA Channel Address Register
Address 0x40038364
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BUFF_ADD 31:0 Buffer Address
USBHS_DEVDMACONTROL5Device DMA Channel Control Register
Address 0x40038368
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does BURST_LCK 7 Burst Lock Enable DESC_LD_IT 6 Descriptor Loaded Interrupt Enable END_BUFFIT 5 End of Buffer Interrupt Enable END_TR_IT 4 End of Transfer Interrupt Enable END_B_EN 3 End of Buffer Enable Control END_TR_EN 2 End of Transfer Enable Control (OUT transfers only) LDNXT_DSC 1 Load Next Channel Transfer Descriptor Enable Command CHANN_ENB 0 Channel Enable Command BUFF_LENGTH 31:16 Buffer Byte Length (Write-only)
USBHS_DEVDMASTATUS5Device DMA Channel Status Register
Address 0x4003836C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does DESC_LDST 6 Descriptor Loaded Status END_BF_ST 5 End of Channel Buffer Status END_TR_ST 4 End of Channel Transfer Status CHANN_ACT 1 Channel Active Status CHANN_ENB 0 Channel Enable Status BUFF_COUNT 31:16 Buffer Byte Count
USBHS_DEVDMANXTDSC6Device DMA Channel Next Descriptor Address Register
Address 0x40038370
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT_DSC_ADD 31:0 Next Descriptor Address
USBHS_DEVDMAADDRESS6Device DMA Channel Address Register
Address 0x40038374
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BUFF_ADD 31:0 Buffer Address
USBHS_DEVDMACONTROL6Device DMA Channel Control Register
Address 0x40038378
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does BURST_LCK 7 Burst Lock Enable DESC_LD_IT 6 Descriptor Loaded Interrupt Enable END_BUFFIT 5 End of Buffer Interrupt Enable END_TR_IT 4 End of Transfer Interrupt Enable END_B_EN 3 End of Buffer Enable Control END_TR_EN 2 End of Transfer Enable Control (OUT transfers only) LDNXT_DSC 1 Load Next Channel Transfer Descriptor Enable Command CHANN_ENB 0 Channel Enable Command BUFF_LENGTH 31:16 Buffer Byte Length (Write-only)
USBHS_DEVDMASTATUS6Device DMA Channel Status Register
Address 0x4003837C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does DESC_LDST 6 Descriptor Loaded Status END_BF_ST 5 End of Channel Buffer Status END_TR_ST 4 End of Channel Transfer Status CHANN_ACT 1 Channel Active Status CHANN_ENB 0 Channel Enable Status BUFF_COUNT 31:16 Buffer Byte Count
USBHS_HSTCTRLHost General Control Register
Address 0x40038400
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does SPDCONF 13:12 Mode Configuration0 The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable.1 For a better consumption, if high speed is not needed.2 Forced high speed.3 The host remains in Full-speed mode whatever the peripheral speed capability. RESUME 10 Send USB Resume RESET 9 Send USB Reset SOFE 8 Start of Frame Generation Enable
USBHS_HSTISRHost Global Interrupt Status Register
Address 0x40038404
Reset 0x00000000
Access read only
Size 32-bit 24 fields
Field Bits What it does DMA_6 30 DMA Channel 5 Interrupt DMA_5 29 DMA Channel 4 Interrupt DMA_4 28 DMA Channel 3 Interrupt DMA_3 27 DMA Channel 2 Interrupt DMA_2 26 DMA Channel 1 Interrupt DMA_1 25 DMA Channel 0 Interrupt PEP_9 17 Pipe 9 Interrupt PEP_8 16 Pipe 8 Interrupt PEP_7 15 Pipe 7 Interrupt PEP_6 14 Pipe 6 Interrupt PEP_5 13 Pipe 5 Interrupt PEP_4 12 Pipe 4 Interrupt PEP_3 11 Pipe 3 Interrupt PEP_2 10 Pipe 2 Interrupt PEP_1 9 Pipe 1 Interrupt PEP_0 8 Pipe 0 Interrupt HWUPI 6 Host Wake-Up Interrupt HSOFI 5 Host Start of Frame Interrupt RXRSMI 4 Upstream Resume Received Interrupt RSMEDI 3 Downstream Resume Sent Interrupt RSTI 2 USB Reset Sent Interrupt DDISCI 1 Device Disconnection Interrupt DCONNI 0 Device Connection Interrupt DMA_7 31 DMA Channel 6 Interrupt
USBHS_HSTICRHost Global Interrupt Clear Register
Address 0x40038408
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does HWUPIC 6 Host Wake-Up Interrupt Clear HSOFIC 5 Host Start of Frame Interrupt Clear RXRSMIC 4 Upstream Resume Received Interrupt Clear RSMEDIC 3 Downstream Resume Sent Interrupt Clear RSTIC 2 USB Reset Sent Interrupt Clear DDISCIC 1 Device Disconnection Interrupt Clear DCONNIC 0 Device Connection Interrupt Clear
USBHS_HSTIFRHost Global Interrupt Set Register
Address 0x4003840C
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does DMA_6 30 DMA Channel 5 Interrupt Set DMA_5 29 DMA Channel 4 Interrupt Set DMA_4 28 DMA Channel 3 Interrupt Set DMA_3 27 DMA Channel 2 Interrupt Set DMA_2 26 DMA Channel 1 Interrupt Set DMA_1 25 DMA Channel 0 Interrupt Set HWUPIS 6 Host Wake-Up Interrupt Set HSOFIS 5 Host Start of Frame Interrupt Set RXRSMIS 4 Upstream Resume Received Interrupt Set RSMEDIS 3 Downstream Resume Sent Interrupt Set RSTIS 2 USB Reset Sent Interrupt Set DDISCIS 1 Device Disconnection Interrupt Set DCONNIS 0 Device Connection Interrupt Set DMA_7 31 DMA Channel 6 Interrupt Set
USBHS_HSTIMRHost Global Interrupt Mask Register
Address 0x40038410
Reset 0x00000000
Access read only
Size 32-bit 24 fields
Field Bits What it does DMA_6 30 DMA Channel 5 Interrupt Enable DMA_5 29 DMA Channel 4 Interrupt Enable DMA_4 28 DMA Channel 3 Interrupt Enable DMA_3 27 DMA Channel 2 Interrupt Enable DMA_2 26 DMA Channel 1 Interrupt Enable DMA_1 25 DMA Channel 0 Interrupt Enable PEP_9 17 Pipe 9 Interrupt Enable PEP_8 16 Pipe 8 Interrupt Enable PEP_7 15 Pipe 7 Interrupt Enable PEP_6 14 Pipe 6 Interrupt Enable PEP_5 13 Pipe 5 Interrupt Enable PEP_4 12 Pipe 4 Interrupt Enable PEP_3 11 Pipe 3 Interrupt Enable PEP_2 10 Pipe 2 Interrupt Enable PEP_1 9 Pipe 1 Interrupt Enable PEP_0 8 Pipe 0 Interrupt Enable HWUPIE 6 Host Wake-Up Interrupt Enable HSOFIE 5 Host Start of Frame Interrupt Enable RXRSMIE 4 Upstream Resume Received Interrupt Enable RSMEDIE 3 Downstream Resume Sent Interrupt Enable RSTIE 2 USB Reset Sent Interrupt Enable DDISCIE 1 Device Disconnection Interrupt Enable DCONNIE 0 Device Connection Interrupt Enable DMA_7 31 DMA Channel 6 Interrupt Enable
USBHS_HSTIDRHost Global Interrupt Disable Register
Address 0x40038414
Reset 0x00000000
Access write only
Size 32-bit 24 fields
Field Bits What it does DMA_6 30 DMA Channel 5 Interrupt Disable DMA_5 29 DMA Channel 4 Interrupt Disable DMA_4 28 DMA Channel 3 Interrupt Disable DMA_3 27 DMA Channel 2 Interrupt Disable DMA_2 26 DMA Channel 1 Interrupt Disable DMA_1 25 DMA Channel 0 Interrupt Disable PEP_9 17 Pipe 9 Interrupt Disable PEP_8 16 Pipe 8 Interrupt Disable PEP_7 15 Pipe 7 Interrupt Disable PEP_6 14 Pipe 6 Interrupt Disable PEP_5 13 Pipe 5 Interrupt Disable PEP_4 12 Pipe 4 Interrupt Disable PEP_3 11 Pipe 3 Interrupt Disable PEP_2 10 Pipe 2 Interrupt Disable PEP_1 9 Pipe 1 Interrupt Disable PEP_0 8 Pipe 0 Interrupt Disable HWUPIEC 6 Host Wake-Up Interrupt Disable HSOFIEC 5 Host Start of Frame Interrupt Disable RXRSMIEC 4 Upstream Resume Received Interrupt Disable RSMEDIEC 3 Downstream Resume Sent Interrupt Disable RSTIEC 2 USB Reset Sent Interrupt Disable DDISCIEC 1 Device Disconnection Interrupt Disable DCONNIEC 0 Device Connection Interrupt Disable DMA_7 31 DMA Channel 6 Interrupt Disable
USBHS_HSTIERHost Global Interrupt Enable Register
Address 0x40038418
Reset 0x00000000
Access write only
Size 32-bit 24 fields
Field Bits What it does DMA_6 30 DMA Channel 5 Interrupt Enable DMA_5 29 DMA Channel 4 Interrupt Enable DMA_4 28 DMA Channel 3 Interrupt Enable DMA_3 27 DMA Channel 2 Interrupt Enable DMA_2 26 DMA Channel 1 Interrupt Enable DMA_1 25 DMA Channel 0 Interrupt Enable PEP_9 17 Pipe 9 Interrupt Enable PEP_8 16 Pipe 8 Interrupt Enable PEP_7 15 Pipe 7 Interrupt Enable PEP_6 14 Pipe 6 Interrupt Enable PEP_5 13 Pipe 5 Interrupt Enable PEP_4 12 Pipe 4 Interrupt Enable PEP_3 11 Pipe 3 Interrupt Enable PEP_2 10 Pipe 2 Interrupt Enable PEP_1 9 Pipe 1 Interrupt Enable PEP_0 8 Pipe 0 Interrupt Enable HWUPIES 6 Host Wake-Up Interrupt Enable HSOFIES 5 Host Start of Frame Interrupt Enable RXRSMIES 4 Upstream Resume Received Interrupt Enable RSMEDIES 3 Downstream Resume Sent Interrupt Enable RSTIES 2 USB Reset Sent Interrupt Enable DDISCIES 1 Device Disconnection Interrupt Enable DCONNIES 0 Device Connection Interrupt Enable DMA_7 31 DMA Channel 6 Interrupt Enable
USBHS_HSTPIPHost Pipe Register
Address 0x4003841C
Reset 0x00000000
Access read/write
Size 32-bit 18 fields
Field Bits What it does PRST8 24 Pipe 8 Reset PRST7 23 Pipe 7 Reset PRST6 22 Pipe 6 Reset PRST5 21 Pipe 5 Reset PRST4 20 Pipe 4 Reset PRST3 19 Pipe 3 Reset PRST2 18 Pipe 2 Reset PRST1 17 Pipe 1 Reset PRST0 16 Pipe 0 Reset PEN8 8 Pipe 8 Enable PEN7 7 Pipe 7 Enable PEN6 6 Pipe 6 Enable PEN5 5 Pipe 5 Enable PEN4 4 Pipe 4 Enable PEN3 3 Pipe 3 Enable PEN2 2 Pipe 2 Enable PEN1 1 Pipe 1 Enable PEN0 0 Pipe 0 Enable
USBHS_HSTFNUMHost Frame Number Register
Address 0x40038420
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does FLENHIGH 23:16 Frame Length FNUM 13:3 Frame Number MFNUM 2:0 Micro Frame Number
USBHS_HSTADDR1Host Address 1 Register
Address 0x40038424
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does HSTADDRP3 30:24 USB Host Address HSTADDRP2 22:16 USB Host Address HSTADDRP1 14:8 USB Host Address HSTADDRP0 6:0 USB Host Address
USBHS_HSTADDR2Host Address 2 Register
Address 0x40038428
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does HSTADDRP7 30:24 USB Host Address HSTADDRP6 22:16 USB Host Address HSTADDRP5 14:8 USB Host Address HSTADDRP4 6:0 USB Host Address
USBHS_HSTADDR3Host Address 3 Register
Address 0x4003842C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does HSTADDRP9 14:8 USB Host Address HSTADDRP8 6:0 USB Host Address
USBHS_HSTPIPCFG0Host Pipe Configuration Register
Address 0x40038500
Reset 0x00000000
Access read/write
Size 32-bit 10 fields
Field Bits What it does PINGEN 20 Ping Enable PEPNUM 19:16 Pipe Endpoint Number PTYPE 13:12 Pipe Type0 Control1 Isochronous2 Bulk3 Interrupt AUTOSW 10 Automatic Switch PTOKEN 9:8 Pipe Token PSIZE 6:4 Pipe Size0 8 bytes1 16 bytes2 32 bytes3 64 bytes4 128 bytes5 256 bytes6 512 bytes7 1024 bytes PBK 3:2 Pipe Banks0 Single-bank pipe1 Double-bank pipe2 Triple-bank pipe ALLOC 1 Pipe Memory Allocate BINTERVAL 31:24 bInterval Parameter for the Bulk-Out/Ping Transaction INTFRQ 31:24 Pipe Interrupt Request Frequency
USBHS_HSTPIPCFG1Host Pipe Configuration Register
Address 0x40038504
Reset 0x00000000
Access read/write
Size 32-bit 10 fields
Field Bits What it does PINGEN 20 Ping Enable PEPNUM 19:16 Pipe Endpoint Number PTYPE 13:12 Pipe Type0 Control1 Isochronous2 Bulk3 Interrupt AUTOSW 10 Automatic Switch PTOKEN 9:8 Pipe Token PSIZE 6:4 Pipe Size0 8 bytes1 16 bytes2 32 bytes3 64 bytes4 128 bytes5 256 bytes6 512 bytes7 1024 bytes PBK 3:2 Pipe Banks0 Single-bank pipe1 Double-bank pipe2 Triple-bank pipe ALLOC 1 Pipe Memory Allocate BINTERVAL 31:24 bInterval Parameter for the Bulk-Out/Ping Transaction INTFRQ 31:24 Pipe Interrupt Request Frequency
USBHS_HSTPIPCFG2Host Pipe Configuration Register
Address 0x40038508
Reset 0x00000000
Access read/write
Size 32-bit 10 fields
Field Bits What it does PINGEN 20 Ping Enable PEPNUM 19:16 Pipe Endpoint Number PTYPE 13:12 Pipe Type0 Control1 Isochronous2 Bulk3 Interrupt AUTOSW 10 Automatic Switch PTOKEN 9:8 Pipe Token PSIZE 6:4 Pipe Size0 8 bytes1 16 bytes2 32 bytes3 64 bytes4 128 bytes5 256 bytes6 512 bytes7 1024 bytes PBK 3:2 Pipe Banks0 Single-bank pipe1 Double-bank pipe2 Triple-bank pipe ALLOC 1 Pipe Memory Allocate BINTERVAL 31:24 bInterval Parameter for the Bulk-Out/Ping Transaction INTFRQ 31:24 Pipe Interrupt Request Frequency
USBHS_HSTPIPCFG3Host Pipe Configuration Register
Address 0x4003850C
Reset 0x00000000
Access read/write
Size 32-bit 10 fields
Field Bits What it does PINGEN 20 Ping Enable PEPNUM 19:16 Pipe Endpoint Number PTYPE 13:12 Pipe Type0 Control1 Isochronous2 Bulk3 Interrupt AUTOSW 10 Automatic Switch PTOKEN 9:8 Pipe Token PSIZE 6:4 Pipe Size0 8 bytes1 16 bytes2 32 bytes3 64 bytes4 128 bytes5 256 bytes6 512 bytes7 1024 bytes PBK 3:2 Pipe Banks0 Single-bank pipe1 Double-bank pipe2 Triple-bank pipe ALLOC 1 Pipe Memory Allocate BINTERVAL 31:24 bInterval Parameter for the Bulk-Out/Ping Transaction INTFRQ 31:24 Pipe Interrupt Request Frequency
USBHS_HSTPIPCFG4Host Pipe Configuration Register
Address 0x40038510
Reset 0x00000000
Access read/write
Size 32-bit 10 fields
Field Bits What it does PINGEN 20 Ping Enable PEPNUM 19:16 Pipe Endpoint Number PTYPE 13:12 Pipe Type0 Control1 Isochronous2 Bulk3 Interrupt AUTOSW 10 Automatic Switch PTOKEN 9:8 Pipe Token PSIZE 6:4 Pipe Size0 8 bytes1 16 bytes2 32 bytes3 64 bytes4 128 bytes5 256 bytes6 512 bytes7 1024 bytes PBK 3:2 Pipe Banks0 Single-bank pipe1 Double-bank pipe2 Triple-bank pipe ALLOC 1 Pipe Memory Allocate BINTERVAL 31:24 bInterval Parameter for the Bulk-Out/Ping Transaction INTFRQ 31:24 Pipe Interrupt Request Frequency
USBHS_HSTPIPCFG5Host Pipe Configuration Register
Address 0x40038514
Reset 0x00000000
Access read/write
Size 32-bit 10 fields
Field Bits What it does PINGEN 20 Ping Enable PEPNUM 19:16 Pipe Endpoint Number PTYPE 13:12 Pipe Type0 Control1 Isochronous2 Bulk3 Interrupt AUTOSW 10 Automatic Switch PTOKEN 9:8 Pipe Token PSIZE 6:4 Pipe Size0 8 bytes1 16 bytes2 32 bytes3 64 bytes4 128 bytes5 256 bytes6 512 bytes7 1024 bytes PBK 3:2 Pipe Banks0 Single-bank pipe1 Double-bank pipe2 Triple-bank pipe ALLOC 1 Pipe Memory Allocate BINTERVAL 31:24 bInterval Parameter for the Bulk-Out/Ping Transaction INTFRQ 31:24 Pipe Interrupt Request Frequency
USBHS_HSTPIPCFG6Host Pipe Configuration Register
Address 0x40038518
Reset 0x00000000
Access read/write
Size 32-bit 10 fields
Field Bits What it does PINGEN 20 Ping Enable PEPNUM 19:16 Pipe Endpoint Number PTYPE 13:12 Pipe Type0 Control1 Isochronous2 Bulk3 Interrupt AUTOSW 10 Automatic Switch PTOKEN 9:8 Pipe Token PSIZE 6:4 Pipe Size0 8 bytes1 16 bytes2 32 bytes3 64 bytes4 128 bytes5 256 bytes6 512 bytes7 1024 bytes PBK 3:2 Pipe Banks0 Single-bank pipe1 Double-bank pipe2 Triple-bank pipe ALLOC 1 Pipe Memory Allocate BINTERVAL 31:24 bInterval Parameter for the Bulk-Out/Ping Transaction INTFRQ 31:24 Pipe Interrupt Request Frequency
USBHS_HSTPIPCFG7Host Pipe Configuration Register
Address 0x4003851C
Reset 0x00000000
Access read/write
Size 32-bit 10 fields
Field Bits What it does PINGEN 20 Ping Enable PEPNUM 19:16 Pipe Endpoint Number PTYPE 13:12 Pipe Type0 Control1 Isochronous2 Bulk3 Interrupt AUTOSW 10 Automatic Switch PTOKEN 9:8 Pipe Token PSIZE 6:4 Pipe Size0 8 bytes1 16 bytes2 32 bytes3 64 bytes4 128 bytes5 256 bytes6 512 bytes7 1024 bytes PBK 3:2 Pipe Banks0 Single-bank pipe1 Double-bank pipe2 Triple-bank pipe ALLOC 1 Pipe Memory Allocate BINTERVAL 31:24 bInterval Parameter for the Bulk-Out/Ping Transaction INTFRQ 31:24 Pipe Interrupt Request Frequency
USBHS_HSTPIPCFG8Host Pipe Configuration Register
Address 0x40038520
Reset 0x00000000
Access read/write
Size 32-bit 10 fields
Field Bits What it does PINGEN 20 Ping Enable PEPNUM 19:16 Pipe Endpoint Number PTYPE 13:12 Pipe Type0 Control1 Isochronous2 Bulk3 Interrupt AUTOSW 10 Automatic Switch PTOKEN 9:8 Pipe Token PSIZE 6:4 Pipe Size0 8 bytes1 16 bytes2 32 bytes3 64 bytes4 128 bytes5 256 bytes6 512 bytes7 1024 bytes PBK 3:2 Pipe Banks0 Single-bank pipe1 Double-bank pipe2 Triple-bank pipe ALLOC 1 Pipe Memory Allocate BINTERVAL 31:24 bInterval Parameter for the Bulk-Out/Ping Transaction INTFRQ 31:24 Pipe Interrupt Request Frequency
USBHS_HSTPIPCFG9Host Pipe Configuration Register
Address 0x40038524
Reset 0x00000000
Access read/write
Size 32-bit 10 fields
Field Bits What it does PINGEN 20 Ping Enable PEPNUM 19:16 Pipe Endpoint Number PTYPE 13:12 Pipe Type0 Control1 Isochronous2 Bulk3 Interrupt AUTOSW 10 Automatic Switch PTOKEN 9:8 Pipe Token PSIZE 6:4 Pipe Size0 8 bytes1 16 bytes2 32 bytes3 64 bytes4 128 bytes5 256 bytes6 512 bytes7 1024 bytes PBK 3:2 Pipe Banks0 Single-bank pipe1 Double-bank pipe2 Triple-bank pipe ALLOC 1 Pipe Memory Allocate BINTERVAL 31:24 bInterval Parameter for the Bulk-Out/Ping Transaction INTFRQ 31:24 Pipe Interrupt Request Frequency
USBHS_HSTPIPISR0Host Pipe Status Register
Address 0x40038530
Reset 0x00000000
Access read only
Size 32-bit 16 fields
Field Bits What it does PBYCT 30:20 Pipe Byte Count CFGOK 18 Configuration OK Status RWALL 16 Read/Write Allowed CURRBK 15:14 Current Bank0 Current bank is bank01 Current bank is bank12 Current bank is bank2 NBUSYBK 13:12 Number of Busy Banks0 0 busy bank (all banks free)1 1 busy bank2 2 busy banks3 3 busy banks DTSEQ 9:8 Data Toggle Sequence0 Data0 toggle sequence1 Data1 toggle sequence SHORTPACKETI 7 Short Packet Interrupt CRCERRI 6 CRC Error Interrupt RXSTALLDI 6 Received STALLed Interrupt OVERFI 5 Overflow Interrupt NAKEDI 4 NAKed Interrupt PERRI 3 Pipe Error Interrupt TXSTPI 2 Transmitted SETUP Interrupt UNDERFI 2 Underflow Interrupt TXOUTI 1 Transmitted OUT Data Interrupt RXINI 0 Received IN Data Interrupt
USBHS_HSTPIPISR1Host Pipe Status Register
Address 0x40038534
Reset 0x00000000
Access read only
Size 32-bit 16 fields
Field Bits What it does PBYCT 30:20 Pipe Byte Count CFGOK 18 Configuration OK Status RWALL 16 Read/Write Allowed CURRBK 15:14 Current Bank0 Current bank is bank01 Current bank is bank12 Current bank is bank2 NBUSYBK 13:12 Number of Busy Banks0 0 busy bank (all banks free)1 1 busy bank2 2 busy banks3 3 busy banks DTSEQ 9:8 Data Toggle Sequence0 Data0 toggle sequence1 Data1 toggle sequence SHORTPACKETI 7 Short Packet Interrupt CRCERRI 6 CRC Error Interrupt RXSTALLDI 6 Received STALLed Interrupt OVERFI 5 Overflow Interrupt NAKEDI 4 NAKed Interrupt PERRI 3 Pipe Error Interrupt TXSTPI 2 Transmitted SETUP Interrupt UNDERFI 2 Underflow Interrupt TXOUTI 1 Transmitted OUT Data Interrupt RXINI 0 Received IN Data Interrupt
USBHS_HSTPIPISR2Host Pipe Status Register
Address 0x40038538
Reset 0x00000000
Access read only
Size 32-bit 16 fields
Field Bits What it does PBYCT 30:20 Pipe Byte Count CFGOK 18 Configuration OK Status RWALL 16 Read/Write Allowed CURRBK 15:14 Current Bank0 Current bank is bank01 Current bank is bank12 Current bank is bank2 NBUSYBK 13:12 Number of Busy Banks0 0 busy bank (all banks free)1 1 busy bank2 2 busy banks3 3 busy banks DTSEQ 9:8 Data Toggle Sequence0 Data0 toggle sequence1 Data1 toggle sequence SHORTPACKETI 7 Short Packet Interrupt CRCERRI 6 CRC Error Interrupt RXSTALLDI 6 Received STALLed Interrupt OVERFI 5 Overflow Interrupt NAKEDI 4 NAKed Interrupt PERRI 3 Pipe Error Interrupt TXSTPI 2 Transmitted SETUP Interrupt UNDERFI 2 Underflow Interrupt TXOUTI 1 Transmitted OUT Data Interrupt RXINI 0 Received IN Data Interrupt
USBHS_HSTPIPISR3Host Pipe Status Register
Address 0x4003853C
Reset 0x00000000
Access read only
Size 32-bit 16 fields
Field Bits What it does PBYCT 30:20 Pipe Byte Count CFGOK 18 Configuration OK Status RWALL 16 Read/Write Allowed CURRBK 15:14 Current Bank0 Current bank is bank01 Current bank is bank12 Current bank is bank2 NBUSYBK 13:12 Number of Busy Banks0 0 busy bank (all banks free)1 1 busy bank2 2 busy banks3 3 busy banks DTSEQ 9:8 Data Toggle Sequence0 Data0 toggle sequence1 Data1 toggle sequence SHORTPACKETI 7 Short Packet Interrupt CRCERRI 6 CRC Error Interrupt RXSTALLDI 6 Received STALLed Interrupt OVERFI 5 Overflow Interrupt NAKEDI 4 NAKed Interrupt PERRI 3 Pipe Error Interrupt TXSTPI 2 Transmitted SETUP Interrupt UNDERFI 2 Underflow Interrupt TXOUTI 1 Transmitted OUT Data Interrupt RXINI 0 Received IN Data Interrupt
USBHS_HSTPIPISR4Host Pipe Status Register
Address 0x40038540
Reset 0x00000000
Access read only
Size 32-bit 16 fields
Field Bits What it does PBYCT 30:20 Pipe Byte Count CFGOK 18 Configuration OK Status RWALL 16 Read/Write Allowed CURRBK 15:14 Current Bank0 Current bank is bank01 Current bank is bank12 Current bank is bank2 NBUSYBK 13:12 Number of Busy Banks0 0 busy bank (all banks free)1 1 busy bank2 2 busy banks3 3 busy banks DTSEQ 9:8 Data Toggle Sequence0 Data0 toggle sequence1 Data1 toggle sequence SHORTPACKETI 7 Short Packet Interrupt CRCERRI 6 CRC Error Interrupt RXSTALLDI 6 Received STALLed Interrupt OVERFI 5 Overflow Interrupt NAKEDI 4 NAKed Interrupt PERRI 3 Pipe Error Interrupt TXSTPI 2 Transmitted SETUP Interrupt UNDERFI 2 Underflow Interrupt TXOUTI 1 Transmitted OUT Data Interrupt RXINI 0 Received IN Data Interrupt
USBHS_HSTPIPISR5Host Pipe Status Register
Address 0x40038544
Reset 0x00000000
Access read only
Size 32-bit 16 fields
Field Bits What it does PBYCT 30:20 Pipe Byte Count CFGOK 18 Configuration OK Status RWALL 16 Read/Write Allowed CURRBK 15:14 Current Bank0 Current bank is bank01 Current bank is bank12 Current bank is bank2 NBUSYBK 13:12 Number of Busy Banks0 0 busy bank (all banks free)1 1 busy bank2 2 busy banks3 3 busy banks DTSEQ 9:8 Data Toggle Sequence0 Data0 toggle sequence1 Data1 toggle sequence SHORTPACKETI 7 Short Packet Interrupt CRCERRI 6 CRC Error Interrupt RXSTALLDI 6 Received STALLed Interrupt OVERFI 5 Overflow Interrupt NAKEDI 4 NAKed Interrupt PERRI 3 Pipe Error Interrupt TXSTPI 2 Transmitted SETUP Interrupt UNDERFI 2 Underflow Interrupt TXOUTI 1 Transmitted OUT Data Interrupt RXINI 0 Received IN Data Interrupt
USBHS_HSTPIPISR6Host Pipe Status Register
Address 0x40038548
Reset 0x00000000
Access read only
Size 32-bit 16 fields
Field Bits What it does PBYCT 30:20 Pipe Byte Count CFGOK 18 Configuration OK Status RWALL 16 Read/Write Allowed CURRBK 15:14 Current Bank0 Current bank is bank01 Current bank is bank12 Current bank is bank2 NBUSYBK 13:12 Number of Busy Banks0 0 busy bank (all banks free)1 1 busy bank2 2 busy banks3 3 busy banks DTSEQ 9:8 Data Toggle Sequence0 Data0 toggle sequence1 Data1 toggle sequence SHORTPACKETI 7 Short Packet Interrupt CRCERRI 6 CRC Error Interrupt RXSTALLDI 6 Received STALLed Interrupt OVERFI 5 Overflow Interrupt NAKEDI 4 NAKed Interrupt PERRI 3 Pipe Error Interrupt TXSTPI 2 Transmitted SETUP Interrupt UNDERFI 2 Underflow Interrupt TXOUTI 1 Transmitted OUT Data Interrupt RXINI 0 Received IN Data Interrupt
USBHS_HSTPIPISR7Host Pipe Status Register
Address 0x4003854C
Reset 0x00000000
Access read only
Size 32-bit 16 fields
Field Bits What it does PBYCT 30:20 Pipe Byte Count CFGOK 18 Configuration OK Status RWALL 16 Read/Write Allowed CURRBK 15:14 Current Bank0 Current bank is bank01 Current bank is bank12 Current bank is bank2 NBUSYBK 13:12 Number of Busy Banks0 0 busy bank (all banks free)1 1 busy bank2 2 busy banks3 3 busy banks DTSEQ 9:8 Data Toggle Sequence0 Data0 toggle sequence1 Data1 toggle sequence SHORTPACKETI 7 Short Packet Interrupt CRCERRI 6 CRC Error Interrupt RXSTALLDI 6 Received STALLed Interrupt OVERFI 5 Overflow Interrupt NAKEDI 4 NAKed Interrupt PERRI 3 Pipe Error Interrupt TXSTPI 2 Transmitted SETUP Interrupt UNDERFI 2 Underflow Interrupt TXOUTI 1 Transmitted OUT Data Interrupt RXINI 0 Received IN Data Interrupt
USBHS_HSTPIPISR8Host Pipe Status Register
Address 0x40038550
Reset 0x00000000
Access read only
Size 32-bit 16 fields
Field Bits What it does PBYCT 30:20 Pipe Byte Count CFGOK 18 Configuration OK Status RWALL 16 Read/Write Allowed CURRBK 15:14 Current Bank0 Current bank is bank01 Current bank is bank12 Current bank is bank2 NBUSYBK 13:12 Number of Busy Banks0 0 busy bank (all banks free)1 1 busy bank2 2 busy banks3 3 busy banks DTSEQ 9:8 Data Toggle Sequence0 Data0 toggle sequence1 Data1 toggle sequence SHORTPACKETI 7 Short Packet Interrupt CRCERRI 6 CRC Error Interrupt RXSTALLDI 6 Received STALLed Interrupt OVERFI 5 Overflow Interrupt NAKEDI 4 NAKed Interrupt PERRI 3 Pipe Error Interrupt TXSTPI 2 Transmitted SETUP Interrupt UNDERFI 2 Underflow Interrupt TXOUTI 1 Transmitted OUT Data Interrupt RXINI 0 Received IN Data Interrupt
USBHS_HSTPIPISR9Host Pipe Status Register
Address 0x40038554
Reset 0x00000000
Access read only
Size 32-bit 16 fields
Field Bits What it does PBYCT 30:20 Pipe Byte Count CFGOK 18 Configuration OK Status RWALL 16 Read/Write Allowed CURRBK 15:14 Current Bank0 Current bank is bank01 Current bank is bank12 Current bank is bank2 NBUSYBK 13:12 Number of Busy Banks0 0 busy bank (all banks free)1 1 busy bank2 2 busy banks3 3 busy banks DTSEQ 9:8 Data Toggle Sequence0 Data0 toggle sequence1 Data1 toggle sequence SHORTPACKETI 7 Short Packet Interrupt CRCERRI 6 CRC Error Interrupt RXSTALLDI 6 Received STALLed Interrupt OVERFI 5 Overflow Interrupt NAKEDI 4 NAKed Interrupt PERRI 3 Pipe Error Interrupt TXSTPI 2 Transmitted SETUP Interrupt UNDERFI 2 Underflow Interrupt TXOUTI 1 Transmitted OUT Data Interrupt RXINI 0 Received IN Data Interrupt
USBHS_HSTPIPICR0Host Pipe Clear Register
Address 0x40038560
Reset 0x00000000
Access write only
Size 32-bit 9 fields
Field Bits What it does SHORTPACKETIC 7 Short Packet Interrupt Clear CRCERRIC 6 CRC Error Interrupt Clear RXSTALLDIC 6 Received STALLed Interrupt Clear OVERFIC 5 Overflow Interrupt Clear NAKEDIC 4 NAKed Interrupt Clear TXSTPIC 2 Transmitted SETUP Interrupt Clear UNDERFIC 2 Underflow Interrupt Clear TXOUTIC 1 Transmitted OUT Data Interrupt Clear RXINIC 0 Received IN Data Interrupt Clear
USBHS_HSTPIPICR1Host Pipe Clear Register
Address 0x40038564
Reset 0x00000000
Access write only
Size 32-bit 9 fields
Field Bits What it does SHORTPACKETIC 7 Short Packet Interrupt Clear CRCERRIC 6 CRC Error Interrupt Clear RXSTALLDIC 6 Received STALLed Interrupt Clear OVERFIC 5 Overflow Interrupt Clear NAKEDIC 4 NAKed Interrupt Clear TXSTPIC 2 Transmitted SETUP Interrupt Clear UNDERFIC 2 Underflow Interrupt Clear TXOUTIC 1 Transmitted OUT Data Interrupt Clear RXINIC 0 Received IN Data Interrupt Clear
USBHS_HSTPIPICR2Host Pipe Clear Register
Address 0x40038568
Reset 0x00000000
Access write only
Size 32-bit 9 fields
Field Bits What it does SHORTPACKETIC 7 Short Packet Interrupt Clear CRCERRIC 6 CRC Error Interrupt Clear RXSTALLDIC 6 Received STALLed Interrupt Clear OVERFIC 5 Overflow Interrupt Clear NAKEDIC 4 NAKed Interrupt Clear TXSTPIC 2 Transmitted SETUP Interrupt Clear UNDERFIC 2 Underflow Interrupt Clear TXOUTIC 1 Transmitted OUT Data Interrupt Clear RXINIC 0 Received IN Data Interrupt Clear
USBHS_HSTPIPICR3Host Pipe Clear Register
Address 0x4003856C
Reset 0x00000000
Access write only
Size 32-bit 9 fields
Field Bits What it does SHORTPACKETIC 7 Short Packet Interrupt Clear CRCERRIC 6 CRC Error Interrupt Clear RXSTALLDIC 6 Received STALLed Interrupt Clear OVERFIC 5 Overflow Interrupt Clear NAKEDIC 4 NAKed Interrupt Clear TXSTPIC 2 Transmitted SETUP Interrupt Clear UNDERFIC 2 Underflow Interrupt Clear TXOUTIC 1 Transmitted OUT Data Interrupt Clear RXINIC 0 Received IN Data Interrupt Clear
USBHS_HSTPIPICR4Host Pipe Clear Register
Address 0x40038570
Reset 0x00000000
Access write only
Size 32-bit 9 fields
Field Bits What it does SHORTPACKETIC 7 Short Packet Interrupt Clear CRCERRIC 6 CRC Error Interrupt Clear RXSTALLDIC 6 Received STALLed Interrupt Clear OVERFIC 5 Overflow Interrupt Clear NAKEDIC 4 NAKed Interrupt Clear TXSTPIC 2 Transmitted SETUP Interrupt Clear UNDERFIC 2 Underflow Interrupt Clear TXOUTIC 1 Transmitted OUT Data Interrupt Clear RXINIC 0 Received IN Data Interrupt Clear
USBHS_HSTPIPICR5Host Pipe Clear Register
Address 0x40038574
Reset 0x00000000
Access write only
Size 32-bit 9 fields
Field Bits What it does SHORTPACKETIC 7 Short Packet Interrupt Clear CRCERRIC 6 CRC Error Interrupt Clear RXSTALLDIC 6 Received STALLed Interrupt Clear OVERFIC 5 Overflow Interrupt Clear NAKEDIC 4 NAKed Interrupt Clear TXSTPIC 2 Transmitted SETUP Interrupt Clear UNDERFIC 2 Underflow Interrupt Clear TXOUTIC 1 Transmitted OUT Data Interrupt Clear RXINIC 0 Received IN Data Interrupt Clear
USBHS_HSTPIPICR6Host Pipe Clear Register
Address 0x40038578
Reset 0x00000000
Access write only
Size 32-bit 9 fields
Field Bits What it does SHORTPACKETIC 7 Short Packet Interrupt Clear CRCERRIC 6 CRC Error Interrupt Clear RXSTALLDIC 6 Received STALLed Interrupt Clear OVERFIC 5 Overflow Interrupt Clear NAKEDIC 4 NAKed Interrupt Clear TXSTPIC 2 Transmitted SETUP Interrupt Clear UNDERFIC 2 Underflow Interrupt Clear TXOUTIC 1 Transmitted OUT Data Interrupt Clear RXINIC 0 Received IN Data Interrupt Clear
USBHS_HSTPIPICR7Host Pipe Clear Register
Address 0x4003857C
Reset 0x00000000
Access write only
Size 32-bit 9 fields
Field Bits What it does SHORTPACKETIC 7 Short Packet Interrupt Clear CRCERRIC 6 CRC Error Interrupt Clear RXSTALLDIC 6 Received STALLed Interrupt Clear OVERFIC 5 Overflow Interrupt Clear NAKEDIC 4 NAKed Interrupt Clear TXSTPIC 2 Transmitted SETUP Interrupt Clear UNDERFIC 2 Underflow Interrupt Clear TXOUTIC 1 Transmitted OUT Data Interrupt Clear RXINIC 0 Received IN Data Interrupt Clear
USBHS_HSTPIPICR8Host Pipe Clear Register
Address 0x40038580
Reset 0x00000000
Access write only
Size 32-bit 9 fields
Field Bits What it does SHORTPACKETIC 7 Short Packet Interrupt Clear CRCERRIC 6 CRC Error Interrupt Clear RXSTALLDIC 6 Received STALLed Interrupt Clear OVERFIC 5 Overflow Interrupt Clear NAKEDIC 4 NAKed Interrupt Clear TXSTPIC 2 Transmitted SETUP Interrupt Clear UNDERFIC 2 Underflow Interrupt Clear TXOUTIC 1 Transmitted OUT Data Interrupt Clear RXINIC 0 Received IN Data Interrupt Clear
USBHS_HSTPIPICR9Host Pipe Clear Register
Address 0x40038584
Reset 0x00000000
Access write only
Size 32-bit 9 fields
Field Bits What it does SHORTPACKETIC 7 Short Packet Interrupt Clear CRCERRIC 6 CRC Error Interrupt Clear RXSTALLDIC 6 Received STALLed Interrupt Clear OVERFIC 5 Overflow Interrupt Clear NAKEDIC 4 NAKed Interrupt Clear TXSTPIC 2 Transmitted SETUP Interrupt Clear UNDERFIC 2 Underflow Interrupt Clear TXOUTIC 1 Transmitted OUT Data Interrupt Clear RXINIC 0 Received IN Data Interrupt Clear
USBHS_HSTPIPIFR0Host Pipe Set Register
Address 0x40038590
Reset 0x00000000
Access write only
Size 32-bit 11 fields
Field Bits What it does NBUSYBKS 12 Number of Busy Banks Set SHORTPACKETIS 7 Short Packet Interrupt Set CRCERRIS 6 CRC Error Interrupt Set RXSTALLDIS 6 Received STALLed Interrupt Set OVERFIS 5 Overflow Interrupt Set NAKEDIS 4 NAKed Interrupt Set PERRIS 3 Pipe Error Interrupt Set TXSTPIS 2 Transmitted SETUP Interrupt Set UNDERFIS 2 Underflow Interrupt Set TXOUTIS 1 Transmitted OUT Data Interrupt Set RXINIS 0 Received IN Data Interrupt Set
USBHS_HSTPIPIFR1Host Pipe Set Register
Address 0x40038594
Reset 0x00000000
Access write only
Size 32-bit 11 fields
Field Bits What it does NBUSYBKS 12 Number of Busy Banks Set SHORTPACKETIS 7 Short Packet Interrupt Set CRCERRIS 6 CRC Error Interrupt Set RXSTALLDIS 6 Received STALLed Interrupt Set OVERFIS 5 Overflow Interrupt Set NAKEDIS 4 NAKed Interrupt Set PERRIS 3 Pipe Error Interrupt Set TXSTPIS 2 Transmitted SETUP Interrupt Set UNDERFIS 2 Underflow Interrupt Set TXOUTIS 1 Transmitted OUT Data Interrupt Set RXINIS 0 Received IN Data Interrupt Set
USBHS_HSTPIPIFR2Host Pipe Set Register
Address 0x40038598
Reset 0x00000000
Access write only
Size 32-bit 11 fields
Field Bits What it does NBUSYBKS 12 Number of Busy Banks Set SHORTPACKETIS 7 Short Packet Interrupt Set CRCERRIS 6 CRC Error Interrupt Set RXSTALLDIS 6 Received STALLed Interrupt Set OVERFIS 5 Overflow Interrupt Set NAKEDIS 4 NAKed Interrupt Set PERRIS 3 Pipe Error Interrupt Set TXSTPIS 2 Transmitted SETUP Interrupt Set UNDERFIS 2 Underflow Interrupt Set TXOUTIS 1 Transmitted OUT Data Interrupt Set RXINIS 0 Received IN Data Interrupt Set
USBHS_HSTPIPIFR3Host Pipe Set Register
Address 0x4003859C
Reset 0x00000000
Access write only
Size 32-bit 11 fields
Field Bits What it does NBUSYBKS 12 Number of Busy Banks Set SHORTPACKETIS 7 Short Packet Interrupt Set CRCERRIS 6 CRC Error Interrupt Set RXSTALLDIS 6 Received STALLed Interrupt Set OVERFIS 5 Overflow Interrupt Set NAKEDIS 4 NAKed Interrupt Set PERRIS 3 Pipe Error Interrupt Set TXSTPIS 2 Transmitted SETUP Interrupt Set UNDERFIS 2 Underflow Interrupt Set TXOUTIS 1 Transmitted OUT Data Interrupt Set RXINIS 0 Received IN Data Interrupt Set
USBHS_HSTPIPIFR4Host Pipe Set Register
Address 0x400385A0
Reset 0x00000000
Access write only
Size 32-bit 11 fields
Field Bits What it does NBUSYBKS 12 Number of Busy Banks Set SHORTPACKETIS 7 Short Packet Interrupt Set CRCERRIS 6 CRC Error Interrupt Set RXSTALLDIS 6 Received STALLed Interrupt Set OVERFIS 5 Overflow Interrupt Set NAKEDIS 4 NAKed Interrupt Set PERRIS 3 Pipe Error Interrupt Set TXSTPIS 2 Transmitted SETUP Interrupt Set UNDERFIS 2 Underflow Interrupt Set TXOUTIS 1 Transmitted OUT Data Interrupt Set RXINIS 0 Received IN Data Interrupt Set
USBHS_HSTPIPIFR5Host Pipe Set Register
Address 0x400385A4
Reset 0x00000000
Access write only
Size 32-bit 11 fields
Field Bits What it does NBUSYBKS 12 Number of Busy Banks Set SHORTPACKETIS 7 Short Packet Interrupt Set CRCERRIS 6 CRC Error Interrupt Set RXSTALLDIS 6 Received STALLed Interrupt Set OVERFIS 5 Overflow Interrupt Set NAKEDIS 4 NAKed Interrupt Set PERRIS 3 Pipe Error Interrupt Set TXSTPIS 2 Transmitted SETUP Interrupt Set UNDERFIS 2 Underflow Interrupt Set TXOUTIS 1 Transmitted OUT Data Interrupt Set RXINIS 0 Received IN Data Interrupt Set
USBHS_HSTPIPIFR6Host Pipe Set Register
Address 0x400385A8
Reset 0x00000000
Access write only
Size 32-bit 11 fields
Field Bits What it does NBUSYBKS 12 Number of Busy Banks Set SHORTPACKETIS 7 Short Packet Interrupt Set CRCERRIS 6 CRC Error Interrupt Set RXSTALLDIS 6 Received STALLed Interrupt Set OVERFIS 5 Overflow Interrupt Set NAKEDIS 4 NAKed Interrupt Set PERRIS 3 Pipe Error Interrupt Set TXSTPIS 2 Transmitted SETUP Interrupt Set UNDERFIS 2 Underflow Interrupt Set TXOUTIS 1 Transmitted OUT Data Interrupt Set RXINIS 0 Received IN Data Interrupt Set
USBHS_HSTPIPIFR7Host Pipe Set Register
Address 0x400385AC
Reset 0x00000000
Access write only
Size 32-bit 11 fields
Field Bits What it does NBUSYBKS 12 Number of Busy Banks Set SHORTPACKETIS 7 Short Packet Interrupt Set CRCERRIS 6 CRC Error Interrupt Set RXSTALLDIS 6 Received STALLed Interrupt Set OVERFIS 5 Overflow Interrupt Set NAKEDIS 4 NAKed Interrupt Set PERRIS 3 Pipe Error Interrupt Set TXSTPIS 2 Transmitted SETUP Interrupt Set UNDERFIS 2 Underflow Interrupt Set TXOUTIS 1 Transmitted OUT Data Interrupt Set RXINIS 0 Received IN Data Interrupt Set
USBHS_HSTPIPIFR8Host Pipe Set Register
Address 0x400385B0
Reset 0x00000000
Access write only
Size 32-bit 11 fields
Field Bits What it does NBUSYBKS 12 Number of Busy Banks Set SHORTPACKETIS 7 Short Packet Interrupt Set CRCERRIS 6 CRC Error Interrupt Set RXSTALLDIS 6 Received STALLed Interrupt Set OVERFIS 5 Overflow Interrupt Set NAKEDIS 4 NAKed Interrupt Set PERRIS 3 Pipe Error Interrupt Set TXSTPIS 2 Transmitted SETUP Interrupt Set UNDERFIS 2 Underflow Interrupt Set TXOUTIS 1 Transmitted OUT Data Interrupt Set RXINIS 0 Received IN Data Interrupt Set
USBHS_HSTPIPIFR9Host Pipe Set Register
Address 0x400385B4
Reset 0x00000000
Access write only
Size 32-bit 11 fields
Field Bits What it does NBUSYBKS 12 Number of Busy Banks Set SHORTPACKETIS 7 Short Packet Interrupt Set CRCERRIS 6 CRC Error Interrupt Set RXSTALLDIS 6 Received STALLed Interrupt Set OVERFIS 5 Overflow Interrupt Set NAKEDIS 4 NAKed Interrupt Set PERRIS 3 Pipe Error Interrupt Set TXSTPIS 2 Transmitted SETUP Interrupt Set UNDERFIS 2 Underflow Interrupt Set TXOUTIS 1 Transmitted OUT Data Interrupt Set RXINIS 0 Received IN Data Interrupt Set
USBHS_HSTPIPIMR0Host Pipe Mask Register
Address 0x400385C0
Reset 0x00000000
Access read only
Size 32-bit 15 fields
Field Bits What it does RSTDT 18 Reset Data Toggle PFREEZE 17 Pipe Freeze PDISHDMA 16 Pipe Interrupts Disable HDMA Request Enable FIFOCON 14 FIFO Control NBUSYBKE 12 Number of Busy Banks Interrupt Enable SHORTPACKETIE 7 Short Packet Interrupt Enable CRCERRE 6 CRC Error Interrupt Enable RXSTALLDE 6 Received STALLed Interrupt Enable OVERFIE 5 Overflow Interrupt Enable NAKEDE 4 NAKed Interrupt Enable PERRE 3 Pipe Error Interrupt Enable TXSTPE 2 Transmitted SETUP Interrupt Enable UNDERFIE 2 Underflow Interrupt Enable TXOUTE 1 Transmitted OUT Data Interrupt Enable RXINE 0 Received IN Data Interrupt Enable
USBHS_HSTPIPIMR1Host Pipe Mask Register
Address 0x400385C4
Reset 0x00000000
Access read only
Size 32-bit 15 fields
Field Bits What it does RSTDT 18 Reset Data Toggle PFREEZE 17 Pipe Freeze PDISHDMA 16 Pipe Interrupts Disable HDMA Request Enable FIFOCON 14 FIFO Control NBUSYBKE 12 Number of Busy Banks Interrupt Enable SHORTPACKETIE 7 Short Packet Interrupt Enable CRCERRE 6 CRC Error Interrupt Enable RXSTALLDE 6 Received STALLed Interrupt Enable OVERFIE 5 Overflow Interrupt Enable NAKEDE 4 NAKed Interrupt Enable PERRE 3 Pipe Error Interrupt Enable TXSTPE 2 Transmitted SETUP Interrupt Enable UNDERFIE 2 Underflow Interrupt Enable TXOUTE 1 Transmitted OUT Data Interrupt Enable RXINE 0 Received IN Data Interrupt Enable
USBHS_HSTPIPIMR2Host Pipe Mask Register
Address 0x400385C8
Reset 0x00000000
Access read only
Size 32-bit 15 fields
Field Bits What it does RSTDT 18 Reset Data Toggle PFREEZE 17 Pipe Freeze PDISHDMA 16 Pipe Interrupts Disable HDMA Request Enable FIFOCON 14 FIFO Control NBUSYBKE 12 Number of Busy Banks Interrupt Enable SHORTPACKETIE 7 Short Packet Interrupt Enable CRCERRE 6 CRC Error Interrupt Enable RXSTALLDE 6 Received STALLed Interrupt Enable OVERFIE 5 Overflow Interrupt Enable NAKEDE 4 NAKed Interrupt Enable PERRE 3 Pipe Error Interrupt Enable TXSTPE 2 Transmitted SETUP Interrupt Enable UNDERFIE 2 Underflow Interrupt Enable TXOUTE 1 Transmitted OUT Data Interrupt Enable RXINE 0 Received IN Data Interrupt Enable
USBHS_HSTPIPIMR3Host Pipe Mask Register
Address 0x400385CC
Reset 0x00000000
Access read only
Size 32-bit 15 fields
Field Bits What it does RSTDT 18 Reset Data Toggle PFREEZE 17 Pipe Freeze PDISHDMA 16 Pipe Interrupts Disable HDMA Request Enable FIFOCON 14 FIFO Control NBUSYBKE 12 Number of Busy Banks Interrupt Enable SHORTPACKETIE 7 Short Packet Interrupt Enable CRCERRE 6 CRC Error Interrupt Enable RXSTALLDE 6 Received STALLed Interrupt Enable OVERFIE 5 Overflow Interrupt Enable NAKEDE 4 NAKed Interrupt Enable PERRE 3 Pipe Error Interrupt Enable TXSTPE 2 Transmitted SETUP Interrupt Enable UNDERFIE 2 Underflow Interrupt Enable TXOUTE 1 Transmitted OUT Data Interrupt Enable RXINE 0 Received IN Data Interrupt Enable
USBHS_HSTPIPIMR4Host Pipe Mask Register
Address 0x400385D0
Reset 0x00000000
Access read only
Size 32-bit 15 fields
Field Bits What it does RSTDT 18 Reset Data Toggle PFREEZE 17 Pipe Freeze PDISHDMA 16 Pipe Interrupts Disable HDMA Request Enable FIFOCON 14 FIFO Control NBUSYBKE 12 Number of Busy Banks Interrupt Enable SHORTPACKETIE 7 Short Packet Interrupt Enable CRCERRE 6 CRC Error Interrupt Enable RXSTALLDE 6 Received STALLed Interrupt Enable OVERFIE 5 Overflow Interrupt Enable NAKEDE 4 NAKed Interrupt Enable PERRE 3 Pipe Error Interrupt Enable TXSTPE 2 Transmitted SETUP Interrupt Enable UNDERFIE 2 Underflow Interrupt Enable TXOUTE 1 Transmitted OUT Data Interrupt Enable RXINE 0 Received IN Data Interrupt Enable
USBHS_HSTPIPIMR5Host Pipe Mask Register
Address 0x400385D4
Reset 0x00000000
Access read only
Size 32-bit 15 fields
Field Bits What it does RSTDT 18 Reset Data Toggle PFREEZE 17 Pipe Freeze PDISHDMA 16 Pipe Interrupts Disable HDMA Request Enable FIFOCON 14 FIFO Control NBUSYBKE 12 Number of Busy Banks Interrupt Enable SHORTPACKETIE 7 Short Packet Interrupt Enable CRCERRE 6 CRC Error Interrupt Enable RXSTALLDE 6 Received STALLed Interrupt Enable OVERFIE 5 Overflow Interrupt Enable NAKEDE 4 NAKed Interrupt Enable PERRE 3 Pipe Error Interrupt Enable TXSTPE 2 Transmitted SETUP Interrupt Enable UNDERFIE 2 Underflow Interrupt Enable TXOUTE 1 Transmitted OUT Data Interrupt Enable RXINE 0 Received IN Data Interrupt Enable
USBHS_HSTPIPIMR6Host Pipe Mask Register
Address 0x400385D8
Reset 0x00000000
Access read only
Size 32-bit 15 fields
Field Bits What it does RSTDT 18 Reset Data Toggle PFREEZE 17 Pipe Freeze PDISHDMA 16 Pipe Interrupts Disable HDMA Request Enable FIFOCON 14 FIFO Control NBUSYBKE 12 Number of Busy Banks Interrupt Enable SHORTPACKETIE 7 Short Packet Interrupt Enable CRCERRE 6 CRC Error Interrupt Enable RXSTALLDE 6 Received STALLed Interrupt Enable OVERFIE 5 Overflow Interrupt Enable NAKEDE 4 NAKed Interrupt Enable PERRE 3 Pipe Error Interrupt Enable TXSTPE 2 Transmitted SETUP Interrupt Enable UNDERFIE 2 Underflow Interrupt Enable TXOUTE 1 Transmitted OUT Data Interrupt Enable RXINE 0 Received IN Data Interrupt Enable
USBHS_HSTPIPIMR7Host Pipe Mask Register
Address 0x400385DC
Reset 0x00000000
Access read only
Size 32-bit 15 fields
Field Bits What it does RSTDT 18 Reset Data Toggle PFREEZE 17 Pipe Freeze PDISHDMA 16 Pipe Interrupts Disable HDMA Request Enable FIFOCON 14 FIFO Control NBUSYBKE 12 Number of Busy Banks Interrupt Enable SHORTPACKETIE 7 Short Packet Interrupt Enable CRCERRE 6 CRC Error Interrupt Enable RXSTALLDE 6 Received STALLed Interrupt Enable OVERFIE 5 Overflow Interrupt Enable NAKEDE 4 NAKed Interrupt Enable PERRE 3 Pipe Error Interrupt Enable TXSTPE 2 Transmitted SETUP Interrupt Enable UNDERFIE 2 Underflow Interrupt Enable TXOUTE 1 Transmitted OUT Data Interrupt Enable RXINE 0 Received IN Data Interrupt Enable
USBHS_HSTPIPIMR8Host Pipe Mask Register
Address 0x400385E0
Reset 0x00000000
Access read only
Size 32-bit 15 fields
Field Bits What it does RSTDT 18 Reset Data Toggle PFREEZE 17 Pipe Freeze PDISHDMA 16 Pipe Interrupts Disable HDMA Request Enable FIFOCON 14 FIFO Control NBUSYBKE 12 Number of Busy Banks Interrupt Enable SHORTPACKETIE 7 Short Packet Interrupt Enable CRCERRE 6 CRC Error Interrupt Enable RXSTALLDE 6 Received STALLed Interrupt Enable OVERFIE 5 Overflow Interrupt Enable NAKEDE 4 NAKed Interrupt Enable PERRE 3 Pipe Error Interrupt Enable TXSTPE 2 Transmitted SETUP Interrupt Enable UNDERFIE 2 Underflow Interrupt Enable TXOUTE 1 Transmitted OUT Data Interrupt Enable RXINE 0 Received IN Data Interrupt Enable
USBHS_HSTPIPIMR9Host Pipe Mask Register
Address 0x400385E4
Reset 0x00000000
Access read only
Size 32-bit 15 fields
Field Bits What it does RSTDT 18 Reset Data Toggle PFREEZE 17 Pipe Freeze PDISHDMA 16 Pipe Interrupts Disable HDMA Request Enable FIFOCON 14 FIFO Control NBUSYBKE 12 Number of Busy Banks Interrupt Enable SHORTPACKETIE 7 Short Packet Interrupt Enable CRCERRE 6 CRC Error Interrupt Enable RXSTALLDE 6 Received STALLed Interrupt Enable OVERFIE 5 Overflow Interrupt Enable NAKEDE 4 NAKed Interrupt Enable PERRE 3 Pipe Error Interrupt Enable TXSTPE 2 Transmitted SETUP Interrupt Enable UNDERFIE 2 Underflow Interrupt Enable TXOUTE 1 Transmitted OUT Data Interrupt Enable RXINE 0 Received IN Data Interrupt Enable
USBHS_HSTPIPIER0Host Pipe Enable Register
Address 0x400385F0
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does RSTDTS 18 Reset Data Toggle Enable PFREEZES 17 Pipe Freeze Enable PDISHDMAS 16 Pipe Interrupts Disable HDMA Request Enable NBUSYBKES 12 Number of Busy Banks Enable SHORTPACKETIES 7 Short Packet Interrupt Enable CRCERRES 6 CRC Error Interrupt Enable RXSTALLDES 6 Received STALLed Interrupt Enable OVERFIES 5 Overflow Interrupt Enable NAKEDES 4 NAKed Interrupt Enable PERRES 3 Pipe Error Interrupt Enable TXSTPES 2 Transmitted SETUP Interrupt Enable UNDERFIES 2 Underflow Interrupt Enable TXOUTES 1 Transmitted OUT Data Interrupt Enable RXINES 0 Received IN Data Interrupt Enable
USBHS_HSTPIPIER1Host Pipe Enable Register
Address 0x400385F4
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does RSTDTS 18 Reset Data Toggle Enable PFREEZES 17 Pipe Freeze Enable PDISHDMAS 16 Pipe Interrupts Disable HDMA Request Enable NBUSYBKES 12 Number of Busy Banks Enable SHORTPACKETIES 7 Short Packet Interrupt Enable CRCERRES 6 CRC Error Interrupt Enable RXSTALLDES 6 Received STALLed Interrupt Enable OVERFIES 5 Overflow Interrupt Enable NAKEDES 4 NAKed Interrupt Enable PERRES 3 Pipe Error Interrupt Enable TXSTPES 2 Transmitted SETUP Interrupt Enable UNDERFIES 2 Underflow Interrupt Enable TXOUTES 1 Transmitted OUT Data Interrupt Enable RXINES 0 Received IN Data Interrupt Enable
USBHS_HSTPIPIER2Host Pipe Enable Register
Address 0x400385F8
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does RSTDTS 18 Reset Data Toggle Enable PFREEZES 17 Pipe Freeze Enable PDISHDMAS 16 Pipe Interrupts Disable HDMA Request Enable NBUSYBKES 12 Number of Busy Banks Enable SHORTPACKETIES 7 Short Packet Interrupt Enable CRCERRES 6 CRC Error Interrupt Enable RXSTALLDES 6 Received STALLed Interrupt Enable OVERFIES 5 Overflow Interrupt Enable NAKEDES 4 NAKed Interrupt Enable PERRES 3 Pipe Error Interrupt Enable TXSTPES 2 Transmitted SETUP Interrupt Enable UNDERFIES 2 Underflow Interrupt Enable TXOUTES 1 Transmitted OUT Data Interrupt Enable RXINES 0 Received IN Data Interrupt Enable
USBHS_HSTPIPIER3Host Pipe Enable Register
Address 0x400385FC
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does RSTDTS 18 Reset Data Toggle Enable PFREEZES 17 Pipe Freeze Enable PDISHDMAS 16 Pipe Interrupts Disable HDMA Request Enable NBUSYBKES 12 Number of Busy Banks Enable SHORTPACKETIES 7 Short Packet Interrupt Enable CRCERRES 6 CRC Error Interrupt Enable RXSTALLDES 6 Received STALLed Interrupt Enable OVERFIES 5 Overflow Interrupt Enable NAKEDES 4 NAKed Interrupt Enable PERRES 3 Pipe Error Interrupt Enable TXSTPES 2 Transmitted SETUP Interrupt Enable UNDERFIES 2 Underflow Interrupt Enable TXOUTES 1 Transmitted OUT Data Interrupt Enable RXINES 0 Received IN Data Interrupt Enable
USBHS_HSTPIPIER4Host Pipe Enable Register
Address 0x40038600
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does RSTDTS 18 Reset Data Toggle Enable PFREEZES 17 Pipe Freeze Enable PDISHDMAS 16 Pipe Interrupts Disable HDMA Request Enable NBUSYBKES 12 Number of Busy Banks Enable SHORTPACKETIES 7 Short Packet Interrupt Enable CRCERRES 6 CRC Error Interrupt Enable RXSTALLDES 6 Received STALLed Interrupt Enable OVERFIES 5 Overflow Interrupt Enable NAKEDES 4 NAKed Interrupt Enable PERRES 3 Pipe Error Interrupt Enable TXSTPES 2 Transmitted SETUP Interrupt Enable UNDERFIES 2 Underflow Interrupt Enable TXOUTES 1 Transmitted OUT Data Interrupt Enable RXINES 0 Received IN Data Interrupt Enable
USBHS_HSTPIPIER5Host Pipe Enable Register
Address 0x40038604
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does RSTDTS 18 Reset Data Toggle Enable PFREEZES 17 Pipe Freeze Enable PDISHDMAS 16 Pipe Interrupts Disable HDMA Request Enable NBUSYBKES 12 Number of Busy Banks Enable SHORTPACKETIES 7 Short Packet Interrupt Enable CRCERRES 6 CRC Error Interrupt Enable RXSTALLDES 6 Received STALLed Interrupt Enable OVERFIES 5 Overflow Interrupt Enable NAKEDES 4 NAKed Interrupt Enable PERRES 3 Pipe Error Interrupt Enable TXSTPES 2 Transmitted SETUP Interrupt Enable UNDERFIES 2 Underflow Interrupt Enable TXOUTES 1 Transmitted OUT Data Interrupt Enable RXINES 0 Received IN Data Interrupt Enable
USBHS_HSTPIPIER6Host Pipe Enable Register
Address 0x40038608
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does RSTDTS 18 Reset Data Toggle Enable PFREEZES 17 Pipe Freeze Enable PDISHDMAS 16 Pipe Interrupts Disable HDMA Request Enable NBUSYBKES 12 Number of Busy Banks Enable SHORTPACKETIES 7 Short Packet Interrupt Enable CRCERRES 6 CRC Error Interrupt Enable RXSTALLDES 6 Received STALLed Interrupt Enable OVERFIES 5 Overflow Interrupt Enable NAKEDES 4 NAKed Interrupt Enable PERRES 3 Pipe Error Interrupt Enable TXSTPES 2 Transmitted SETUP Interrupt Enable UNDERFIES 2 Underflow Interrupt Enable TXOUTES 1 Transmitted OUT Data Interrupt Enable RXINES 0 Received IN Data Interrupt Enable
USBHS_HSTPIPIER7Host Pipe Enable Register
Address 0x4003860C
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does RSTDTS 18 Reset Data Toggle Enable PFREEZES 17 Pipe Freeze Enable PDISHDMAS 16 Pipe Interrupts Disable HDMA Request Enable NBUSYBKES 12 Number of Busy Banks Enable SHORTPACKETIES 7 Short Packet Interrupt Enable CRCERRES 6 CRC Error Interrupt Enable RXSTALLDES 6 Received STALLed Interrupt Enable OVERFIES 5 Overflow Interrupt Enable NAKEDES 4 NAKed Interrupt Enable PERRES 3 Pipe Error Interrupt Enable TXSTPES 2 Transmitted SETUP Interrupt Enable UNDERFIES 2 Underflow Interrupt Enable TXOUTES 1 Transmitted OUT Data Interrupt Enable RXINES 0 Received IN Data Interrupt Enable
USBHS_HSTPIPIER8Host Pipe Enable Register
Address 0x40038610
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does RSTDTS 18 Reset Data Toggle Enable PFREEZES 17 Pipe Freeze Enable PDISHDMAS 16 Pipe Interrupts Disable HDMA Request Enable NBUSYBKES 12 Number of Busy Banks Enable SHORTPACKETIES 7 Short Packet Interrupt Enable CRCERRES 6 CRC Error Interrupt Enable RXSTALLDES 6 Received STALLed Interrupt Enable OVERFIES 5 Overflow Interrupt Enable NAKEDES 4 NAKed Interrupt Enable PERRES 3 Pipe Error Interrupt Enable TXSTPES 2 Transmitted SETUP Interrupt Enable UNDERFIES 2 Underflow Interrupt Enable TXOUTES 1 Transmitted OUT Data Interrupt Enable RXINES 0 Received IN Data Interrupt Enable
USBHS_HSTPIPIER9Host Pipe Enable Register
Address 0x40038614
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does RSTDTS 18 Reset Data Toggle Enable PFREEZES 17 Pipe Freeze Enable PDISHDMAS 16 Pipe Interrupts Disable HDMA Request Enable NBUSYBKES 12 Number of Busy Banks Enable SHORTPACKETIES 7 Short Packet Interrupt Enable CRCERRES 6 CRC Error Interrupt Enable RXSTALLDES 6 Received STALLed Interrupt Enable OVERFIES 5 Overflow Interrupt Enable NAKEDES 4 NAKed Interrupt Enable PERRES 3 Pipe Error Interrupt Enable TXSTPES 2 Transmitted SETUP Interrupt Enable UNDERFIES 2 Underflow Interrupt Enable TXOUTES 1 Transmitted OUT Data Interrupt Enable RXINES 0 Received IN Data Interrupt Enable
USBHS_HSTPIPIDR0Host Pipe Disable Register
Address 0x40038620
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does PFREEZEC 17 Pipe Freeze Disable PDISHDMAC 16 Pipe Interrupts Disable HDMA Request Disable FIFOCONC 14 FIFO Control Disable NBUSYBKEC 12 Number of Busy Banks Disable SHORTPACKETIEC 7 Short Packet Interrupt Disable CRCERREC 6 CRC Error Interrupt Disable RXSTALLDEC 6 Received STALLed Interrupt Disable OVERFIEC 5 Overflow Interrupt Disable NAKEDEC 4 NAKed Interrupt Disable PERREC 3 Pipe Error Interrupt Disable TXSTPEC 2 Transmitted SETUP Interrupt Disable UNDERFIEC 2 Underflow Interrupt Disable TXOUTEC 1 Transmitted OUT Data Interrupt Disable RXINEC 0 Received IN Data Interrupt Disable
USBHS_HSTPIPIDR1Host Pipe Disable Register
Address 0x40038624
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does PFREEZEC 17 Pipe Freeze Disable PDISHDMAC 16 Pipe Interrupts Disable HDMA Request Disable FIFOCONC 14 FIFO Control Disable NBUSYBKEC 12 Number of Busy Banks Disable SHORTPACKETIEC 7 Short Packet Interrupt Disable CRCERREC 6 CRC Error Interrupt Disable RXSTALLDEC 6 Received STALLed Interrupt Disable OVERFIEC 5 Overflow Interrupt Disable NAKEDEC 4 NAKed Interrupt Disable PERREC 3 Pipe Error Interrupt Disable TXSTPEC 2 Transmitted SETUP Interrupt Disable UNDERFIEC 2 Underflow Interrupt Disable TXOUTEC 1 Transmitted OUT Data Interrupt Disable RXINEC 0 Received IN Data Interrupt Disable
USBHS_HSTPIPIDR2Host Pipe Disable Register
Address 0x40038628
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does PFREEZEC 17 Pipe Freeze Disable PDISHDMAC 16 Pipe Interrupts Disable HDMA Request Disable FIFOCONC 14 FIFO Control Disable NBUSYBKEC 12 Number of Busy Banks Disable SHORTPACKETIEC 7 Short Packet Interrupt Disable CRCERREC 6 CRC Error Interrupt Disable RXSTALLDEC 6 Received STALLed Interrupt Disable OVERFIEC 5 Overflow Interrupt Disable NAKEDEC 4 NAKed Interrupt Disable PERREC 3 Pipe Error Interrupt Disable TXSTPEC 2 Transmitted SETUP Interrupt Disable UNDERFIEC 2 Underflow Interrupt Disable TXOUTEC 1 Transmitted OUT Data Interrupt Disable RXINEC 0 Received IN Data Interrupt Disable
USBHS_HSTPIPIDR3Host Pipe Disable Register
Address 0x4003862C
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does PFREEZEC 17 Pipe Freeze Disable PDISHDMAC 16 Pipe Interrupts Disable HDMA Request Disable FIFOCONC 14 FIFO Control Disable NBUSYBKEC 12 Number of Busy Banks Disable SHORTPACKETIEC 7 Short Packet Interrupt Disable CRCERREC 6 CRC Error Interrupt Disable RXSTALLDEC 6 Received STALLed Interrupt Disable OVERFIEC 5 Overflow Interrupt Disable NAKEDEC 4 NAKed Interrupt Disable PERREC 3 Pipe Error Interrupt Disable TXSTPEC 2 Transmitted SETUP Interrupt Disable UNDERFIEC 2 Underflow Interrupt Disable TXOUTEC 1 Transmitted OUT Data Interrupt Disable RXINEC 0 Received IN Data Interrupt Disable
USBHS_HSTPIPIDR4Host Pipe Disable Register
Address 0x40038630
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does PFREEZEC 17 Pipe Freeze Disable PDISHDMAC 16 Pipe Interrupts Disable HDMA Request Disable FIFOCONC 14 FIFO Control Disable NBUSYBKEC 12 Number of Busy Banks Disable SHORTPACKETIEC 7 Short Packet Interrupt Disable CRCERREC 6 CRC Error Interrupt Disable RXSTALLDEC 6 Received STALLed Interrupt Disable OVERFIEC 5 Overflow Interrupt Disable NAKEDEC 4 NAKed Interrupt Disable PERREC 3 Pipe Error Interrupt Disable TXSTPEC 2 Transmitted SETUP Interrupt Disable UNDERFIEC 2 Underflow Interrupt Disable TXOUTEC 1 Transmitted OUT Data Interrupt Disable RXINEC 0 Received IN Data Interrupt Disable
USBHS_HSTPIPIDR5Host Pipe Disable Register
Address 0x40038634
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does PFREEZEC 17 Pipe Freeze Disable PDISHDMAC 16 Pipe Interrupts Disable HDMA Request Disable FIFOCONC 14 FIFO Control Disable NBUSYBKEC 12 Number of Busy Banks Disable SHORTPACKETIEC 7 Short Packet Interrupt Disable CRCERREC 6 CRC Error Interrupt Disable RXSTALLDEC 6 Received STALLed Interrupt Disable OVERFIEC 5 Overflow Interrupt Disable NAKEDEC 4 NAKed Interrupt Disable PERREC 3 Pipe Error Interrupt Disable TXSTPEC 2 Transmitted SETUP Interrupt Disable UNDERFIEC 2 Underflow Interrupt Disable TXOUTEC 1 Transmitted OUT Data Interrupt Disable RXINEC 0 Received IN Data Interrupt Disable
USBHS_HSTPIPIDR6Host Pipe Disable Register
Address 0x40038638
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does PFREEZEC 17 Pipe Freeze Disable PDISHDMAC 16 Pipe Interrupts Disable HDMA Request Disable FIFOCONC 14 FIFO Control Disable NBUSYBKEC 12 Number of Busy Banks Disable SHORTPACKETIEC 7 Short Packet Interrupt Disable CRCERREC 6 CRC Error Interrupt Disable RXSTALLDEC 6 Received STALLed Interrupt Disable OVERFIEC 5 Overflow Interrupt Disable NAKEDEC 4 NAKed Interrupt Disable PERREC 3 Pipe Error Interrupt Disable TXSTPEC 2 Transmitted SETUP Interrupt Disable UNDERFIEC 2 Underflow Interrupt Disable TXOUTEC 1 Transmitted OUT Data Interrupt Disable RXINEC 0 Received IN Data Interrupt Disable
USBHS_HSTPIPIDR7Host Pipe Disable Register
Address 0x4003863C
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does PFREEZEC 17 Pipe Freeze Disable PDISHDMAC 16 Pipe Interrupts Disable HDMA Request Disable FIFOCONC 14 FIFO Control Disable NBUSYBKEC 12 Number of Busy Banks Disable SHORTPACKETIEC 7 Short Packet Interrupt Disable CRCERREC 6 CRC Error Interrupt Disable RXSTALLDEC 6 Received STALLed Interrupt Disable OVERFIEC 5 Overflow Interrupt Disable NAKEDEC 4 NAKed Interrupt Disable PERREC 3 Pipe Error Interrupt Disable TXSTPEC 2 Transmitted SETUP Interrupt Disable UNDERFIEC 2 Underflow Interrupt Disable TXOUTEC 1 Transmitted OUT Data Interrupt Disable RXINEC 0 Received IN Data Interrupt Disable
USBHS_HSTPIPIDR8Host Pipe Disable Register
Address 0x40038640
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does PFREEZEC 17 Pipe Freeze Disable PDISHDMAC 16 Pipe Interrupts Disable HDMA Request Disable FIFOCONC 14 FIFO Control Disable NBUSYBKEC 12 Number of Busy Banks Disable SHORTPACKETIEC 7 Short Packet Interrupt Disable CRCERREC 6 CRC Error Interrupt Disable RXSTALLDEC 6 Received STALLed Interrupt Disable OVERFIEC 5 Overflow Interrupt Disable NAKEDEC 4 NAKed Interrupt Disable PERREC 3 Pipe Error Interrupt Disable TXSTPEC 2 Transmitted SETUP Interrupt Disable UNDERFIEC 2 Underflow Interrupt Disable TXOUTEC 1 Transmitted OUT Data Interrupt Disable RXINEC 0 Received IN Data Interrupt Disable
USBHS_HSTPIPIDR9Host Pipe Disable Register
Address 0x40038644
Reset 0x00000000
Access write only
Size 32-bit 14 fields
Field Bits What it does PFREEZEC 17 Pipe Freeze Disable PDISHDMAC 16 Pipe Interrupts Disable HDMA Request Disable FIFOCONC 14 FIFO Control Disable NBUSYBKEC 12 Number of Busy Banks Disable SHORTPACKETIEC 7 Short Packet Interrupt Disable CRCERREC 6 CRC Error Interrupt Disable RXSTALLDEC 6 Received STALLed Interrupt Disable OVERFIEC 5 Overflow Interrupt Disable NAKEDEC 4 NAKed Interrupt Disable PERREC 3 Pipe Error Interrupt Disable TXSTPEC 2 Transmitted SETUP Interrupt Disable UNDERFIEC 2 Underflow Interrupt Disable TXOUTEC 1 Transmitted OUT Data Interrupt Disable RXINEC 0 Received IN Data Interrupt Disable
USBHS_HSTPIPINRQ0Host Pipe IN Request Register
Address 0x40038650
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does INMODE 8 IN Request Mode INRQ 7:0 IN Request Number before Freeze
USBHS_HSTPIPINRQ1Host Pipe IN Request Register
Address 0x40038654
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does INMODE 8 IN Request Mode INRQ 7:0 IN Request Number before Freeze
USBHS_HSTPIPINRQ2Host Pipe IN Request Register
Address 0x40038658
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does INMODE 8 IN Request Mode INRQ 7:0 IN Request Number before Freeze
USBHS_HSTPIPINRQ3Host Pipe IN Request Register
Address 0x4003865C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does INMODE 8 IN Request Mode INRQ 7:0 IN Request Number before Freeze
USBHS_HSTPIPINRQ4Host Pipe IN Request Register
Address 0x40038660
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does INMODE 8 IN Request Mode INRQ 7:0 IN Request Number before Freeze
USBHS_HSTPIPINRQ5Host Pipe IN Request Register
Address 0x40038664
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does INMODE 8 IN Request Mode INRQ 7:0 IN Request Number before Freeze
USBHS_HSTPIPINRQ6Host Pipe IN Request Register
Address 0x40038668
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does INMODE 8 IN Request Mode INRQ 7:0 IN Request Number before Freeze
USBHS_HSTPIPINRQ7Host Pipe IN Request Register
Address 0x4003866C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does INMODE 8 IN Request Mode INRQ 7:0 IN Request Number before Freeze
USBHS_HSTPIPINRQ8Host Pipe IN Request Register
Address 0x40038670
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does INMODE 8 IN Request Mode INRQ 7:0 IN Request Number before Freeze
USBHS_HSTPIPINRQ9Host Pipe IN Request Register
Address 0x40038674
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does INMODE 8 IN Request Mode INRQ 7:0 IN Request Number before Freeze
USBHS_HSTPIPERR0Host Pipe Error Register
Address 0x40038680
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does COUNTER 6:5 Error Counter CRC16 4 CRC16 Error TIMEOUT 3 Time-Out Error PID 2 Data PID Error DATAPID 1 Data PID Error DATATGL 0 Data Toggle Error
USBHS_HSTPIPERR1Host Pipe Error Register
Address 0x40038684
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does COUNTER 6:5 Error Counter CRC16 4 CRC16 Error TIMEOUT 3 Time-Out Error PID 2 Data PID Error DATAPID 1 Data PID Error DATATGL 0 Data Toggle Error
USBHS_HSTPIPERR2Host Pipe Error Register
Address 0x40038688
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does COUNTER 6:5 Error Counter CRC16 4 CRC16 Error TIMEOUT 3 Time-Out Error PID 2 Data PID Error DATAPID 1 Data PID Error DATATGL 0 Data Toggle Error
USBHS_HSTPIPERR3Host Pipe Error Register
Address 0x4003868C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does COUNTER 6:5 Error Counter CRC16 4 CRC16 Error TIMEOUT 3 Time-Out Error PID 2 Data PID Error DATAPID 1 Data PID Error DATATGL 0 Data Toggle Error
USBHS_HSTPIPERR4Host Pipe Error Register
Address 0x40038690
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does COUNTER 6:5 Error Counter CRC16 4 CRC16 Error TIMEOUT 3 Time-Out Error PID 2 Data PID Error DATAPID 1 Data PID Error DATATGL 0 Data Toggle Error
USBHS_HSTPIPERR5Host Pipe Error Register
Address 0x40038694
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does COUNTER 6:5 Error Counter CRC16 4 CRC16 Error TIMEOUT 3 Time-Out Error PID 2 Data PID Error DATAPID 1 Data PID Error DATATGL 0 Data Toggle Error
USBHS_HSTPIPERR6Host Pipe Error Register
Address 0x40038698
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does COUNTER 6:5 Error Counter CRC16 4 CRC16 Error TIMEOUT 3 Time-Out Error PID 2 Data PID Error DATAPID 1 Data PID Error DATATGL 0 Data Toggle Error
USBHS_HSTPIPERR7Host Pipe Error Register
Address 0x4003869C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does COUNTER 6:5 Error Counter CRC16 4 CRC16 Error TIMEOUT 3 Time-Out Error PID 2 Data PID Error DATAPID 1 Data PID Error DATATGL 0 Data Toggle Error
USBHS_HSTPIPERR8Host Pipe Error Register
Address 0x400386A0
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does COUNTER 6:5 Error Counter CRC16 4 CRC16 Error TIMEOUT 3 Time-Out Error PID 2 Data PID Error DATAPID 1 Data PID Error DATATGL 0 Data Toggle Error
USBHS_HSTPIPERR9Host Pipe Error Register
Address 0x400386A4
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does COUNTER 6:5 Error Counter CRC16 4 CRC16 Error TIMEOUT 3 Time-Out Error PID 2 Data PID Error DATAPID 1 Data PID Error DATATGL 0 Data Toggle Error
USBHS_HSTDMANXTDSC0Host DMA Channel Next Descriptor Address Register
Address 0x40038710
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT_DSC_ADD 31:0 Next Descriptor Address
USBHS_HSTDMAADDRESS0Host DMA Channel Address Register
Address 0x40038714
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BUFF_ADD 31:0 Buffer Address
USBHS_HSTDMACONTROL0Host DMA Channel Control Register
Address 0x40038718
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does BURST_LCK 7 Burst Lock Enable DESC_LD_IT 6 Descriptor Loaded Interrupt Enable END_BUFFIT 5 End of Buffer Interrupt Enable END_TR_IT 4 End of Transfer Interrupt Enable END_B_EN 3 End of Buffer Enable Control END_TR_EN 2 End of Transfer Enable Control (OUT transfers only) LDNXT_DSC 1 Load Next Channel Transfer Descriptor Enable Command CHANN_ENB 0 Channel Enable Command BUFF_LENGTH 31:16 Buffer Byte Length (Write-only)
USBHS_HSTDMASTATUS0Host DMA Channel Status Register
Address 0x4003871C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does DESC_LDST 6 Descriptor Loaded Status END_BF_ST 5 End of Channel Buffer Status END_TR_ST 4 End of Channel Transfer Status CHANN_ACT 1 Channel Active Status CHANN_ENB 0 Channel Enable Status BUFF_COUNT 31:16 Buffer Byte Count
USBHS_HSTDMANXTDSC1Host DMA Channel Next Descriptor Address Register
Address 0x40038720
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT_DSC_ADD 31:0 Next Descriptor Address
USBHS_HSTDMAADDRESS1Host DMA Channel Address Register
Address 0x40038724
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BUFF_ADD 31:0 Buffer Address
USBHS_HSTDMACONTROL1Host DMA Channel Control Register
Address 0x40038728
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does BURST_LCK 7 Burst Lock Enable DESC_LD_IT 6 Descriptor Loaded Interrupt Enable END_BUFFIT 5 End of Buffer Interrupt Enable END_TR_IT 4 End of Transfer Interrupt Enable END_B_EN 3 End of Buffer Enable Control END_TR_EN 2 End of Transfer Enable Control (OUT transfers only) LDNXT_DSC 1 Load Next Channel Transfer Descriptor Enable Command CHANN_ENB 0 Channel Enable Command BUFF_LENGTH 31:16 Buffer Byte Length (Write-only)
USBHS_HSTDMASTATUS1Host DMA Channel Status Register
Address 0x4003872C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does DESC_LDST 6 Descriptor Loaded Status END_BF_ST 5 End of Channel Buffer Status END_TR_ST 4 End of Channel Transfer Status CHANN_ACT 1 Channel Active Status CHANN_ENB 0 Channel Enable Status BUFF_COUNT 31:16 Buffer Byte Count
USBHS_HSTDMANXTDSC2Host DMA Channel Next Descriptor Address Register
Address 0x40038730
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT_DSC_ADD 31:0 Next Descriptor Address
USBHS_HSTDMAADDRESS2Host DMA Channel Address Register
Address 0x40038734
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BUFF_ADD 31:0 Buffer Address
USBHS_HSTDMACONTROL2Host DMA Channel Control Register
Address 0x40038738
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does BURST_LCK 7 Burst Lock Enable DESC_LD_IT 6 Descriptor Loaded Interrupt Enable END_BUFFIT 5 End of Buffer Interrupt Enable END_TR_IT 4 End of Transfer Interrupt Enable END_B_EN 3 End of Buffer Enable Control END_TR_EN 2 End of Transfer Enable Control (OUT transfers only) LDNXT_DSC 1 Load Next Channel Transfer Descriptor Enable Command CHANN_ENB 0 Channel Enable Command BUFF_LENGTH 31:16 Buffer Byte Length (Write-only)
USBHS_HSTDMASTATUS2Host DMA Channel Status Register
Address 0x4003873C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does DESC_LDST 6 Descriptor Loaded Status END_BF_ST 5 End of Channel Buffer Status END_TR_ST 4 End of Channel Transfer Status CHANN_ACT 1 Channel Active Status CHANN_ENB 0 Channel Enable Status BUFF_COUNT 31:16 Buffer Byte Count
USBHS_HSTDMANXTDSC3Host DMA Channel Next Descriptor Address Register
Address 0x40038740
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT_DSC_ADD 31:0 Next Descriptor Address
USBHS_HSTDMAADDRESS3Host DMA Channel Address Register
Address 0x40038744
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BUFF_ADD 31:0 Buffer Address
USBHS_HSTDMACONTROL3Host DMA Channel Control Register
Address 0x40038748
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does BURST_LCK 7 Burst Lock Enable DESC_LD_IT 6 Descriptor Loaded Interrupt Enable END_BUFFIT 5 End of Buffer Interrupt Enable END_TR_IT 4 End of Transfer Interrupt Enable END_B_EN 3 End of Buffer Enable Control END_TR_EN 2 End of Transfer Enable Control (OUT transfers only) LDNXT_DSC 1 Load Next Channel Transfer Descriptor Enable Command CHANN_ENB 0 Channel Enable Command BUFF_LENGTH 31:16 Buffer Byte Length (Write-only)
USBHS_HSTDMASTATUS3Host DMA Channel Status Register
Address 0x4003874C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does DESC_LDST 6 Descriptor Loaded Status END_BF_ST 5 End of Channel Buffer Status END_TR_ST 4 End of Channel Transfer Status CHANN_ACT 1 Channel Active Status CHANN_ENB 0 Channel Enable Status BUFF_COUNT 31:16 Buffer Byte Count
USBHS_HSTDMANXTDSC4Host DMA Channel Next Descriptor Address Register
Address 0x40038750
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT_DSC_ADD 31:0 Next Descriptor Address
USBHS_HSTDMAADDRESS4Host DMA Channel Address Register
Address 0x40038754
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BUFF_ADD 31:0 Buffer Address
USBHS_HSTDMACONTROL4Host DMA Channel Control Register
Address 0x40038758
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does BURST_LCK 7 Burst Lock Enable DESC_LD_IT 6 Descriptor Loaded Interrupt Enable END_BUFFIT 5 End of Buffer Interrupt Enable END_TR_IT 4 End of Transfer Interrupt Enable END_B_EN 3 End of Buffer Enable Control END_TR_EN 2 End of Transfer Enable Control (OUT transfers only) LDNXT_DSC 1 Load Next Channel Transfer Descriptor Enable Command CHANN_ENB 0 Channel Enable Command BUFF_LENGTH 31:16 Buffer Byte Length (Write-only)
USBHS_HSTDMASTATUS4Host DMA Channel Status Register
Address 0x4003875C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does DESC_LDST 6 Descriptor Loaded Status END_BF_ST 5 End of Channel Buffer Status END_TR_ST 4 End of Channel Transfer Status CHANN_ACT 1 Channel Active Status CHANN_ENB 0 Channel Enable Status BUFF_COUNT 31:16 Buffer Byte Count
USBHS_HSTDMANXTDSC5Host DMA Channel Next Descriptor Address Register
Address 0x40038760
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT_DSC_ADD 31:0 Next Descriptor Address
USBHS_HSTDMAADDRESS5Host DMA Channel Address Register
Address 0x40038764
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BUFF_ADD 31:0 Buffer Address
USBHS_HSTDMACONTROL5Host DMA Channel Control Register
Address 0x40038768
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does BURST_LCK 7 Burst Lock Enable DESC_LD_IT 6 Descriptor Loaded Interrupt Enable END_BUFFIT 5 End of Buffer Interrupt Enable END_TR_IT 4 End of Transfer Interrupt Enable END_B_EN 3 End of Buffer Enable Control END_TR_EN 2 End of Transfer Enable Control (OUT transfers only) LDNXT_DSC 1 Load Next Channel Transfer Descriptor Enable Command CHANN_ENB 0 Channel Enable Command BUFF_LENGTH 31:16 Buffer Byte Length (Write-only)
USBHS_HSTDMASTATUS5Host DMA Channel Status Register
Address 0x4003876C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does DESC_LDST 6 Descriptor Loaded Status END_BF_ST 5 End of Channel Buffer Status END_TR_ST 4 End of Channel Transfer Status CHANN_ACT 1 Channel Active Status CHANN_ENB 0 Channel Enable Status BUFF_COUNT 31:16 Buffer Byte Count
USBHS_HSTDMANXTDSC6Host DMA Channel Next Descriptor Address Register
Address 0x40038770
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT_DSC_ADD 31:0 Next Descriptor Address
USBHS_HSTDMAADDRESS6Host DMA Channel Address Register
Address 0x40038774
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BUFF_ADD 31:0 Buffer Address
USBHS_HSTDMACONTROL6Host DMA Channel Control Register
Address 0x40038778
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does BURST_LCK 7 Burst Lock Enable DESC_LD_IT 6 Descriptor Loaded Interrupt Enable END_BUFFIT 5 End of Buffer Interrupt Enable END_TR_IT 4 End of Transfer Interrupt Enable END_B_EN 3 End of Buffer Enable Control END_TR_EN 2 End of Transfer Enable Control (OUT transfers only) LDNXT_DSC 1 Load Next Channel Transfer Descriptor Enable Command CHANN_ENB 0 Channel Enable Command BUFF_LENGTH 31:16 Buffer Byte Length (Write-only)
USBHS_HSTDMASTATUS6Host DMA Channel Status Register
Address 0x4003877C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does DESC_LDST 6 Descriptor Loaded Status END_BF_ST 5 End of Channel Buffer Status END_TR_ST 4 End of Channel Transfer Status CHANN_ACT 1 Channel Active Status CHANN_ENB 0 Channel Enable Status BUFF_COUNT 31:16 Buffer Byte Count
USBHS_CTRLGeneral Control Register
Address 0x40038800
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does UIMOD 25 USBHS Mode0 The module is in USB Host mode.1 The module is in USB Device mode. UID 24 UID Pin Enable USBE 15 USBHS Enable FRZCLK 14 Freeze USB Clock VBUSHWC 8 VBUS Hardware Control RDERRE 4 Remote Device Connection Error Interrupt Enable
USBHS_SRGeneral Status Register
Address 0x40038804
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does CLKUSABLE 14 UTMI Clock Usable SPEED 13:12 Speed Status (Device mode only)0 Full-Speed mode1 High-Speed mode2 Low-Speed mode RDERRI 4 Remote Device Connection Error Interrupt (Host mode only)
USBHS_SCRGeneral Status Clear Register
Address 0x40038808
Reset 0x00000000
Access write only
Size 32-bit 1 field
Field Bits What it does RDERRIC 4 Remote Device Connection Error Interrupt Clear
USBHS_SFRGeneral Status Set Register
Address 0x4003880C
Reset 0x00000000
Access write only
Size 32-bit 2 fields
Field Bits What it does VBUSRQS 9 VBUS Request Set RDERRIS 4 Remote Device Connection Error Interrupt Set
BETA