ATSAMV71J19B XDMAC registers The 353 registers of XDMAC (Extensible DMA Controller), from 0x40078000, with their reset value and every field. The ATSAMV71J19B has 2417 registers in 55 peripherals, one page each.
XDMAC Extensible DMA Controller XDMAC_GTYPEGlobal Type Register
Address 0x40078000
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does NB_REQ 22:16 Number of Peripheral Requests Minus One FIFO_SZ 15:5 Number of Bytes NB_CH 4:0 Number of Channels Minus One
XDMAC_GCFGGlobal Configuration Register
Address 0x40078004
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does BXKBEN 8 Boundary X Kilobyte Enable CGDISIF 3 Bus Interface Clock Gating Disable CGDISFIFO 2 FIFO Clock Gating Disable CGDISPIPE 1 Pipeline Clock Gating Disable CGDISREG 0 Configuration Registers Clock Gating Disable
XDMAC_GWACGlobal Weighted Arbiter Configuration Register
Address 0x40078008
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does PW3 15:12 Pool Weight 3 PW2 11:8 Pool Weight 2 PW1 7:4 Pool Weight 1 PW0 3:0 Pool Weight 0
XDMAC_GIEGlobal Interrupt Enable Register
Address 0x4007800C
Reset 0x00000000
Access write only
Size 32-bit 24 fields
Field Bits What it does IE23 23 XDMAC Channel 23 Interrupt Enable Bit IE22 22 XDMAC Channel 22 Interrupt Enable Bit IE21 21 XDMAC Channel 21 Interrupt Enable Bit IE20 20 XDMAC Channel 20 Interrupt Enable Bit IE19 19 XDMAC Channel 19 Interrupt Enable Bit IE18 18 XDMAC Channel 18 Interrupt Enable Bit IE17 17 XDMAC Channel 17 Interrupt Enable Bit IE16 16 XDMAC Channel 16 Interrupt Enable Bit IE15 15 XDMAC Channel 15 Interrupt Enable Bit IE14 14 XDMAC Channel 14 Interrupt Enable Bit IE13 13 XDMAC Channel 13 Interrupt Enable Bit IE12 12 XDMAC Channel 12 Interrupt Enable Bit IE11 11 XDMAC Channel 11 Interrupt Enable Bit IE10 10 XDMAC Channel 10 Interrupt Enable Bit IE9 9 XDMAC Channel 9 Interrupt Enable Bit IE8 8 XDMAC Channel 8 Interrupt Enable Bit IE7 7 XDMAC Channel 7 Interrupt Enable Bit IE6 6 XDMAC Channel 6 Interrupt Enable Bit IE5 5 XDMAC Channel 5 Interrupt Enable Bit IE4 4 XDMAC Channel 4 Interrupt Enable Bit IE3 3 XDMAC Channel 3 Interrupt Enable Bit IE2 2 XDMAC Channel 2 Interrupt Enable Bit IE1 1 XDMAC Channel 1 Interrupt Enable Bit IE0 0 XDMAC Channel 0 Interrupt Enable Bit
XDMAC_GIDGlobal Interrupt Disable Register
Address 0x40078010
Reset 0x00000000
Access write only
Size 32-bit 24 fields
Field Bits What it does ID23 23 XDMAC Channel 23 Interrupt Disable Bit ID22 22 XDMAC Channel 22 Interrupt Disable Bit ID21 21 XDMAC Channel 21 Interrupt Disable Bit ID20 20 XDMAC Channel 20 Interrupt Disable Bit ID19 19 XDMAC Channel 19 Interrupt Disable Bit ID18 18 XDMAC Channel 18 Interrupt Disable Bit ID17 17 XDMAC Channel 17 Interrupt Disable Bit ID16 16 XDMAC Channel 16 Interrupt Disable Bit ID15 15 XDMAC Channel 15 Interrupt Disable Bit ID14 14 XDMAC Channel 14 Interrupt Disable Bit ID13 13 XDMAC Channel 13 Interrupt Disable Bit ID12 12 XDMAC Channel 12 Interrupt Disable Bit ID11 11 XDMAC Channel 11 Interrupt Disable Bit ID10 10 XDMAC Channel 10 Interrupt Disable Bit ID9 9 XDMAC Channel 9 Interrupt Disable Bit ID8 8 XDMAC Channel 8 Interrupt Disable Bit ID7 7 XDMAC Channel 7 Interrupt Disable Bit ID6 6 XDMAC Channel 6 Interrupt Disable Bit ID5 5 XDMAC Channel 5 Interrupt Disable Bit ID4 4 XDMAC Channel 4 Interrupt Disable Bit ID3 3 XDMAC Channel 3 Interrupt Disable Bit ID2 2 XDMAC Channel 2 Interrupt Disable Bit ID1 1 XDMAC Channel 1 Interrupt Disable Bit ID0 0 XDMAC Channel 0 Interrupt Disable Bit
XDMAC_GIMGlobal Interrupt Mask Register
Address 0x40078014
Reset 0x00000000
Access read only
Size 32-bit 24 fields
Field Bits What it does IM23 23 XDMAC Channel 23 Interrupt Mask Bit IM22 22 XDMAC Channel 22 Interrupt Mask Bit IM21 21 XDMAC Channel 21 Interrupt Mask Bit IM20 20 XDMAC Channel 20 Interrupt Mask Bit IM19 19 XDMAC Channel 19 Interrupt Mask Bit IM18 18 XDMAC Channel 18 Interrupt Mask Bit IM17 17 XDMAC Channel 17 Interrupt Mask Bit IM16 16 XDMAC Channel 16 Interrupt Mask Bit IM15 15 XDMAC Channel 15 Interrupt Mask Bit IM14 14 XDMAC Channel 14 Interrupt Mask Bit IM13 13 XDMAC Channel 13 Interrupt Mask Bit IM12 12 XDMAC Channel 12 Interrupt Mask Bit IM11 11 XDMAC Channel 11 Interrupt Mask Bit IM10 10 XDMAC Channel 10 Interrupt Mask Bit IM9 9 XDMAC Channel 9 Interrupt Mask Bit IM8 8 XDMAC Channel 8 Interrupt Mask Bit IM7 7 XDMAC Channel 7 Interrupt Mask Bit IM6 6 XDMAC Channel 6 Interrupt Mask Bit IM5 5 XDMAC Channel 5 Interrupt Mask Bit IM4 4 XDMAC Channel 4 Interrupt Mask Bit IM3 3 XDMAC Channel 3 Interrupt Mask Bit IM2 2 XDMAC Channel 2 Interrupt Mask Bit IM1 1 XDMAC Channel 1 Interrupt Mask Bit IM0 0 XDMAC Channel 0 Interrupt Mask Bit
XDMAC_GISGlobal Interrupt Status Register
Address 0x40078018
Reset 0x00000000
Access read only
Size 32-bit 24 fields
Field Bits What it does IS23 23 XDMAC Channel 23 Interrupt Status Bit IS22 22 XDMAC Channel 22 Interrupt Status Bit IS21 21 XDMAC Channel 21 Interrupt Status Bit IS20 20 XDMAC Channel 20 Interrupt Status Bit IS19 19 XDMAC Channel 19 Interrupt Status Bit IS18 18 XDMAC Channel 18 Interrupt Status Bit IS17 17 XDMAC Channel 17 Interrupt Status Bit IS16 16 XDMAC Channel 16 Interrupt Status Bit IS15 15 XDMAC Channel 15 Interrupt Status Bit IS14 14 XDMAC Channel 14 Interrupt Status Bit IS13 13 XDMAC Channel 13 Interrupt Status Bit IS12 12 XDMAC Channel 12 Interrupt Status Bit IS11 11 XDMAC Channel 11 Interrupt Status Bit IS10 10 XDMAC Channel 10 Interrupt Status Bit IS9 9 XDMAC Channel 9 Interrupt Status Bit IS8 8 XDMAC Channel 8 Interrupt Status Bit IS7 7 XDMAC Channel 7 Interrupt Status Bit IS6 6 XDMAC Channel 6 Interrupt Status Bit IS5 5 XDMAC Channel 5 Interrupt Status Bit IS4 4 XDMAC Channel 4 Interrupt Status Bit IS3 3 XDMAC Channel 3 Interrupt Status Bit IS2 2 XDMAC Channel 2 Interrupt Status Bit IS1 1 XDMAC Channel 1 Interrupt Status Bit IS0 0 XDMAC Channel 0 Interrupt Status Bit
XDMAC_GEGlobal Channel Enable Register
Address 0x4007801C
Reset 0x00000000
Access write only
Size 32-bit 24 fields
Field Bits What it does EN23 23 XDMAC Channel 23 Enable Bit EN22 22 XDMAC Channel 22 Enable Bit EN21 21 XDMAC Channel 21 Enable Bit EN20 20 XDMAC Channel 20 Enable Bit EN19 19 XDMAC Channel 19 Enable Bit EN18 18 XDMAC Channel 18 Enable Bit EN17 17 XDMAC Channel 17 Enable Bit EN16 16 XDMAC Channel 16 Enable Bit EN15 15 XDMAC Channel 15 Enable Bit EN14 14 XDMAC Channel 14 Enable Bit EN13 13 XDMAC Channel 13 Enable Bit EN12 12 XDMAC Channel 12 Enable Bit EN11 11 XDMAC Channel 11 Enable Bit EN10 10 XDMAC Channel 10 Enable Bit EN9 9 XDMAC Channel 9 Enable Bit EN8 8 XDMAC Channel 8 Enable Bit EN7 7 XDMAC Channel 7 Enable Bit EN6 6 XDMAC Channel 6 Enable Bit EN5 5 XDMAC Channel 5 Enable Bit EN4 4 XDMAC Channel 4 Enable Bit EN3 3 XDMAC Channel 3 Enable Bit EN2 2 XDMAC Channel 2 Enable Bit EN1 1 XDMAC Channel 1 Enable Bit EN0 0 XDMAC Channel 0 Enable Bit
XDMAC_GDGlobal Channel Disable Register
Address 0x40078020
Reset 0x00000000
Access write only
Size 32-bit 24 fields
Field Bits What it does DI23 23 XDMAC Channel 23 Disable Bit DI22 22 XDMAC Channel 22 Disable Bit DI21 21 XDMAC Channel 21 Disable Bit DI20 20 XDMAC Channel 20 Disable Bit DI19 19 XDMAC Channel 19 Disable Bit DI18 18 XDMAC Channel 18 Disable Bit DI17 17 XDMAC Channel 17 Disable Bit DI16 16 XDMAC Channel 16 Disable Bit DI15 15 XDMAC Channel 15 Disable Bit DI14 14 XDMAC Channel 14 Disable Bit DI13 13 XDMAC Channel 13 Disable Bit DI12 12 XDMAC Channel 12 Disable Bit DI11 11 XDMAC Channel 11 Disable Bit DI10 10 XDMAC Channel 10 Disable Bit DI9 9 XDMAC Channel 9 Disable Bit DI8 8 XDMAC Channel 8 Disable Bit DI7 7 XDMAC Channel 7 Disable Bit DI6 6 XDMAC Channel 6 Disable Bit DI5 5 XDMAC Channel 5 Disable Bit DI4 4 XDMAC Channel 4 Disable Bit DI3 3 XDMAC Channel 3 Disable Bit DI2 2 XDMAC Channel 2 Disable Bit DI1 1 XDMAC Channel 1 Disable Bit DI0 0 XDMAC Channel 0 Disable Bit
XDMAC_GSGlobal Channel Status Register
Address 0x40078024
Reset 0x00000000
Access read only
Size 32-bit 24 fields
Field Bits What it does ST23 23 XDMAC Channel 23 Status Bit ST22 22 XDMAC Channel 22 Status Bit ST21 21 XDMAC Channel 21 Status Bit ST20 20 XDMAC Channel 20 Status Bit ST19 19 XDMAC Channel 19 Status Bit ST18 18 XDMAC Channel 18 Status Bit ST17 17 XDMAC Channel 17 Status Bit ST16 16 XDMAC Channel 16 Status Bit ST15 15 XDMAC Channel 15 Status Bit ST14 14 XDMAC Channel 14 Status Bit ST13 13 XDMAC Channel 13 Status Bit ST12 12 XDMAC Channel 12 Status Bit ST11 11 XDMAC Channel 11 Status Bit ST10 10 XDMAC Channel 10 Status Bit ST9 9 XDMAC Channel 9 Status Bit ST8 8 XDMAC Channel 8 Status Bit ST7 7 XDMAC Channel 7 Status Bit ST6 6 XDMAC Channel 6 Status Bit ST5 5 XDMAC Channel 5 Status Bit ST4 4 XDMAC Channel 4 Status Bit ST3 3 XDMAC Channel 3 Status Bit ST2 2 XDMAC Channel 2 Status Bit ST1 1 XDMAC Channel 1 Status Bit ST0 0 XDMAC Channel 0 Status Bit
XDMAC_GRSGlobal Channel Read Suspend Register
Address 0x40078028
Reset 0x00000000
Access read/write
Size 32-bit 24 fields
Field Bits What it does RS23 23 XDMAC Channel 23 Read Suspend Bit RS22 22 XDMAC Channel 22 Read Suspend Bit RS21 21 XDMAC Channel 21 Read Suspend Bit RS20 20 XDMAC Channel 20 Read Suspend Bit RS19 19 XDMAC Channel 19 Read Suspend Bit RS18 18 XDMAC Channel 18 Read Suspend Bit RS17 17 XDMAC Channel 17 Read Suspend Bit RS16 16 XDMAC Channel 16 Read Suspend Bit RS15 15 XDMAC Channel 15 Read Suspend Bit RS14 14 XDMAC Channel 14 Read Suspend Bit RS13 13 XDMAC Channel 13 Read Suspend Bit RS12 12 XDMAC Channel 12 Read Suspend Bit RS11 11 XDMAC Channel 11 Read Suspend Bit RS10 10 XDMAC Channel 10 Read Suspend Bit RS9 9 XDMAC Channel 9 Read Suspend Bit RS8 8 XDMAC Channel 8 Read Suspend Bit RS7 7 XDMAC Channel 7 Read Suspend Bit RS6 6 XDMAC Channel 6 Read Suspend Bit RS5 5 XDMAC Channel 5 Read Suspend Bit RS4 4 XDMAC Channel 4 Read Suspend Bit RS3 3 XDMAC Channel 3 Read Suspend Bit RS2 2 XDMAC Channel 2 Read Suspend Bit RS1 1 XDMAC Channel 1 Read Suspend Bit RS0 0 XDMAC Channel 0 Read Suspend Bit
XDMAC_GWSGlobal Channel Write Suspend Register
Address 0x4007802C
Reset 0x00000000
Access read/write
Size 32-bit 24 fields
Field Bits What it does WS23 23 XDMAC Channel 23 Write Suspend Bit WS22 22 XDMAC Channel 22 Write Suspend Bit WS21 21 XDMAC Channel 21 Write Suspend Bit WS20 20 XDMAC Channel 20 Write Suspend Bit WS19 19 XDMAC Channel 19 Write Suspend Bit WS18 18 XDMAC Channel 18 Write Suspend Bit WS17 17 XDMAC Channel 17 Write Suspend Bit WS16 16 XDMAC Channel 16 Write Suspend Bit WS15 15 XDMAC Channel 15 Write Suspend Bit WS14 14 XDMAC Channel 14 Write Suspend Bit WS13 13 XDMAC Channel 13 Write Suspend Bit WS12 12 XDMAC Channel 12 Write Suspend Bit WS11 11 XDMAC Channel 11 Write Suspend Bit WS10 10 XDMAC Channel 10 Write Suspend Bit WS9 9 XDMAC Channel 9 Write Suspend Bit WS8 8 XDMAC Channel 8 Write Suspend Bit WS7 7 XDMAC Channel 7 Write Suspend Bit WS6 6 XDMAC Channel 6 Write Suspend Bit WS5 5 XDMAC Channel 5 Write Suspend Bit WS4 4 XDMAC Channel 4 Write Suspend Bit WS3 3 XDMAC Channel 3 Write Suspend Bit WS2 2 XDMAC Channel 2 Write Suspend Bit WS1 1 XDMAC Channel 1 Write Suspend Bit WS0 0 XDMAC Channel 0 Write Suspend Bit
XDMAC_GRWSGlobal Channel Read Write Suspend Register
Address 0x40078030
Reset 0x00000000
Access write only
Size 32-bit 24 fields
Field Bits What it does RWS23 23 XDMAC Channel 23 Read Write Suspend Bit RWS22 22 XDMAC Channel 22 Read Write Suspend Bit RWS21 21 XDMAC Channel 21 Read Write Suspend Bit RWS20 20 XDMAC Channel 20 Read Write Suspend Bit RWS19 19 XDMAC Channel 19 Read Write Suspend Bit RWS18 18 XDMAC Channel 18 Read Write Suspend Bit RWS17 17 XDMAC Channel 17 Read Write Suspend Bit RWS16 16 XDMAC Channel 16 Read Write Suspend Bit RWS15 15 XDMAC Channel 15 Read Write Suspend Bit RWS14 14 XDMAC Channel 14 Read Write Suspend Bit RWS13 13 XDMAC Channel 13 Read Write Suspend Bit RWS12 12 XDMAC Channel 12 Read Write Suspend Bit RWS11 11 XDMAC Channel 11 Read Write Suspend Bit RWS10 10 XDMAC Channel 10 Read Write Suspend Bit RWS9 9 XDMAC Channel 9 Read Write Suspend Bit RWS8 8 XDMAC Channel 8 Read Write Suspend Bit RWS7 7 XDMAC Channel 7 Read Write Suspend Bit RWS6 6 XDMAC Channel 6 Read Write Suspend Bit RWS5 5 XDMAC Channel 5 Read Write Suspend Bit RWS4 4 XDMAC Channel 4 Read Write Suspend Bit RWS3 3 XDMAC Channel 3 Read Write Suspend Bit RWS2 2 XDMAC Channel 2 Read Write Suspend Bit RWS1 1 XDMAC Channel 1 Read Write Suspend Bit RWS0 0 XDMAC Channel 0 Read Write Suspend Bit
XDMAC_GRWRGlobal Channel Read Write Resume Register
Address 0x40078034
Reset 0x00000000
Access write only
Size 32-bit 24 fields
Field Bits What it does RWR23 23 XDMAC Channel 23 Read Write Resume Bit RWR22 22 XDMAC Channel 22 Read Write Resume Bit RWR21 21 XDMAC Channel 21 Read Write Resume Bit RWR20 20 XDMAC Channel 20 Read Write Resume Bit RWR19 19 XDMAC Channel 19 Read Write Resume Bit RWR18 18 XDMAC Channel 18 Read Write Resume Bit RWR17 17 XDMAC Channel 17 Read Write Resume Bit RWR16 16 XDMAC Channel 16 Read Write Resume Bit RWR15 15 XDMAC Channel 15 Read Write Resume Bit RWR14 14 XDMAC Channel 14 Read Write Resume Bit RWR13 13 XDMAC Channel 13 Read Write Resume Bit RWR12 12 XDMAC Channel 12 Read Write Resume Bit RWR11 11 XDMAC Channel 11 Read Write Resume Bit RWR10 10 XDMAC Channel 10 Read Write Resume Bit RWR9 9 XDMAC Channel 9 Read Write Resume Bit RWR8 8 XDMAC Channel 8 Read Write Resume Bit RWR7 7 XDMAC Channel 7 Read Write Resume Bit RWR6 6 XDMAC Channel 6 Read Write Resume Bit RWR5 5 XDMAC Channel 5 Read Write Resume Bit RWR4 4 XDMAC Channel 4 Read Write Resume Bit RWR3 3 XDMAC Channel 3 Read Write Resume Bit RWR2 2 XDMAC Channel 2 Read Write Resume Bit RWR1 1 XDMAC Channel 1 Read Write Resume Bit RWR0 0 XDMAC Channel 0 Read Write Resume Bit
XDMAC_GSWRGlobal Channel Software Request Register
Address 0x40078038
Reset 0x00000000
Access write only
Size 32-bit 24 fields
Field Bits What it does SWREQ23 23 XDMAC Channel 23 Software Request Bit SWREQ22 22 XDMAC Channel 22 Software Request Bit SWREQ21 21 XDMAC Channel 21 Software Request Bit SWREQ20 20 XDMAC Channel 20 Software Request Bit SWREQ19 19 XDMAC Channel 19 Software Request Bit SWREQ18 18 XDMAC Channel 18 Software Request Bit SWREQ17 17 XDMAC Channel 17 Software Request Bit SWREQ16 16 XDMAC Channel 16 Software Request Bit SWREQ15 15 XDMAC Channel 15 Software Request Bit SWREQ14 14 XDMAC Channel 14 Software Request Bit SWREQ13 13 XDMAC Channel 13 Software Request Bit SWREQ12 12 XDMAC Channel 12 Software Request Bit SWREQ11 11 XDMAC Channel 11 Software Request Bit SWREQ10 10 XDMAC Channel 10 Software Request Bit SWREQ9 9 XDMAC Channel 9 Software Request Bit SWREQ8 8 XDMAC Channel 8 Software Request Bit SWREQ7 7 XDMAC Channel 7 Software Request Bit SWREQ6 6 XDMAC Channel 6 Software Request Bit SWREQ5 5 XDMAC Channel 5 Software Request Bit SWREQ4 4 XDMAC Channel 4 Software Request Bit SWREQ3 3 XDMAC Channel 3 Software Request Bit SWREQ2 2 XDMAC Channel 2 Software Request Bit SWREQ1 1 XDMAC Channel 1 Software Request Bit SWREQ0 0 XDMAC Channel 0 Software Request Bit
XDMAC_GSWSGlobal Channel Software Request Status Register
Address 0x4007803C
Reset 0x00000000
Access read only
Size 32-bit 24 fields
Field Bits What it does SWRS23 23 XDMAC Channel 23 Software Request Status Bit SWRS22 22 XDMAC Channel 22 Software Request Status Bit SWRS21 21 XDMAC Channel 21 Software Request Status Bit SWRS20 20 XDMAC Channel 20 Software Request Status Bit SWRS19 19 XDMAC Channel 19 Software Request Status Bit SWRS18 18 XDMAC Channel 18 Software Request Status Bit SWRS17 17 XDMAC Channel 17 Software Request Status Bit SWRS16 16 XDMAC Channel 16 Software Request Status Bit SWRS15 15 XDMAC Channel 15 Software Request Status Bit SWRS14 14 XDMAC Channel 14 Software Request Status Bit SWRS13 13 XDMAC Channel 13 Software Request Status Bit SWRS12 12 XDMAC Channel 12 Software Request Status Bit SWRS11 11 XDMAC Channel 11 Software Request Status Bit SWRS10 10 XDMAC Channel 10 Software Request Status Bit SWRS9 9 XDMAC Channel 9 Software Request Status Bit SWRS8 8 XDMAC Channel 8 Software Request Status Bit SWRS7 7 XDMAC Channel 7 Software Request Status Bit SWRS6 6 XDMAC Channel 6 Software Request Status Bit SWRS5 5 XDMAC Channel 5 Software Request Status Bit SWRS4 4 XDMAC Channel 4 Software Request Status Bit SWRS3 3 XDMAC Channel 3 Software Request Status Bit SWRS2 2 XDMAC Channel 2 Software Request Status Bit SWRS1 1 XDMAC Channel 1 Software Request Status Bit SWRS0 0 XDMAC Channel 0 Software Request Status Bit
XDMAC_GSWFGlobal Channel Software Flush Request Register
Address 0x40078040
Reset 0x00000000
Access write only
Size 32-bit 24 fields
Field Bits What it does SWF23 23 XDMAC Channel 23 Software Flush Request Bit SWF22 22 XDMAC Channel 22 Software Flush Request Bit SWF21 21 XDMAC Channel 21 Software Flush Request Bit SWF20 20 XDMAC Channel 20 Software Flush Request Bit SWF19 19 XDMAC Channel 19 Software Flush Request Bit SWF18 18 XDMAC Channel 18 Software Flush Request Bit SWF17 17 XDMAC Channel 17 Software Flush Request Bit SWF16 16 XDMAC Channel 16 Software Flush Request Bit SWF15 15 XDMAC Channel 15 Software Flush Request Bit SWF14 14 XDMAC Channel 14 Software Flush Request Bit SWF13 13 XDMAC Channel 13 Software Flush Request Bit SWF12 12 XDMAC Channel 12 Software Flush Request Bit SWF11 11 XDMAC Channel 11 Software Flush Request Bit SWF10 10 XDMAC Channel 10 Software Flush Request Bit SWF9 9 XDMAC Channel 9 Software Flush Request Bit SWF8 8 XDMAC Channel 8 Software Flush Request Bit SWF7 7 XDMAC Channel 7 Software Flush Request Bit SWF6 6 XDMAC Channel 6 Software Flush Request Bit SWF5 5 XDMAC Channel 5 Software Flush Request Bit SWF4 4 XDMAC Channel 4 Software Flush Request Bit SWF3 3 XDMAC Channel 3 Software Flush Request Bit SWF2 2 XDMAC Channel 2 Software Flush Request Bit SWF1 1 XDMAC Channel 1 Software Flush Request Bit SWF0 0 XDMAC Channel 0 Software Flush Request Bit
XDMAC_CHID0.XDMAC_CIEChannel Interrupt Enable Register
Address 0x40078050
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID0.XDMAC_CIDChannel Interrupt Disable Register
Address 0x40078054
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID0.XDMAC_CIMChannel Interrupt Mask Register
Address 0x40078058
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID0.XDMAC_CISChannel Interrupt Status Register
Address 0x4007805C
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID0.XDMAC_CSAChannel Source Address Register
Address 0x40078060
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID0.XDMAC_CDAChannel Destination Address Register
Address 0x40078064
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID0.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x40078068
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID0.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x4007806C
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID0.XDMAC_CUBCChannel Microblock Control Register
Address 0x40078070
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID0.XDMAC_CBCChannel Block Control Register
Address 0x40078074
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID0.XDMAC_CCChannel Configuration Register
Address 0x40078078
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID0.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x4007807C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID0.XDMAC_CSUSChannel Source Microblock Stride
Address 0x40078080
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID0.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x40078084
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID1.XDMAC_CIEChannel Interrupt Enable Register
Address 0x40078090
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID1.XDMAC_CIDChannel Interrupt Disable Register
Address 0x40078094
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID1.XDMAC_CIMChannel Interrupt Mask Register
Address 0x40078098
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID1.XDMAC_CISChannel Interrupt Status Register
Address 0x4007809C
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID1.XDMAC_CSAChannel Source Address Register
Address 0x400780A0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID1.XDMAC_CDAChannel Destination Address Register
Address 0x400780A4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID1.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x400780A8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID1.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x400780AC
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID1.XDMAC_CUBCChannel Microblock Control Register
Address 0x400780B0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID1.XDMAC_CBCChannel Block Control Register
Address 0x400780B4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID1.XDMAC_CCChannel Configuration Register
Address 0x400780B8
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID1.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x400780BC
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID1.XDMAC_CSUSChannel Source Microblock Stride
Address 0x400780C0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID1.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x400780C4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID2.XDMAC_CIEChannel Interrupt Enable Register
Address 0x400780D0
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID2.XDMAC_CIDChannel Interrupt Disable Register
Address 0x400780D4
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID2.XDMAC_CIMChannel Interrupt Mask Register
Address 0x400780D8
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID2.XDMAC_CISChannel Interrupt Status Register
Address 0x400780DC
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID2.XDMAC_CSAChannel Source Address Register
Address 0x400780E0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID2.XDMAC_CDAChannel Destination Address Register
Address 0x400780E4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID2.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x400780E8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID2.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x400780EC
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID2.XDMAC_CUBCChannel Microblock Control Register
Address 0x400780F0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID2.XDMAC_CBCChannel Block Control Register
Address 0x400780F4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID2.XDMAC_CCChannel Configuration Register
Address 0x400780F8
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID2.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x400780FC
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID2.XDMAC_CSUSChannel Source Microblock Stride
Address 0x40078100
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID2.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x40078104
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID3.XDMAC_CIEChannel Interrupt Enable Register
Address 0x40078110
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID3.XDMAC_CIDChannel Interrupt Disable Register
Address 0x40078114
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID3.XDMAC_CIMChannel Interrupt Mask Register
Address 0x40078118
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID3.XDMAC_CISChannel Interrupt Status Register
Address 0x4007811C
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID3.XDMAC_CSAChannel Source Address Register
Address 0x40078120
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID3.XDMAC_CDAChannel Destination Address Register
Address 0x40078124
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID3.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x40078128
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID3.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x4007812C
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID3.XDMAC_CUBCChannel Microblock Control Register
Address 0x40078130
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID3.XDMAC_CBCChannel Block Control Register
Address 0x40078134
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID3.XDMAC_CCChannel Configuration Register
Address 0x40078138
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID3.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x4007813C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID3.XDMAC_CSUSChannel Source Microblock Stride
Address 0x40078140
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID3.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x40078144
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID4.XDMAC_CIEChannel Interrupt Enable Register
Address 0x40078150
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID4.XDMAC_CIDChannel Interrupt Disable Register
Address 0x40078154
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID4.XDMAC_CIMChannel Interrupt Mask Register
Address 0x40078158
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID4.XDMAC_CISChannel Interrupt Status Register
Address 0x4007815C
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID4.XDMAC_CSAChannel Source Address Register
Address 0x40078160
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID4.XDMAC_CDAChannel Destination Address Register
Address 0x40078164
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID4.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x40078168
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID4.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x4007816C
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID4.XDMAC_CUBCChannel Microblock Control Register
Address 0x40078170
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID4.XDMAC_CBCChannel Block Control Register
Address 0x40078174
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID4.XDMAC_CCChannel Configuration Register
Address 0x40078178
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID4.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x4007817C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID4.XDMAC_CSUSChannel Source Microblock Stride
Address 0x40078180
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID4.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x40078184
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID5.XDMAC_CIEChannel Interrupt Enable Register
Address 0x40078190
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID5.XDMAC_CIDChannel Interrupt Disable Register
Address 0x40078194
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID5.XDMAC_CIMChannel Interrupt Mask Register
Address 0x40078198
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID5.XDMAC_CISChannel Interrupt Status Register
Address 0x4007819C
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID5.XDMAC_CSAChannel Source Address Register
Address 0x400781A0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID5.XDMAC_CDAChannel Destination Address Register
Address 0x400781A4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID5.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x400781A8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID5.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x400781AC
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID5.XDMAC_CUBCChannel Microblock Control Register
Address 0x400781B0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID5.XDMAC_CBCChannel Block Control Register
Address 0x400781B4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID5.XDMAC_CCChannel Configuration Register
Address 0x400781B8
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID5.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x400781BC
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID5.XDMAC_CSUSChannel Source Microblock Stride
Address 0x400781C0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID5.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x400781C4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID6.XDMAC_CIEChannel Interrupt Enable Register
Address 0x400781D0
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID6.XDMAC_CIDChannel Interrupt Disable Register
Address 0x400781D4
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID6.XDMAC_CIMChannel Interrupt Mask Register
Address 0x400781D8
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID6.XDMAC_CISChannel Interrupt Status Register
Address 0x400781DC
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID6.XDMAC_CSAChannel Source Address Register
Address 0x400781E0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID6.XDMAC_CDAChannel Destination Address Register
Address 0x400781E4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID6.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x400781E8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID6.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x400781EC
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID6.XDMAC_CUBCChannel Microblock Control Register
Address 0x400781F0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID6.XDMAC_CBCChannel Block Control Register
Address 0x400781F4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID6.XDMAC_CCChannel Configuration Register
Address 0x400781F8
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID6.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x400781FC
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID6.XDMAC_CSUSChannel Source Microblock Stride
Address 0x40078200
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID6.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x40078204
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID7.XDMAC_CIEChannel Interrupt Enable Register
Address 0x40078210
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID7.XDMAC_CIDChannel Interrupt Disable Register
Address 0x40078214
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID7.XDMAC_CIMChannel Interrupt Mask Register
Address 0x40078218
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID7.XDMAC_CISChannel Interrupt Status Register
Address 0x4007821C
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID7.XDMAC_CSAChannel Source Address Register
Address 0x40078220
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID7.XDMAC_CDAChannel Destination Address Register
Address 0x40078224
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID7.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x40078228
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID7.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x4007822C
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID7.XDMAC_CUBCChannel Microblock Control Register
Address 0x40078230
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID7.XDMAC_CBCChannel Block Control Register
Address 0x40078234
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID7.XDMAC_CCChannel Configuration Register
Address 0x40078238
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID7.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x4007823C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID7.XDMAC_CSUSChannel Source Microblock Stride
Address 0x40078240
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID7.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x40078244
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID8.XDMAC_CIEChannel Interrupt Enable Register
Address 0x40078250
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID8.XDMAC_CIDChannel Interrupt Disable Register
Address 0x40078254
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID8.XDMAC_CIMChannel Interrupt Mask Register
Address 0x40078258
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID8.XDMAC_CISChannel Interrupt Status Register
Address 0x4007825C
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID8.XDMAC_CSAChannel Source Address Register
Address 0x40078260
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID8.XDMAC_CDAChannel Destination Address Register
Address 0x40078264
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID8.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x40078268
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID8.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x4007826C
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID8.XDMAC_CUBCChannel Microblock Control Register
Address 0x40078270
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID8.XDMAC_CBCChannel Block Control Register
Address 0x40078274
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID8.XDMAC_CCChannel Configuration Register
Address 0x40078278
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID8.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x4007827C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID8.XDMAC_CSUSChannel Source Microblock Stride
Address 0x40078280
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID8.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x40078284
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID9.XDMAC_CIEChannel Interrupt Enable Register
Address 0x40078290
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID9.XDMAC_CIDChannel Interrupt Disable Register
Address 0x40078294
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID9.XDMAC_CIMChannel Interrupt Mask Register
Address 0x40078298
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID9.XDMAC_CISChannel Interrupt Status Register
Address 0x4007829C
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID9.XDMAC_CSAChannel Source Address Register
Address 0x400782A0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID9.XDMAC_CDAChannel Destination Address Register
Address 0x400782A4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID9.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x400782A8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID9.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x400782AC
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID9.XDMAC_CUBCChannel Microblock Control Register
Address 0x400782B0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID9.XDMAC_CBCChannel Block Control Register
Address 0x400782B4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID9.XDMAC_CCChannel Configuration Register
Address 0x400782B8
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID9.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x400782BC
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID9.XDMAC_CSUSChannel Source Microblock Stride
Address 0x400782C0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID9.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x400782C4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID10.XDMAC_CIEChannel Interrupt Enable Register
Address 0x400782D0
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID10.XDMAC_CIDChannel Interrupt Disable Register
Address 0x400782D4
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID10.XDMAC_CIMChannel Interrupt Mask Register
Address 0x400782D8
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID10.XDMAC_CISChannel Interrupt Status Register
Address 0x400782DC
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID10.XDMAC_CSAChannel Source Address Register
Address 0x400782E0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID10.XDMAC_CDAChannel Destination Address Register
Address 0x400782E4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID10.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x400782E8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID10.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x400782EC
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID10.XDMAC_CUBCChannel Microblock Control Register
Address 0x400782F0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID10.XDMAC_CBCChannel Block Control Register
Address 0x400782F4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID10.XDMAC_CCChannel Configuration Register
Address 0x400782F8
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID10.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x400782FC
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID10.XDMAC_CSUSChannel Source Microblock Stride
Address 0x40078300
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID10.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x40078304
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID11.XDMAC_CIEChannel Interrupt Enable Register
Address 0x40078310
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID11.XDMAC_CIDChannel Interrupt Disable Register
Address 0x40078314
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID11.XDMAC_CIMChannel Interrupt Mask Register
Address 0x40078318
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID11.XDMAC_CISChannel Interrupt Status Register
Address 0x4007831C
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID11.XDMAC_CSAChannel Source Address Register
Address 0x40078320
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID11.XDMAC_CDAChannel Destination Address Register
Address 0x40078324
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID11.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x40078328
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID11.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x4007832C
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID11.XDMAC_CUBCChannel Microblock Control Register
Address 0x40078330
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID11.XDMAC_CBCChannel Block Control Register
Address 0x40078334
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID11.XDMAC_CCChannel Configuration Register
Address 0x40078338
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID11.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x4007833C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID11.XDMAC_CSUSChannel Source Microblock Stride
Address 0x40078340
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID11.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x40078344
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID12.XDMAC_CIEChannel Interrupt Enable Register
Address 0x40078350
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID12.XDMAC_CIDChannel Interrupt Disable Register
Address 0x40078354
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID12.XDMAC_CIMChannel Interrupt Mask Register
Address 0x40078358
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID12.XDMAC_CISChannel Interrupt Status Register
Address 0x4007835C
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID12.XDMAC_CSAChannel Source Address Register
Address 0x40078360
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID12.XDMAC_CDAChannel Destination Address Register
Address 0x40078364
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID12.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x40078368
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID12.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x4007836C
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID12.XDMAC_CUBCChannel Microblock Control Register
Address 0x40078370
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID12.XDMAC_CBCChannel Block Control Register
Address 0x40078374
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID12.XDMAC_CCChannel Configuration Register
Address 0x40078378
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID12.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x4007837C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID12.XDMAC_CSUSChannel Source Microblock Stride
Address 0x40078380
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID12.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x40078384
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID13.XDMAC_CIEChannel Interrupt Enable Register
Address 0x40078390
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID13.XDMAC_CIDChannel Interrupt Disable Register
Address 0x40078394
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID13.XDMAC_CIMChannel Interrupt Mask Register
Address 0x40078398
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID13.XDMAC_CISChannel Interrupt Status Register
Address 0x4007839C
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID13.XDMAC_CSAChannel Source Address Register
Address 0x400783A0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID13.XDMAC_CDAChannel Destination Address Register
Address 0x400783A4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID13.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x400783A8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID13.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x400783AC
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID13.XDMAC_CUBCChannel Microblock Control Register
Address 0x400783B0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID13.XDMAC_CBCChannel Block Control Register
Address 0x400783B4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID13.XDMAC_CCChannel Configuration Register
Address 0x400783B8
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID13.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x400783BC
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID13.XDMAC_CSUSChannel Source Microblock Stride
Address 0x400783C0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID13.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x400783C4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID14.XDMAC_CIEChannel Interrupt Enable Register
Address 0x400783D0
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID14.XDMAC_CIDChannel Interrupt Disable Register
Address 0x400783D4
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID14.XDMAC_CIMChannel Interrupt Mask Register
Address 0x400783D8
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID14.XDMAC_CISChannel Interrupt Status Register
Address 0x400783DC
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID14.XDMAC_CSAChannel Source Address Register
Address 0x400783E0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID14.XDMAC_CDAChannel Destination Address Register
Address 0x400783E4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID14.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x400783E8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID14.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x400783EC
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID14.XDMAC_CUBCChannel Microblock Control Register
Address 0x400783F0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID14.XDMAC_CBCChannel Block Control Register
Address 0x400783F4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID14.XDMAC_CCChannel Configuration Register
Address 0x400783F8
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID14.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x400783FC
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID14.XDMAC_CSUSChannel Source Microblock Stride
Address 0x40078400
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID14.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x40078404
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID15.XDMAC_CIEChannel Interrupt Enable Register
Address 0x40078410
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID15.XDMAC_CIDChannel Interrupt Disable Register
Address 0x40078414
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID15.XDMAC_CIMChannel Interrupt Mask Register
Address 0x40078418
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID15.XDMAC_CISChannel Interrupt Status Register
Address 0x4007841C
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID15.XDMAC_CSAChannel Source Address Register
Address 0x40078420
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID15.XDMAC_CDAChannel Destination Address Register
Address 0x40078424
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID15.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x40078428
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID15.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x4007842C
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID15.XDMAC_CUBCChannel Microblock Control Register
Address 0x40078430
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID15.XDMAC_CBCChannel Block Control Register
Address 0x40078434
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID15.XDMAC_CCChannel Configuration Register
Address 0x40078438
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID15.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x4007843C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID15.XDMAC_CSUSChannel Source Microblock Stride
Address 0x40078440
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID15.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x40078444
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID16.XDMAC_CIEChannel Interrupt Enable Register
Address 0x40078450
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID16.XDMAC_CIDChannel Interrupt Disable Register
Address 0x40078454
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID16.XDMAC_CIMChannel Interrupt Mask Register
Address 0x40078458
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID16.XDMAC_CISChannel Interrupt Status Register
Address 0x4007845C
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID16.XDMAC_CSAChannel Source Address Register
Address 0x40078460
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID16.XDMAC_CDAChannel Destination Address Register
Address 0x40078464
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID16.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x40078468
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID16.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x4007846C
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID16.XDMAC_CUBCChannel Microblock Control Register
Address 0x40078470
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID16.XDMAC_CBCChannel Block Control Register
Address 0x40078474
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID16.XDMAC_CCChannel Configuration Register
Address 0x40078478
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID16.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x4007847C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID16.XDMAC_CSUSChannel Source Microblock Stride
Address 0x40078480
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID16.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x40078484
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID17.XDMAC_CIEChannel Interrupt Enable Register
Address 0x40078490
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID17.XDMAC_CIDChannel Interrupt Disable Register
Address 0x40078494
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID17.XDMAC_CIMChannel Interrupt Mask Register
Address 0x40078498
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID17.XDMAC_CISChannel Interrupt Status Register
Address 0x4007849C
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID17.XDMAC_CSAChannel Source Address Register
Address 0x400784A0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID17.XDMAC_CDAChannel Destination Address Register
Address 0x400784A4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID17.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x400784A8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID17.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x400784AC
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID17.XDMAC_CUBCChannel Microblock Control Register
Address 0x400784B0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID17.XDMAC_CBCChannel Block Control Register
Address 0x400784B4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID17.XDMAC_CCChannel Configuration Register
Address 0x400784B8
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID17.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x400784BC
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID17.XDMAC_CSUSChannel Source Microblock Stride
Address 0x400784C0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID17.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x400784C4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID18.XDMAC_CIEChannel Interrupt Enable Register
Address 0x400784D0
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID18.XDMAC_CIDChannel Interrupt Disable Register
Address 0x400784D4
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID18.XDMAC_CIMChannel Interrupt Mask Register
Address 0x400784D8
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID18.XDMAC_CISChannel Interrupt Status Register
Address 0x400784DC
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID18.XDMAC_CSAChannel Source Address Register
Address 0x400784E0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID18.XDMAC_CDAChannel Destination Address Register
Address 0x400784E4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID18.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x400784E8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID18.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x400784EC
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID18.XDMAC_CUBCChannel Microblock Control Register
Address 0x400784F0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID18.XDMAC_CBCChannel Block Control Register
Address 0x400784F4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID18.XDMAC_CCChannel Configuration Register
Address 0x400784F8
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID18.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x400784FC
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID18.XDMAC_CSUSChannel Source Microblock Stride
Address 0x40078500
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID18.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x40078504
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID19.XDMAC_CIEChannel Interrupt Enable Register
Address 0x40078510
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID19.XDMAC_CIDChannel Interrupt Disable Register
Address 0x40078514
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID19.XDMAC_CIMChannel Interrupt Mask Register
Address 0x40078518
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID19.XDMAC_CISChannel Interrupt Status Register
Address 0x4007851C
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID19.XDMAC_CSAChannel Source Address Register
Address 0x40078520
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID19.XDMAC_CDAChannel Destination Address Register
Address 0x40078524
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID19.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x40078528
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID19.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x4007852C
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID19.XDMAC_CUBCChannel Microblock Control Register
Address 0x40078530
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID19.XDMAC_CBCChannel Block Control Register
Address 0x40078534
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID19.XDMAC_CCChannel Configuration Register
Address 0x40078538
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID19.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x4007853C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID19.XDMAC_CSUSChannel Source Microblock Stride
Address 0x40078540
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID19.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x40078544
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID20.XDMAC_CIEChannel Interrupt Enable Register
Address 0x40078550
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID20.XDMAC_CIDChannel Interrupt Disable Register
Address 0x40078554
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID20.XDMAC_CIMChannel Interrupt Mask Register
Address 0x40078558
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID20.XDMAC_CISChannel Interrupt Status Register
Address 0x4007855C
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID20.XDMAC_CSAChannel Source Address Register
Address 0x40078560
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID20.XDMAC_CDAChannel Destination Address Register
Address 0x40078564
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID20.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x40078568
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID20.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x4007856C
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID20.XDMAC_CUBCChannel Microblock Control Register
Address 0x40078570
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID20.XDMAC_CBCChannel Block Control Register
Address 0x40078574
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID20.XDMAC_CCChannel Configuration Register
Address 0x40078578
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID20.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x4007857C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID20.XDMAC_CSUSChannel Source Microblock Stride
Address 0x40078580
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID20.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x40078584
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID21.XDMAC_CIEChannel Interrupt Enable Register
Address 0x40078590
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID21.XDMAC_CIDChannel Interrupt Disable Register
Address 0x40078594
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID21.XDMAC_CIMChannel Interrupt Mask Register
Address 0x40078598
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID21.XDMAC_CISChannel Interrupt Status Register
Address 0x4007859C
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID21.XDMAC_CSAChannel Source Address Register
Address 0x400785A0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID21.XDMAC_CDAChannel Destination Address Register
Address 0x400785A4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID21.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x400785A8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID21.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x400785AC
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID21.XDMAC_CUBCChannel Microblock Control Register
Address 0x400785B0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID21.XDMAC_CBCChannel Block Control Register
Address 0x400785B4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID21.XDMAC_CCChannel Configuration Register
Address 0x400785B8
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID21.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x400785BC
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID21.XDMAC_CSUSChannel Source Microblock Stride
Address 0x400785C0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID21.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x400785C4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID22.XDMAC_CIEChannel Interrupt Enable Register
Address 0x400785D0
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID22.XDMAC_CIDChannel Interrupt Disable Register
Address 0x400785D4
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID22.XDMAC_CIMChannel Interrupt Mask Register
Address 0x400785D8
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID22.XDMAC_CISChannel Interrupt Status Register
Address 0x400785DC
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID22.XDMAC_CSAChannel Source Address Register
Address 0x400785E0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID22.XDMAC_CDAChannel Destination Address Register
Address 0x400785E4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID22.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x400785E8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID22.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x400785EC
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID22.XDMAC_CUBCChannel Microblock Control Register
Address 0x400785F0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID22.XDMAC_CBCChannel Block Control Register
Address 0x400785F4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID22.XDMAC_CCChannel Configuration Register
Address 0x400785F8
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID22.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x400785FC
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID22.XDMAC_CSUSChannel Source Microblock Stride
Address 0x40078600
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID22.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x40078604
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
XDMAC_CHID23.XDMAC_CIEChannel Interrupt Enable Register
Address 0x40078610
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROIE 6 Request Overflow Error Interrupt Enable Bit WBIE 5 Write Bus Error Interrupt Enable Bit RBIE 4 Read Bus Error Interrupt Enable Bit FIE 3 End of Flush Interrupt Enable Bit DIE 2 End of Disable Interrupt Enable Bit LIE 1 End of Linked List Interrupt Enable Bit BIE 0 End of Block Interrupt Enable Bit
XDMAC_CHID23.XDMAC_CIDChannel Interrupt Disable Register
Address 0x40078614
Reset 0x00000000
Access write only
Size 32-bit 7 fields
Field Bits What it does ROID 6 Request Overflow Error Interrupt Disable Bit WBEID 5 Write Bus Error Interrupt Disable Bit RBEID 4 Read Bus Error Interrupt Disable Bit FID 3 End of Flush Interrupt Disable Bit DID 2 End of Disable Interrupt Disable Bit LID 1 End of Linked List Interrupt Disable Bit BID 0 End of Block Interrupt Disable Bit
XDMAC_CHID23.XDMAC_CIMChannel Interrupt Mask Register
Address 0x40078618
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIM 6 Request Overflow Error Interrupt Mask Bit WBEIM 5 Write Bus Error Interrupt Mask Bit RBEIM 4 Read Bus Error Interrupt Mask Bit FIM 3 End of Flush Interrupt Mask Bit DIM 2 End of Disable Interrupt Mask Bit LIM 1 End of Linked List Interrupt Mask Bit BIM 0 End of Block Interrupt Mask Bit
XDMAC_CHID23.XDMAC_CISChannel Interrupt Status Register
Address 0x4007861C
Reset 0x00000000
Access read only
Size 32-bit 7 fields
Field Bits What it does ROIS 6 Request Overflow Error Interrupt Status Bit WBEIS 5 Write Bus Error Interrupt Status Bit RBEIS 4 Read Bus Error Interrupt Status Bit FIS 3 End of Flush Interrupt Status Bit DIS 2 End of Disable Interrupt Status Bit LIS 1 End of Linked List Interrupt Status Bit BIS 0 End of Block Interrupt Status Bit
XDMAC_CHID23.XDMAC_CSAChannel Source Address Register
Address 0x40078620
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SA 31:0 Channel x Source Address
XDMAC_CHID23.XDMAC_CDAChannel Destination Address Register
Address 0x40078624
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DA 31:0 Channel x Destination Address
XDMAC_CHID23.XDMAC_CNDAChannel Next Descriptor Address Register
Address 0x40078628
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NDAIF 0 Channel x Next Descriptor Interface NDA 31:2 Channel x Next Descriptor Address
XDMAC_CHID23.XDMAC_CNDCChannel Next Descriptor Control Register
Address 0x4007862C
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does NDVIEW 4:3 Channel x Next Descriptor View0 Next Descriptor View 01 Next Descriptor View 12 Next Descriptor View 23 Next Descriptor View 3 NDDUP 2 Channel x Next Descriptor Destination Update0 Destination parameters remain unchanged.1 Destination parameters are updated when the descriptor is retrieved. NDSUP 1 Channel x Next Descriptor Source Update0 Source parameters remain unchanged.1 Source parameters are updated when the descriptor is retrieved. NDE 0 Channel x Next Descriptor Enable0 Descriptor fetch is disabled.1 Descriptor fetch is enabled.
XDMAC_CHID23.XDMAC_CUBCChannel Microblock Control Register
Address 0x40078630
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does UBLEN 23:0 Channel x Microblock Length
XDMAC_CHID23.XDMAC_CBCChannel Block Control Register
Address 0x40078634
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does BLEN 11:0 Channel x Block Length
XDMAC_CHID23.XDMAC_CCChannel Configuration Register
Address 0x40078638
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does PERID 30:24 Channel x Peripheral Hardware Request Line Identifier5 QSPI_TX6 QSPI_RX7 USART0_TX8 USART0_RX9 USART1_TX10 USART1_RX13 PWM014 TWIHS0_TX15 TWIHS0_RX16 TWIHS1_TX17 TWIHS1_RX20 UART0_TX21 UART0_RX22 UART1_TX23 UART1_RX24 UART2_TX25 UART2_RX30 DACC032 SSC_TX33 SSC_RX34 PIOA35 AFEC036 AFEC137 AES_TX38 AES_RX39 PWM140 TC041 TC342 TC643 TC9 WRIP 23 Write in Progress (this bit is read-only)0 No active write transaction on the bus.1 A write transaction is in progress. RDIP 22 Read in Progress (this bit is read-only)0 No active read transaction on the bus.1 A read transaction is in progress. INITD 21 Channel Initialization Terminated (this bit is read-only)0 Channel initialization is in progress.1 Channel initialization is completed. DAM 19:18 Channel x Destination Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. SAM 17:16 Channel x Source Addressing Mode0 The address remains unchanged.1 The addressing mode is incremented (the increment size is set to the data size).2 The microblock stride is added at the microblock boundary.3 The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. DIF 14 Channel x Destination Interface Identifier0 The data is written through the system bus interface 0.1 The data is written though the system bus interface 1. SIF 13 Channel x Source Interface Identifier0 The data is read through the system bus interface 0.1 The data is read through the system bus interface 1. DWIDTH 12:11 Channel x Data Width0 The data size is set to 8 bits1 The data size is set to 16 bits2 The data size is set to 32 bits CSIZE 10:8 Channel x Chunk Size0 1 data transferred1 2 data transferred2 4 data transferred3 8 data transferred4 16 data transferred MEMSET 7 Channel x Fill Block of memory0 Memset is not activated.1 Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. SWREQ 6 Channel x Software Request Trigger0 Hardware request line is connected to the peripheral request line.1 Software request is connected to the peripheral request line. DSYNC 4 Channel x Synchronization0 Peripheral-to-memory transfer.1 Memory-to-peripheral transfer. MBSIZE 2:1 Channel x Memory Burst Size0 The memory burst size is set to one.1 The memory burst size is set to four.2 The memory burst size is set to eight.3 The memory burst size is set to sixteen. TYPE 0 Channel x Transfer Type0 Self-triggered mode (memory-to-memory transfer).1 Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
XDMAC_CHID23.XDMAC_CDS_MSPChannel Data Stride Memory Set Pattern
Address 0x4007863C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SDS_MSP 15:0 Channel x Source Data stride or Memory Set Pattern DDS_MSP 31:16 Channel x Destination Data Stride or Memory Set Pattern
XDMAC_CHID23.XDMAC_CSUSChannel Source Microblock Stride
Address 0x40078640
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SUBS 23:0 Channel x Source Microblock Stride
XDMAC_CHID23.XDMAC_CDUSChannel Destination Microblock Stride
Address 0x40078644
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DUBS 23:0 Channel x Destination Microblock Stride
BETA