The 6 registers of FPU (Floating Point Unit), from 0xE000EF34, with their reset value and every field. The ATSAMV71J20B has 2417 registers in 55 peripherals, one page each.
FPU Floating Point Unit
FPCCRFloating-point Context Control Register
Address
0xE000EF34
Reset
0xC0000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
LSPEN
30
Enable automatic lazy state preservation for floating-point context.
MONRDY
8
DebugMonitor is enabled and priority permits setting MON_PEND when the floating-point stack frame was allocated.
BFRDY
6
BusFault is enabled and priority permitted setting the BusFault handler to the pending state when the floating-point stack frame was allocated.
MMRDY
5
MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated.
HFRDY
4
Priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated.
THREAD
3
Mode was Thread Mode when the floating-point stack frame was allocated.
USER
1
Privilege level was user when the floating-point stack frame was allocated.
LSPACT
0
Lazy state preservation is active. Floating-point stack frame has been allocated but saving state to it has been deferred.
ASPEN
31
Enables CONTROL.FPCA setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration, for floating-point context, on exception entry and exit.
FPCARFloating-point Context Address Register
Address
0xE000EF38
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
ADDRESS
31:3
The location of the unpopulated floating-point register space allocated on an exception stack frame.
FPDSCRFloating-point Default Status Control Register
Address
0xE000EF3C
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
AHP
26
Default value for FPSCR.AHP.
DN
25
Default value for FPSCR.DN.
FZ
24
Default value for FPSCR.FZ.
RMode
23:22
Default value for FPSCR.RMode.
MVFR0Media and VFP Feature Register 0
Address
0xE000EF40
Reset
0x10110021
Access
read only
Size
32-bit
8 fields
Field
Bits
What it does
Short_vectors
27:24
Indicates the hardware support for FP short vectors
Square_root
23:20
Indicates the hardware support for FP square root operations
Divide
19:16
Indicates the hardware support for FP divide operations
FP_excep_trapping
15:12
Indicates whether the FP hardware implementation supports exception trapping
Double_precision
11:8
Indicates the hardware support for FP double-precision operations
Single_precision
7:4
Indicates the hardware support for FP single-precision operations
A_SIMD_registers
3:0
Indicates the size of the FP register bank
FP_rounding_modes
31:28
Indicates the rounding modes supported by the FP floating-point hardware
MVFR1Media and VFP Feature Register 1
Address
0xE000EF44
Reset
0x11000011
Access
read only
Size
32-bit
4 fields
Field
Bits
What it does
FP_HPFP
27:24
Floating Point Half-Precision and double-precision
D_NaN_mode
7:4
Indicates whether the FP hardware implementation supports only the Default NaN mode
FtZ_mode
3:0
Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation
FP_fused_MAC
31:28
Indicates whether the FP supports fused multiply accumulate operations
MVFR2Media and VFP Feature Register 2
Address
0xE000EF48
Reset
0x00000040
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
VFP_Misc
7:4
Indicates the hardware support for FP miscellaneous features
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