ATSAMV71J20B PIOA registers The 55 registers of PIOA (Parallel Input/Output Controller), from 0x400E0E00, with their reset value and every field. The ATSAMV71J20B has 2417 registers in 55 peripherals, one page each.
PIOA Parallel Input/Output Controller PIO_PERPIO Enable Register
Address 0x400E0E00
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 PIO Enable P29 29 PIO Enable P28 28 PIO Enable P27 27 PIO Enable P26 26 PIO Enable P25 25 PIO Enable P24 24 PIO Enable P23 23 PIO Enable P22 22 PIO Enable P21 21 PIO Enable P20 20 PIO Enable P19 19 PIO Enable P18 18 PIO Enable P17 17 PIO Enable P16 16 PIO Enable P15 15 PIO Enable P14 14 PIO Enable P13 13 PIO Enable P12 12 PIO Enable P11 11 PIO Enable P10 10 PIO Enable P9 9 PIO Enable P8 8 PIO Enable P7 7 PIO Enable P6 6 PIO Enable P5 5 PIO Enable P4 4 PIO Enable P3 3 PIO Enable P2 2 PIO Enable P1 1 PIO Enable P0 0 PIO Enable P31 31 PIO Enable
PIO_PDRPIO Disable Register
Address 0x400E0E04
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 PIO Disable P29 29 PIO Disable P28 28 PIO Disable P27 27 PIO Disable P26 26 PIO Disable P25 25 PIO Disable P24 24 PIO Disable P23 23 PIO Disable P22 22 PIO Disable P21 21 PIO Disable P20 20 PIO Disable P19 19 PIO Disable P18 18 PIO Disable P17 17 PIO Disable P16 16 PIO Disable P15 15 PIO Disable P14 14 PIO Disable P13 13 PIO Disable P12 12 PIO Disable P11 11 PIO Disable P10 10 PIO Disable P9 9 PIO Disable P8 8 PIO Disable P7 7 PIO Disable P6 6 PIO Disable P5 5 PIO Disable P4 4 PIO Disable P3 3 PIO Disable P2 2 PIO Disable P1 1 PIO Disable P0 0 PIO Disable P31 31 PIO Disable
PIO_PSRPIO Status Register
Address 0x400E0E08
Reset 0x00000000
Access read only
Size 32-bit 32 fields
Field Bits What it does P30 30 PIO Status P29 29 PIO Status P28 28 PIO Status P27 27 PIO Status P26 26 PIO Status P25 25 PIO Status P24 24 PIO Status P23 23 PIO Status P22 22 PIO Status P21 21 PIO Status P20 20 PIO Status P19 19 PIO Status P18 18 PIO Status P17 17 PIO Status P16 16 PIO Status P15 15 PIO Status P14 14 PIO Status P13 13 PIO Status P12 12 PIO Status P11 11 PIO Status P10 10 PIO Status P9 9 PIO Status P8 8 PIO Status P7 7 PIO Status P6 6 PIO Status P5 5 PIO Status P4 4 PIO Status P3 3 PIO Status P2 2 PIO Status P1 1 PIO Status P0 0 PIO Status P31 31 PIO Status
PIO_OEROutput Enable Register
Address 0x400E0E10
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Output Enable P29 29 Output Enable P28 28 Output Enable P27 27 Output Enable P26 26 Output Enable P25 25 Output Enable P24 24 Output Enable P23 23 Output Enable P22 22 Output Enable P21 21 Output Enable P20 20 Output Enable P19 19 Output Enable P18 18 Output Enable P17 17 Output Enable P16 16 Output Enable P15 15 Output Enable P14 14 Output Enable P13 13 Output Enable P12 12 Output Enable P11 11 Output Enable P10 10 Output Enable P9 9 Output Enable P8 8 Output Enable P7 7 Output Enable P6 6 Output Enable P5 5 Output Enable P4 4 Output Enable P3 3 Output Enable P2 2 Output Enable P1 1 Output Enable P0 0 Output Enable P31 31 Output Enable
PIO_ODROutput Disable Register
Address 0x400E0E14
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Output Disable P29 29 Output Disable P28 28 Output Disable P27 27 Output Disable P26 26 Output Disable P25 25 Output Disable P24 24 Output Disable P23 23 Output Disable P22 22 Output Disable P21 21 Output Disable P20 20 Output Disable P19 19 Output Disable P18 18 Output Disable P17 17 Output Disable P16 16 Output Disable P15 15 Output Disable P14 14 Output Disable P13 13 Output Disable P12 12 Output Disable P11 11 Output Disable P10 10 Output Disable P9 9 Output Disable P8 8 Output Disable P7 7 Output Disable P6 6 Output Disable P5 5 Output Disable P4 4 Output Disable P3 3 Output Disable P2 2 Output Disable P1 1 Output Disable P0 0 Output Disable P31 31 Output Disable
PIO_OSROutput Status Register
Address 0x400E0E18
Reset 0x00000000
Access read only
Size 32-bit 32 fields
Field Bits What it does P30 30 Output Status P29 29 Output Status P28 28 Output Status P27 27 Output Status P26 26 Output Status P25 25 Output Status P24 24 Output Status P23 23 Output Status P22 22 Output Status P21 21 Output Status P20 20 Output Status P19 19 Output Status P18 18 Output Status P17 17 Output Status P16 16 Output Status P15 15 Output Status P14 14 Output Status P13 13 Output Status P12 12 Output Status P11 11 Output Status P10 10 Output Status P9 9 Output Status P8 8 Output Status P7 7 Output Status P6 6 Output Status P5 5 Output Status P4 4 Output Status P3 3 Output Status P2 2 Output Status P1 1 Output Status P0 0 Output Status P31 31 Output Status
PIO_IFERGlitch Input Filter Enable Register
Address 0x400E0E20
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Input Filter Enable P29 29 Input Filter Enable P28 28 Input Filter Enable P27 27 Input Filter Enable P26 26 Input Filter Enable P25 25 Input Filter Enable P24 24 Input Filter Enable P23 23 Input Filter Enable P22 22 Input Filter Enable P21 21 Input Filter Enable P20 20 Input Filter Enable P19 19 Input Filter Enable P18 18 Input Filter Enable P17 17 Input Filter Enable P16 16 Input Filter Enable P15 15 Input Filter Enable P14 14 Input Filter Enable P13 13 Input Filter Enable P12 12 Input Filter Enable P11 11 Input Filter Enable P10 10 Input Filter Enable P9 9 Input Filter Enable P8 8 Input Filter Enable P7 7 Input Filter Enable P6 6 Input Filter Enable P5 5 Input Filter Enable P4 4 Input Filter Enable P3 3 Input Filter Enable P2 2 Input Filter Enable P1 1 Input Filter Enable P0 0 Input Filter Enable P31 31 Input Filter Enable
PIO_IFDRGlitch Input Filter Disable Register
Address 0x400E0E24
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Input Filter Disable P29 29 Input Filter Disable P28 28 Input Filter Disable P27 27 Input Filter Disable P26 26 Input Filter Disable P25 25 Input Filter Disable P24 24 Input Filter Disable P23 23 Input Filter Disable P22 22 Input Filter Disable P21 21 Input Filter Disable P20 20 Input Filter Disable P19 19 Input Filter Disable P18 18 Input Filter Disable P17 17 Input Filter Disable P16 16 Input Filter Disable P15 15 Input Filter Disable P14 14 Input Filter Disable P13 13 Input Filter Disable P12 12 Input Filter Disable P11 11 Input Filter Disable P10 10 Input Filter Disable P9 9 Input Filter Disable P8 8 Input Filter Disable P7 7 Input Filter Disable P6 6 Input Filter Disable P5 5 Input Filter Disable P4 4 Input Filter Disable P3 3 Input Filter Disable P2 2 Input Filter Disable P1 1 Input Filter Disable P0 0 Input Filter Disable P31 31 Input Filter Disable
PIO_IFSRGlitch Input Filter Status Register
Address 0x400E0E28
Reset 0x00000000
Access read only
Size 32-bit 32 fields
Field Bits What it does P30 30 Input Filter Status P29 29 Input Filter Status P28 28 Input Filter Status P27 27 Input Filter Status P26 26 Input Filter Status P25 25 Input Filter Status P24 24 Input Filter Status P23 23 Input Filter Status P22 22 Input Filter Status P21 21 Input Filter Status P20 20 Input Filter Status P19 19 Input Filter Status P18 18 Input Filter Status P17 17 Input Filter Status P16 16 Input Filter Status P15 15 Input Filter Status P14 14 Input Filter Status P13 13 Input Filter Status P12 12 Input Filter Status P11 11 Input Filter Status P10 10 Input Filter Status P9 9 Input Filter Status P8 8 Input Filter Status P7 7 Input Filter Status P6 6 Input Filter Status P5 5 Input Filter Status P4 4 Input Filter Status P3 3 Input Filter Status P2 2 Input Filter Status P1 1 Input Filter Status P0 0 Input Filter Status P31 31 Input Filter Status
PIO_SODRSet Output Data Register
Address 0x400E0E30
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Set Output Data P29 29 Set Output Data P28 28 Set Output Data P27 27 Set Output Data P26 26 Set Output Data P25 25 Set Output Data P24 24 Set Output Data P23 23 Set Output Data P22 22 Set Output Data P21 21 Set Output Data P20 20 Set Output Data P19 19 Set Output Data P18 18 Set Output Data P17 17 Set Output Data P16 16 Set Output Data P15 15 Set Output Data P14 14 Set Output Data P13 13 Set Output Data P12 12 Set Output Data P11 11 Set Output Data P10 10 Set Output Data P9 9 Set Output Data P8 8 Set Output Data P7 7 Set Output Data P6 6 Set Output Data P5 5 Set Output Data P4 4 Set Output Data P3 3 Set Output Data P2 2 Set Output Data P1 1 Set Output Data P0 0 Set Output Data P31 31 Set Output Data
PIO_CODRClear Output Data Register
Address 0x400E0E34
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Clear Output Data P29 29 Clear Output Data P28 28 Clear Output Data P27 27 Clear Output Data P26 26 Clear Output Data P25 25 Clear Output Data P24 24 Clear Output Data P23 23 Clear Output Data P22 22 Clear Output Data P21 21 Clear Output Data P20 20 Clear Output Data P19 19 Clear Output Data P18 18 Clear Output Data P17 17 Clear Output Data P16 16 Clear Output Data P15 15 Clear Output Data P14 14 Clear Output Data P13 13 Clear Output Data P12 12 Clear Output Data P11 11 Clear Output Data P10 10 Clear Output Data P9 9 Clear Output Data P8 8 Clear Output Data P7 7 Clear Output Data P6 6 Clear Output Data P5 5 Clear Output Data P4 4 Clear Output Data P3 3 Clear Output Data P2 2 Clear Output Data P1 1 Clear Output Data P0 0 Clear Output Data P31 31 Clear Output Data
PIO_ODSROutput Data Status Register
Address 0x400E0E38
Reset 0x00000000
Access read/write
Size 32-bit 32 fields
Field Bits What it does P30 30 Output Data Status P29 29 Output Data Status P28 28 Output Data Status P27 27 Output Data Status P26 26 Output Data Status P25 25 Output Data Status P24 24 Output Data Status P23 23 Output Data Status P22 22 Output Data Status P21 21 Output Data Status P20 20 Output Data Status P19 19 Output Data Status P18 18 Output Data Status P17 17 Output Data Status P16 16 Output Data Status P15 15 Output Data Status P14 14 Output Data Status P13 13 Output Data Status P12 12 Output Data Status P11 11 Output Data Status P10 10 Output Data Status P9 9 Output Data Status P8 8 Output Data Status P7 7 Output Data Status P6 6 Output Data Status P5 5 Output Data Status P4 4 Output Data Status P3 3 Output Data Status P2 2 Output Data Status P1 1 Output Data Status P0 0 Output Data Status P31 31 Output Data Status
PIO_PDSRPin Data Status Register
Address 0x400E0E3C
Reset 0x00000000
Access read only
Size 32-bit 32 fields
Field Bits What it does P30 30 Output Data Status P29 29 Output Data Status P28 28 Output Data Status P27 27 Output Data Status P26 26 Output Data Status P25 25 Output Data Status P24 24 Output Data Status P23 23 Output Data Status P22 22 Output Data Status P21 21 Output Data Status P20 20 Output Data Status P19 19 Output Data Status P18 18 Output Data Status P17 17 Output Data Status P16 16 Output Data Status P15 15 Output Data Status P14 14 Output Data Status P13 13 Output Data Status P12 12 Output Data Status P11 11 Output Data Status P10 10 Output Data Status P9 9 Output Data Status P8 8 Output Data Status P7 7 Output Data Status P6 6 Output Data Status P5 5 Output Data Status P4 4 Output Data Status P3 3 Output Data Status P2 2 Output Data Status P1 1 Output Data Status P0 0 Output Data Status P31 31 Output Data Status
PIO_IERInterrupt Enable Register
Address 0x400E0E40
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Input Change Interrupt Enable P29 29 Input Change Interrupt Enable P28 28 Input Change Interrupt Enable P27 27 Input Change Interrupt Enable P26 26 Input Change Interrupt Enable P25 25 Input Change Interrupt Enable P24 24 Input Change Interrupt Enable P23 23 Input Change Interrupt Enable P22 22 Input Change Interrupt Enable P21 21 Input Change Interrupt Enable P20 20 Input Change Interrupt Enable P19 19 Input Change Interrupt Enable P18 18 Input Change Interrupt Enable P17 17 Input Change Interrupt Enable P16 16 Input Change Interrupt Enable P15 15 Input Change Interrupt Enable P14 14 Input Change Interrupt Enable P13 13 Input Change Interrupt Enable P12 12 Input Change Interrupt Enable P11 11 Input Change Interrupt Enable P10 10 Input Change Interrupt Enable P9 9 Input Change Interrupt Enable P8 8 Input Change Interrupt Enable P7 7 Input Change Interrupt Enable P6 6 Input Change Interrupt Enable P5 5 Input Change Interrupt Enable P4 4 Input Change Interrupt Enable P3 3 Input Change Interrupt Enable P2 2 Input Change Interrupt Enable P1 1 Input Change Interrupt Enable P0 0 Input Change Interrupt Enable P31 31 Input Change Interrupt Enable
PIO_IDRInterrupt Disable Register
Address 0x400E0E44
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Input Change Interrupt Disable P29 29 Input Change Interrupt Disable P28 28 Input Change Interrupt Disable P27 27 Input Change Interrupt Disable P26 26 Input Change Interrupt Disable P25 25 Input Change Interrupt Disable P24 24 Input Change Interrupt Disable P23 23 Input Change Interrupt Disable P22 22 Input Change Interrupt Disable P21 21 Input Change Interrupt Disable P20 20 Input Change Interrupt Disable P19 19 Input Change Interrupt Disable P18 18 Input Change Interrupt Disable P17 17 Input Change Interrupt Disable P16 16 Input Change Interrupt Disable P15 15 Input Change Interrupt Disable P14 14 Input Change Interrupt Disable P13 13 Input Change Interrupt Disable P12 12 Input Change Interrupt Disable P11 11 Input Change Interrupt Disable P10 10 Input Change Interrupt Disable P9 9 Input Change Interrupt Disable P8 8 Input Change Interrupt Disable P7 7 Input Change Interrupt Disable P6 6 Input Change Interrupt Disable P5 5 Input Change Interrupt Disable P4 4 Input Change Interrupt Disable P3 3 Input Change Interrupt Disable P2 2 Input Change Interrupt Disable P1 1 Input Change Interrupt Disable P0 0 Input Change Interrupt Disable P31 31 Input Change Interrupt Disable
PIO_IMRInterrupt Mask Register
Address 0x400E0E48
Reset 0x00000000
Access read only
Size 32-bit 32 fields
Field Bits What it does P30 30 Input Change Interrupt Mask P29 29 Input Change Interrupt Mask P28 28 Input Change Interrupt Mask P27 27 Input Change Interrupt Mask P26 26 Input Change Interrupt Mask P25 25 Input Change Interrupt Mask P24 24 Input Change Interrupt Mask P23 23 Input Change Interrupt Mask P22 22 Input Change Interrupt Mask P21 21 Input Change Interrupt Mask P20 20 Input Change Interrupt Mask P19 19 Input Change Interrupt Mask P18 18 Input Change Interrupt Mask P17 17 Input Change Interrupt Mask P16 16 Input Change Interrupt Mask P15 15 Input Change Interrupt Mask P14 14 Input Change Interrupt Mask P13 13 Input Change Interrupt Mask P12 12 Input Change Interrupt Mask P11 11 Input Change Interrupt Mask P10 10 Input Change Interrupt Mask P9 9 Input Change Interrupt Mask P8 8 Input Change Interrupt Mask P7 7 Input Change Interrupt Mask P6 6 Input Change Interrupt Mask P5 5 Input Change Interrupt Mask P4 4 Input Change Interrupt Mask P3 3 Input Change Interrupt Mask P2 2 Input Change Interrupt Mask P1 1 Input Change Interrupt Mask P0 0 Input Change Interrupt Mask P31 31 Input Change Interrupt Mask
PIO_ISRInterrupt Status Register
Address 0x400E0E4C
Reset 0x00000000
Access read only
Size 32-bit 32 fields
Field Bits What it does P30 30 Input Change Interrupt Status P29 29 Input Change Interrupt Status P28 28 Input Change Interrupt Status P27 27 Input Change Interrupt Status P26 26 Input Change Interrupt Status P25 25 Input Change Interrupt Status P24 24 Input Change Interrupt Status P23 23 Input Change Interrupt Status P22 22 Input Change Interrupt Status P21 21 Input Change Interrupt Status P20 20 Input Change Interrupt Status P19 19 Input Change Interrupt Status P18 18 Input Change Interrupt Status P17 17 Input Change Interrupt Status P16 16 Input Change Interrupt Status P15 15 Input Change Interrupt Status P14 14 Input Change Interrupt Status P13 13 Input Change Interrupt Status P12 12 Input Change Interrupt Status P11 11 Input Change Interrupt Status P10 10 Input Change Interrupt Status P9 9 Input Change Interrupt Status P8 8 Input Change Interrupt Status P7 7 Input Change Interrupt Status P6 6 Input Change Interrupt Status P5 5 Input Change Interrupt Status P4 4 Input Change Interrupt Status P3 3 Input Change Interrupt Status P2 2 Input Change Interrupt Status P1 1 Input Change Interrupt Status P0 0 Input Change Interrupt Status P31 31 Input Change Interrupt Status
PIO_MDERMulti-driver Enable Register
Address 0x400E0E50
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Multi-drive Enable P29 29 Multi-drive Enable P28 28 Multi-drive Enable P27 27 Multi-drive Enable P26 26 Multi-drive Enable P25 25 Multi-drive Enable P24 24 Multi-drive Enable P23 23 Multi-drive Enable P22 22 Multi-drive Enable P21 21 Multi-drive Enable P20 20 Multi-drive Enable P19 19 Multi-drive Enable P18 18 Multi-drive Enable P17 17 Multi-drive Enable P16 16 Multi-drive Enable P15 15 Multi-drive Enable P14 14 Multi-drive Enable P13 13 Multi-drive Enable P12 12 Multi-drive Enable P11 11 Multi-drive Enable P10 10 Multi-drive Enable P9 9 Multi-drive Enable P8 8 Multi-drive Enable P7 7 Multi-drive Enable P6 6 Multi-drive Enable P5 5 Multi-drive Enable P4 4 Multi-drive Enable P3 3 Multi-drive Enable P2 2 Multi-drive Enable P1 1 Multi-drive Enable P0 0 Multi-drive Enable P31 31 Multi-drive Enable
PIO_MDDRMulti-driver Disable Register
Address 0x400E0E54
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Multi-drive Disable P29 29 Multi-drive Disable P28 28 Multi-drive Disable P27 27 Multi-drive Disable P26 26 Multi-drive Disable P25 25 Multi-drive Disable P24 24 Multi-drive Disable P23 23 Multi-drive Disable P22 22 Multi-drive Disable P21 21 Multi-drive Disable P20 20 Multi-drive Disable P19 19 Multi-drive Disable P18 18 Multi-drive Disable P17 17 Multi-drive Disable P16 16 Multi-drive Disable P15 15 Multi-drive Disable P14 14 Multi-drive Disable P13 13 Multi-drive Disable P12 12 Multi-drive Disable P11 11 Multi-drive Disable P10 10 Multi-drive Disable P9 9 Multi-drive Disable P8 8 Multi-drive Disable P7 7 Multi-drive Disable P6 6 Multi-drive Disable P5 5 Multi-drive Disable P4 4 Multi-drive Disable P3 3 Multi-drive Disable P2 2 Multi-drive Disable P1 1 Multi-drive Disable P0 0 Multi-drive Disable P31 31 Multi-drive Disable
PIO_MDSRMulti-driver Status Register
Address 0x400E0E58
Reset 0x00000000
Access read only
Size 32-bit 32 fields
Field Bits What it does P30 30 Multi-drive Status P29 29 Multi-drive Status P28 28 Multi-drive Status P27 27 Multi-drive Status P26 26 Multi-drive Status P25 25 Multi-drive Status P24 24 Multi-drive Status P23 23 Multi-drive Status P22 22 Multi-drive Status P21 21 Multi-drive Status P20 20 Multi-drive Status P19 19 Multi-drive Status P18 18 Multi-drive Status P17 17 Multi-drive Status P16 16 Multi-drive Status P15 15 Multi-drive Status P14 14 Multi-drive Status P13 13 Multi-drive Status P12 12 Multi-drive Status P11 11 Multi-drive Status P10 10 Multi-drive Status P9 9 Multi-drive Status P8 8 Multi-drive Status P7 7 Multi-drive Status P6 6 Multi-drive Status P5 5 Multi-drive Status P4 4 Multi-drive Status P3 3 Multi-drive Status P2 2 Multi-drive Status P1 1 Multi-drive Status P0 0 Multi-drive Status P31 31 Multi-drive Status
PIO_PUDRPull-up Disable Register
Address 0x400E0E60
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Pull-Up Disable P29 29 Pull-Up Disable P28 28 Pull-Up Disable P27 27 Pull-Up Disable P26 26 Pull-Up Disable P25 25 Pull-Up Disable P24 24 Pull-Up Disable P23 23 Pull-Up Disable P22 22 Pull-Up Disable P21 21 Pull-Up Disable P20 20 Pull-Up Disable P19 19 Pull-Up Disable P18 18 Pull-Up Disable P17 17 Pull-Up Disable P16 16 Pull-Up Disable P15 15 Pull-Up Disable P14 14 Pull-Up Disable P13 13 Pull-Up Disable P12 12 Pull-Up Disable P11 11 Pull-Up Disable P10 10 Pull-Up Disable P9 9 Pull-Up Disable P8 8 Pull-Up Disable P7 7 Pull-Up Disable P6 6 Pull-Up Disable P5 5 Pull-Up Disable P4 4 Pull-Up Disable P3 3 Pull-Up Disable P2 2 Pull-Up Disable P1 1 Pull-Up Disable P0 0 Pull-Up Disable P31 31 Pull-Up Disable
PIO_PUERPull-up Enable Register
Address 0x400E0E64
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Pull-Up Enable P29 29 Pull-Up Enable P28 28 Pull-Up Enable P27 27 Pull-Up Enable P26 26 Pull-Up Enable P25 25 Pull-Up Enable P24 24 Pull-Up Enable P23 23 Pull-Up Enable P22 22 Pull-Up Enable P21 21 Pull-Up Enable P20 20 Pull-Up Enable P19 19 Pull-Up Enable P18 18 Pull-Up Enable P17 17 Pull-Up Enable P16 16 Pull-Up Enable P15 15 Pull-Up Enable P14 14 Pull-Up Enable P13 13 Pull-Up Enable P12 12 Pull-Up Enable P11 11 Pull-Up Enable P10 10 Pull-Up Enable P9 9 Pull-Up Enable P8 8 Pull-Up Enable P7 7 Pull-Up Enable P6 6 Pull-Up Enable P5 5 Pull-Up Enable P4 4 Pull-Up Enable P3 3 Pull-Up Enable P2 2 Pull-Up Enable P1 1 Pull-Up Enable P0 0 Pull-Up Enable P31 31 Pull-Up Enable
PIO_PUSRPad Pull-up Status Register
Address 0x400E0E68
Reset 0x00000000
Access read only
Size 32-bit 32 fields
Field Bits What it does P30 30 Pull-Up Status P29 29 Pull-Up Status P28 28 Pull-Up Status P27 27 Pull-Up Status P26 26 Pull-Up Status P25 25 Pull-Up Status P24 24 Pull-Up Status P23 23 Pull-Up Status P22 22 Pull-Up Status P21 21 Pull-Up Status P20 20 Pull-Up Status P19 19 Pull-Up Status P18 18 Pull-Up Status P17 17 Pull-Up Status P16 16 Pull-Up Status P15 15 Pull-Up Status P14 14 Pull-Up Status P13 13 Pull-Up Status P12 12 Pull-Up Status P11 11 Pull-Up Status P10 10 Pull-Up Status P9 9 Pull-Up Status P8 8 Pull-Up Status P7 7 Pull-Up Status P6 6 Pull-Up Status P5 5 Pull-Up Status P4 4 Pull-Up Status P3 3 Pull-Up Status P2 2 Pull-Up Status P1 1 Pull-Up Status P0 0 Pull-Up Status P31 31 Pull-Up Status
PIO_ABCDSR0Peripheral ABCD Select Register 0
Address 0x400E0E70
Reset 0x00000000
Access read/write
Size 32-bit 32 fields
Field Bits What it does P30 30 Peripheral Select P29 29 Peripheral Select P28 28 Peripheral Select P27 27 Peripheral Select P26 26 Peripheral Select P25 25 Peripheral Select P24 24 Peripheral Select P23 23 Peripheral Select P22 22 Peripheral Select P21 21 Peripheral Select P20 20 Peripheral Select P19 19 Peripheral Select P18 18 Peripheral Select P17 17 Peripheral Select P16 16 Peripheral Select P15 15 Peripheral Select P14 14 Peripheral Select P13 13 Peripheral Select P12 12 Peripheral Select P11 11 Peripheral Select P10 10 Peripheral Select P9 9 Peripheral Select P8 8 Peripheral Select P7 7 Peripheral Select P6 6 Peripheral Select P5 5 Peripheral Select P4 4 Peripheral Select P3 3 Peripheral Select P2 2 Peripheral Select P1 1 Peripheral Select P0 0 Peripheral Select P31 31 Peripheral Select
PIO_ABCDSR1Peripheral ABCD Select Register 0
Address 0x400E0E74
Reset 0x00000000
Access read/write
Size 32-bit 32 fields
Field Bits What it does P30 30 Peripheral Select P29 29 Peripheral Select P28 28 Peripheral Select P27 27 Peripheral Select P26 26 Peripheral Select P25 25 Peripheral Select P24 24 Peripheral Select P23 23 Peripheral Select P22 22 Peripheral Select P21 21 Peripheral Select P20 20 Peripheral Select P19 19 Peripheral Select P18 18 Peripheral Select P17 17 Peripheral Select P16 16 Peripheral Select P15 15 Peripheral Select P14 14 Peripheral Select P13 13 Peripheral Select P12 12 Peripheral Select P11 11 Peripheral Select P10 10 Peripheral Select P9 9 Peripheral Select P8 8 Peripheral Select P7 7 Peripheral Select P6 6 Peripheral Select P5 5 Peripheral Select P4 4 Peripheral Select P3 3 Peripheral Select P2 2 Peripheral Select P1 1 Peripheral Select P0 0 Peripheral Select P31 31 Peripheral Select
PIO_IFSCDRInput Filter Slow Clock Disable Register
Address 0x400E0E80
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Peripheral Clock Glitch Filtering Select P29 29 Peripheral Clock Glitch Filtering Select P28 28 Peripheral Clock Glitch Filtering Select P27 27 Peripheral Clock Glitch Filtering Select P26 26 Peripheral Clock Glitch Filtering Select P25 25 Peripheral Clock Glitch Filtering Select P24 24 Peripheral Clock Glitch Filtering Select P23 23 Peripheral Clock Glitch Filtering Select P22 22 Peripheral Clock Glitch Filtering Select P21 21 Peripheral Clock Glitch Filtering Select P20 20 Peripheral Clock Glitch Filtering Select P19 19 Peripheral Clock Glitch Filtering Select P18 18 Peripheral Clock Glitch Filtering Select P17 17 Peripheral Clock Glitch Filtering Select P16 16 Peripheral Clock Glitch Filtering Select P15 15 Peripheral Clock Glitch Filtering Select P14 14 Peripheral Clock Glitch Filtering Select P13 13 Peripheral Clock Glitch Filtering Select P12 12 Peripheral Clock Glitch Filtering Select P11 11 Peripheral Clock Glitch Filtering Select P10 10 Peripheral Clock Glitch Filtering Select P9 9 Peripheral Clock Glitch Filtering Select P8 8 Peripheral Clock Glitch Filtering Select P7 7 Peripheral Clock Glitch Filtering Select P6 6 Peripheral Clock Glitch Filtering Select P5 5 Peripheral Clock Glitch Filtering Select P4 4 Peripheral Clock Glitch Filtering Select P3 3 Peripheral Clock Glitch Filtering Select P2 2 Peripheral Clock Glitch Filtering Select P1 1 Peripheral Clock Glitch Filtering Select P0 0 Peripheral Clock Glitch Filtering Select P31 31 Peripheral Clock Glitch Filtering Select
PIO_IFSCERInput Filter Slow Clock Enable Register
Address 0x400E0E84
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Slow Clock Debouncing Filtering Select P29 29 Slow Clock Debouncing Filtering Select P28 28 Slow Clock Debouncing Filtering Select P27 27 Slow Clock Debouncing Filtering Select P26 26 Slow Clock Debouncing Filtering Select P25 25 Slow Clock Debouncing Filtering Select P24 24 Slow Clock Debouncing Filtering Select P23 23 Slow Clock Debouncing Filtering Select P22 22 Slow Clock Debouncing Filtering Select P21 21 Slow Clock Debouncing Filtering Select P20 20 Slow Clock Debouncing Filtering Select P19 19 Slow Clock Debouncing Filtering Select P18 18 Slow Clock Debouncing Filtering Select P17 17 Slow Clock Debouncing Filtering Select P16 16 Slow Clock Debouncing Filtering Select P15 15 Slow Clock Debouncing Filtering Select P14 14 Slow Clock Debouncing Filtering Select P13 13 Slow Clock Debouncing Filtering Select P12 12 Slow Clock Debouncing Filtering Select P11 11 Slow Clock Debouncing Filtering Select P10 10 Slow Clock Debouncing Filtering Select P9 9 Slow Clock Debouncing Filtering Select P8 8 Slow Clock Debouncing Filtering Select P7 7 Slow Clock Debouncing Filtering Select P6 6 Slow Clock Debouncing Filtering Select P5 5 Slow Clock Debouncing Filtering Select P4 4 Slow Clock Debouncing Filtering Select P3 3 Slow Clock Debouncing Filtering Select P2 2 Slow Clock Debouncing Filtering Select P1 1 Slow Clock Debouncing Filtering Select P0 0 Slow Clock Debouncing Filtering Select P31 31 Slow Clock Debouncing Filtering Select
PIO_IFSCSRInput Filter Slow Clock Status Register
Address 0x400E0E88
Reset 0x00000000
Access read only
Size 32-bit 32 fields
Field Bits What it does P30 30 Glitch or Debouncing Filter Selection Status P29 29 Glitch or Debouncing Filter Selection Status P28 28 Glitch or Debouncing Filter Selection Status P27 27 Glitch or Debouncing Filter Selection Status P26 26 Glitch or Debouncing Filter Selection Status P25 25 Glitch or Debouncing Filter Selection Status P24 24 Glitch or Debouncing Filter Selection Status P23 23 Glitch or Debouncing Filter Selection Status P22 22 Glitch or Debouncing Filter Selection Status P21 21 Glitch or Debouncing Filter Selection Status P20 20 Glitch or Debouncing Filter Selection Status P19 19 Glitch or Debouncing Filter Selection Status P18 18 Glitch or Debouncing Filter Selection Status P17 17 Glitch or Debouncing Filter Selection Status P16 16 Glitch or Debouncing Filter Selection Status P15 15 Glitch or Debouncing Filter Selection Status P14 14 Glitch or Debouncing Filter Selection Status P13 13 Glitch or Debouncing Filter Selection Status P12 12 Glitch or Debouncing Filter Selection Status P11 11 Glitch or Debouncing Filter Selection Status P10 10 Glitch or Debouncing Filter Selection Status P9 9 Glitch or Debouncing Filter Selection Status P8 8 Glitch or Debouncing Filter Selection Status P7 7 Glitch or Debouncing Filter Selection Status P6 6 Glitch or Debouncing Filter Selection Status P5 5 Glitch or Debouncing Filter Selection Status P4 4 Glitch or Debouncing Filter Selection Status P3 3 Glitch or Debouncing Filter Selection Status P2 2 Glitch or Debouncing Filter Selection Status P1 1 Glitch or Debouncing Filter Selection Status P0 0 Glitch or Debouncing Filter Selection Status P31 31 Glitch or Debouncing Filter Selection Status
PIO_SCDRSlow Clock Divider Debouncing Register
Address 0x400E0E8C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DIV 13:0 Slow Clock Divider Selection for Debouncing
PIO_PPDDRPad Pull-down Disable Register
Address 0x400E0E90
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Pull-Down Disable P29 29 Pull-Down Disable P28 28 Pull-Down Disable P27 27 Pull-Down Disable P26 26 Pull-Down Disable P25 25 Pull-Down Disable P24 24 Pull-Down Disable P23 23 Pull-Down Disable P22 22 Pull-Down Disable P21 21 Pull-Down Disable P20 20 Pull-Down Disable P19 19 Pull-Down Disable P18 18 Pull-Down Disable P17 17 Pull-Down Disable P16 16 Pull-Down Disable P15 15 Pull-Down Disable P14 14 Pull-Down Disable P13 13 Pull-Down Disable P12 12 Pull-Down Disable P11 11 Pull-Down Disable P10 10 Pull-Down Disable P9 9 Pull-Down Disable P8 8 Pull-Down Disable P7 7 Pull-Down Disable P6 6 Pull-Down Disable P5 5 Pull-Down Disable P4 4 Pull-Down Disable P3 3 Pull-Down Disable P2 2 Pull-Down Disable P1 1 Pull-Down Disable P0 0 Pull-Down Disable P31 31 Pull-Down Disable
PIO_PPDERPad Pull-down Enable Register
Address 0x400E0E94
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Pull-Down Enable P29 29 Pull-Down Enable P28 28 Pull-Down Enable P27 27 Pull-Down Enable P26 26 Pull-Down Enable P25 25 Pull-Down Enable P24 24 Pull-Down Enable P23 23 Pull-Down Enable P22 22 Pull-Down Enable P21 21 Pull-Down Enable P20 20 Pull-Down Enable P19 19 Pull-Down Enable P18 18 Pull-Down Enable P17 17 Pull-Down Enable P16 16 Pull-Down Enable P15 15 Pull-Down Enable P14 14 Pull-Down Enable P13 13 Pull-Down Enable P12 12 Pull-Down Enable P11 11 Pull-Down Enable P10 10 Pull-Down Enable P9 9 Pull-Down Enable P8 8 Pull-Down Enable P7 7 Pull-Down Enable P6 6 Pull-Down Enable P5 5 Pull-Down Enable P4 4 Pull-Down Enable P3 3 Pull-Down Enable P2 2 Pull-Down Enable P1 1 Pull-Down Enable P0 0 Pull-Down Enable P31 31 Pull-Down Enable
PIO_PPDSRPad Pull-down Status Register
Address 0x400E0E98
Reset 0x00000000
Access read only
Size 32-bit 32 fields
Field Bits What it does P30 30 Pull-Down Status P29 29 Pull-Down Status P28 28 Pull-Down Status P27 27 Pull-Down Status P26 26 Pull-Down Status P25 25 Pull-Down Status P24 24 Pull-Down Status P23 23 Pull-Down Status P22 22 Pull-Down Status P21 21 Pull-Down Status P20 20 Pull-Down Status P19 19 Pull-Down Status P18 18 Pull-Down Status P17 17 Pull-Down Status P16 16 Pull-Down Status P15 15 Pull-Down Status P14 14 Pull-Down Status P13 13 Pull-Down Status P12 12 Pull-Down Status P11 11 Pull-Down Status P10 10 Pull-Down Status P9 9 Pull-Down Status P8 8 Pull-Down Status P7 7 Pull-Down Status P6 6 Pull-Down Status P5 5 Pull-Down Status P4 4 Pull-Down Status P3 3 Pull-Down Status P2 2 Pull-Down Status P1 1 Pull-Down Status P0 0 Pull-Down Status P31 31 Pull-Down Status
PIO_OWEROutput Write Enable
Address 0x400E0EA0
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Output Write Enable P29 29 Output Write Enable P28 28 Output Write Enable P27 27 Output Write Enable P26 26 Output Write Enable P25 25 Output Write Enable P24 24 Output Write Enable P23 23 Output Write Enable P22 22 Output Write Enable P21 21 Output Write Enable P20 20 Output Write Enable P19 19 Output Write Enable P18 18 Output Write Enable P17 17 Output Write Enable P16 16 Output Write Enable P15 15 Output Write Enable P14 14 Output Write Enable P13 13 Output Write Enable P12 12 Output Write Enable P11 11 Output Write Enable P10 10 Output Write Enable P9 9 Output Write Enable P8 8 Output Write Enable P7 7 Output Write Enable P6 6 Output Write Enable P5 5 Output Write Enable P4 4 Output Write Enable P3 3 Output Write Enable P2 2 Output Write Enable P1 1 Output Write Enable P0 0 Output Write Enable P31 31 Output Write Enable
PIO_OWDROutput Write Disable
Address 0x400E0EA4
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Output Write Disable P29 29 Output Write Disable P28 28 Output Write Disable P27 27 Output Write Disable P26 26 Output Write Disable P25 25 Output Write Disable P24 24 Output Write Disable P23 23 Output Write Disable P22 22 Output Write Disable P21 21 Output Write Disable P20 20 Output Write Disable P19 19 Output Write Disable P18 18 Output Write Disable P17 17 Output Write Disable P16 16 Output Write Disable P15 15 Output Write Disable P14 14 Output Write Disable P13 13 Output Write Disable P12 12 Output Write Disable P11 11 Output Write Disable P10 10 Output Write Disable P9 9 Output Write Disable P8 8 Output Write Disable P7 7 Output Write Disable P6 6 Output Write Disable P5 5 Output Write Disable P4 4 Output Write Disable P3 3 Output Write Disable P2 2 Output Write Disable P1 1 Output Write Disable P0 0 Output Write Disable P31 31 Output Write Disable
PIO_OWSROutput Write Status Register
Address 0x400E0EA8
Reset 0x00000000
Access read only
Size 32-bit 32 fields
Field Bits What it does P30 30 Output Write Status P29 29 Output Write Status P28 28 Output Write Status P27 27 Output Write Status P26 26 Output Write Status P25 25 Output Write Status P24 24 Output Write Status P23 23 Output Write Status P22 22 Output Write Status P21 21 Output Write Status P20 20 Output Write Status P19 19 Output Write Status P18 18 Output Write Status P17 17 Output Write Status P16 16 Output Write Status P15 15 Output Write Status P14 14 Output Write Status P13 13 Output Write Status P12 12 Output Write Status P11 11 Output Write Status P10 10 Output Write Status P9 9 Output Write Status P8 8 Output Write Status P7 7 Output Write Status P6 6 Output Write Status P5 5 Output Write Status P4 4 Output Write Status P3 3 Output Write Status P2 2 Output Write Status P1 1 Output Write Status P0 0 Output Write Status P31 31 Output Write Status
PIO_AIMERAdditional Interrupt Modes Enable Register
Address 0x400E0EB0
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Additional Interrupt Modes Enable P29 29 Additional Interrupt Modes Enable P28 28 Additional Interrupt Modes Enable P27 27 Additional Interrupt Modes Enable P26 26 Additional Interrupt Modes Enable P25 25 Additional Interrupt Modes Enable P24 24 Additional Interrupt Modes Enable P23 23 Additional Interrupt Modes Enable P22 22 Additional Interrupt Modes Enable P21 21 Additional Interrupt Modes Enable P20 20 Additional Interrupt Modes Enable P19 19 Additional Interrupt Modes Enable P18 18 Additional Interrupt Modes Enable P17 17 Additional Interrupt Modes Enable P16 16 Additional Interrupt Modes Enable P15 15 Additional Interrupt Modes Enable P14 14 Additional Interrupt Modes Enable P13 13 Additional Interrupt Modes Enable P12 12 Additional Interrupt Modes Enable P11 11 Additional Interrupt Modes Enable P10 10 Additional Interrupt Modes Enable P9 9 Additional Interrupt Modes Enable P8 8 Additional Interrupt Modes Enable P7 7 Additional Interrupt Modes Enable P6 6 Additional Interrupt Modes Enable P5 5 Additional Interrupt Modes Enable P4 4 Additional Interrupt Modes Enable P3 3 Additional Interrupt Modes Enable P2 2 Additional Interrupt Modes Enable P1 1 Additional Interrupt Modes Enable P0 0 Additional Interrupt Modes Enable P31 31 Additional Interrupt Modes Enable
PIO_AIMDRAdditional Interrupt Modes Disable Register
Address 0x400E0EB4
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Additional Interrupt Modes Disable P29 29 Additional Interrupt Modes Disable P28 28 Additional Interrupt Modes Disable P27 27 Additional Interrupt Modes Disable P26 26 Additional Interrupt Modes Disable P25 25 Additional Interrupt Modes Disable P24 24 Additional Interrupt Modes Disable P23 23 Additional Interrupt Modes Disable P22 22 Additional Interrupt Modes Disable P21 21 Additional Interrupt Modes Disable P20 20 Additional Interrupt Modes Disable P19 19 Additional Interrupt Modes Disable P18 18 Additional Interrupt Modes Disable P17 17 Additional Interrupt Modes Disable P16 16 Additional Interrupt Modes Disable P15 15 Additional Interrupt Modes Disable P14 14 Additional Interrupt Modes Disable P13 13 Additional Interrupt Modes Disable P12 12 Additional Interrupt Modes Disable P11 11 Additional Interrupt Modes Disable P10 10 Additional Interrupt Modes Disable P9 9 Additional Interrupt Modes Disable P8 8 Additional Interrupt Modes Disable P7 7 Additional Interrupt Modes Disable P6 6 Additional Interrupt Modes Disable P5 5 Additional Interrupt Modes Disable P4 4 Additional Interrupt Modes Disable P3 3 Additional Interrupt Modes Disable P2 2 Additional Interrupt Modes Disable P1 1 Additional Interrupt Modes Disable P0 0 Additional Interrupt Modes Disable P31 31 Additional Interrupt Modes Disable
PIO_AIMMRAdditional Interrupt Modes Mask Register
Address 0x400E0EB8
Reset 0x00000000
Access read only
Size 32-bit 32 fields
Field Bits What it does P30 30 IO Line Index P29 29 IO Line Index P28 28 IO Line Index P27 27 IO Line Index P26 26 IO Line Index P25 25 IO Line Index P24 24 IO Line Index P23 23 IO Line Index P22 22 IO Line Index P21 21 IO Line Index P20 20 IO Line Index P19 19 IO Line Index P18 18 IO Line Index P17 17 IO Line Index P16 16 IO Line Index P15 15 IO Line Index P14 14 IO Line Index P13 13 IO Line Index P12 12 IO Line Index P11 11 IO Line Index P10 10 IO Line Index P9 9 IO Line Index P8 8 IO Line Index P7 7 IO Line Index P6 6 IO Line Index P5 5 IO Line Index P4 4 IO Line Index P3 3 IO Line Index P2 2 IO Line Index P1 1 IO Line Index P0 0 IO Line Index P31 31 IO Line Index
PIO_ESREdge Select Register
Address 0x400E0EC0
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Edge Interrupt Selection P29 29 Edge Interrupt Selection P28 28 Edge Interrupt Selection P27 27 Edge Interrupt Selection P26 26 Edge Interrupt Selection P25 25 Edge Interrupt Selection P24 24 Edge Interrupt Selection P23 23 Edge Interrupt Selection P22 22 Edge Interrupt Selection P21 21 Edge Interrupt Selection P20 20 Edge Interrupt Selection P19 19 Edge Interrupt Selection P18 18 Edge Interrupt Selection P17 17 Edge Interrupt Selection P16 16 Edge Interrupt Selection P15 15 Edge Interrupt Selection P14 14 Edge Interrupt Selection P13 13 Edge Interrupt Selection P12 12 Edge Interrupt Selection P11 11 Edge Interrupt Selection P10 10 Edge Interrupt Selection P9 9 Edge Interrupt Selection P8 8 Edge Interrupt Selection P7 7 Edge Interrupt Selection P6 6 Edge Interrupt Selection P5 5 Edge Interrupt Selection P4 4 Edge Interrupt Selection P3 3 Edge Interrupt Selection P2 2 Edge Interrupt Selection P1 1 Edge Interrupt Selection P0 0 Edge Interrupt Selection P31 31 Edge Interrupt Selection
PIO_LSRLevel Select Register
Address 0x400E0EC4
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Level Interrupt Selection P29 29 Level Interrupt Selection P28 28 Level Interrupt Selection P27 27 Level Interrupt Selection P26 26 Level Interrupt Selection P25 25 Level Interrupt Selection P24 24 Level Interrupt Selection P23 23 Level Interrupt Selection P22 22 Level Interrupt Selection P21 21 Level Interrupt Selection P20 20 Level Interrupt Selection P19 19 Level Interrupt Selection P18 18 Level Interrupt Selection P17 17 Level Interrupt Selection P16 16 Level Interrupt Selection P15 15 Level Interrupt Selection P14 14 Level Interrupt Selection P13 13 Level Interrupt Selection P12 12 Level Interrupt Selection P11 11 Level Interrupt Selection P10 10 Level Interrupt Selection P9 9 Level Interrupt Selection P8 8 Level Interrupt Selection P7 7 Level Interrupt Selection P6 6 Level Interrupt Selection P5 5 Level Interrupt Selection P4 4 Level Interrupt Selection P3 3 Level Interrupt Selection P2 2 Level Interrupt Selection P1 1 Level Interrupt Selection P0 0 Level Interrupt Selection P31 31 Level Interrupt Selection
PIO_ELSREdge/Level Status Register
Address 0x400E0EC8
Reset 0x00000000
Access read only
Size 32-bit 32 fields
Field Bits What it does P30 30 Edge/Level Interrupt Source Selection P29 29 Edge/Level Interrupt Source Selection P28 28 Edge/Level Interrupt Source Selection P27 27 Edge/Level Interrupt Source Selection P26 26 Edge/Level Interrupt Source Selection P25 25 Edge/Level Interrupt Source Selection P24 24 Edge/Level Interrupt Source Selection P23 23 Edge/Level Interrupt Source Selection P22 22 Edge/Level Interrupt Source Selection P21 21 Edge/Level Interrupt Source Selection P20 20 Edge/Level Interrupt Source Selection P19 19 Edge/Level Interrupt Source Selection P18 18 Edge/Level Interrupt Source Selection P17 17 Edge/Level Interrupt Source Selection P16 16 Edge/Level Interrupt Source Selection P15 15 Edge/Level Interrupt Source Selection P14 14 Edge/Level Interrupt Source Selection P13 13 Edge/Level Interrupt Source Selection P12 12 Edge/Level Interrupt Source Selection P11 11 Edge/Level Interrupt Source Selection P10 10 Edge/Level Interrupt Source Selection P9 9 Edge/Level Interrupt Source Selection P8 8 Edge/Level Interrupt Source Selection P7 7 Edge/Level Interrupt Source Selection P6 6 Edge/Level Interrupt Source Selection P5 5 Edge/Level Interrupt Source Selection P4 4 Edge/Level Interrupt Source Selection P3 3 Edge/Level Interrupt Source Selection P2 2 Edge/Level Interrupt Source Selection P1 1 Edge/Level Interrupt Source Selection P0 0 Edge/Level Interrupt Source Selection P31 31 Edge/Level Interrupt Source Selection
PIO_FELLSRFalling Edge/Low-Level Select Register
Address 0x400E0ED0
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Falling Edge/Low-Level Interrupt Selection P29 29 Falling Edge/Low-Level Interrupt Selection P28 28 Falling Edge/Low-Level Interrupt Selection P27 27 Falling Edge/Low-Level Interrupt Selection P26 26 Falling Edge/Low-Level Interrupt Selection P25 25 Falling Edge/Low-Level Interrupt Selection P24 24 Falling Edge/Low-Level Interrupt Selection P23 23 Falling Edge/Low-Level Interrupt Selection P22 22 Falling Edge/Low-Level Interrupt Selection P21 21 Falling Edge/Low-Level Interrupt Selection P20 20 Falling Edge/Low-Level Interrupt Selection P19 19 Falling Edge/Low-Level Interrupt Selection P18 18 Falling Edge/Low-Level Interrupt Selection P17 17 Falling Edge/Low-Level Interrupt Selection P16 16 Falling Edge/Low-Level Interrupt Selection P15 15 Falling Edge/Low-Level Interrupt Selection P14 14 Falling Edge/Low-Level Interrupt Selection P13 13 Falling Edge/Low-Level Interrupt Selection P12 12 Falling Edge/Low-Level Interrupt Selection P11 11 Falling Edge/Low-Level Interrupt Selection P10 10 Falling Edge/Low-Level Interrupt Selection P9 9 Falling Edge/Low-Level Interrupt Selection P8 8 Falling Edge/Low-Level Interrupt Selection P7 7 Falling Edge/Low-Level Interrupt Selection P6 6 Falling Edge/Low-Level Interrupt Selection P5 5 Falling Edge/Low-Level Interrupt Selection P4 4 Falling Edge/Low-Level Interrupt Selection P3 3 Falling Edge/Low-Level Interrupt Selection P2 2 Falling Edge/Low-Level Interrupt Selection P1 1 Falling Edge/Low-Level Interrupt Selection P0 0 Falling Edge/Low-Level Interrupt Selection P31 31 Falling Edge/Low-Level Interrupt Selection
PIO_REHLSRRising Edge/High-Level Select Register
Address 0x400E0ED4
Reset 0x00000000
Access write only
Size 32-bit 32 fields
Field Bits What it does P30 30 Rising Edge/High-Level Interrupt Selection P29 29 Rising Edge/High-Level Interrupt Selection P28 28 Rising Edge/High-Level Interrupt Selection P27 27 Rising Edge/High-Level Interrupt Selection P26 26 Rising Edge/High-Level Interrupt Selection P25 25 Rising Edge/High-Level Interrupt Selection P24 24 Rising Edge/High-Level Interrupt Selection P23 23 Rising Edge/High-Level Interrupt Selection P22 22 Rising Edge/High-Level Interrupt Selection P21 21 Rising Edge/High-Level Interrupt Selection P20 20 Rising Edge/High-Level Interrupt Selection P19 19 Rising Edge/High-Level Interrupt Selection P18 18 Rising Edge/High-Level Interrupt Selection P17 17 Rising Edge/High-Level Interrupt Selection P16 16 Rising Edge/High-Level Interrupt Selection P15 15 Rising Edge/High-Level Interrupt Selection P14 14 Rising Edge/High-Level Interrupt Selection P13 13 Rising Edge/High-Level Interrupt Selection P12 12 Rising Edge/High-Level Interrupt Selection P11 11 Rising Edge/High-Level Interrupt Selection P10 10 Rising Edge/High-Level Interrupt Selection P9 9 Rising Edge/High-Level Interrupt Selection P8 8 Rising Edge/High-Level Interrupt Selection P7 7 Rising Edge/High-Level Interrupt Selection P6 6 Rising Edge/High-Level Interrupt Selection P5 5 Rising Edge/High-Level Interrupt Selection P4 4 Rising Edge/High-Level Interrupt Selection P3 3 Rising Edge/High-Level Interrupt Selection P2 2 Rising Edge/High-Level Interrupt Selection P1 1 Rising Edge/High-Level Interrupt Selection P0 0 Rising Edge/High-Level Interrupt Selection P31 31 Rising Edge/High-Level Interrupt Selection
PIO_FRLHSRFall/Rise - Low/High Status Register
Address 0x400E0ED8
Reset 0x00000000
Access read only
Size 32-bit 32 fields
Field Bits What it does P30 30 Edge/Level Interrupt Source Selection P29 29 Edge/Level Interrupt Source Selection P28 28 Edge/Level Interrupt Source Selection P27 27 Edge/Level Interrupt Source Selection P26 26 Edge/Level Interrupt Source Selection P25 25 Edge/Level Interrupt Source Selection P24 24 Edge/Level Interrupt Source Selection P23 23 Edge/Level Interrupt Source Selection P22 22 Edge/Level Interrupt Source Selection P21 21 Edge/Level Interrupt Source Selection P20 20 Edge/Level Interrupt Source Selection P19 19 Edge/Level Interrupt Source Selection P18 18 Edge/Level Interrupt Source Selection P17 17 Edge/Level Interrupt Source Selection P16 16 Edge/Level Interrupt Source Selection P15 15 Edge/Level Interrupt Source Selection P14 14 Edge/Level Interrupt Source Selection P13 13 Edge/Level Interrupt Source Selection P12 12 Edge/Level Interrupt Source Selection P11 11 Edge/Level Interrupt Source Selection P10 10 Edge/Level Interrupt Source Selection P9 9 Edge/Level Interrupt Source Selection P8 8 Edge/Level Interrupt Source Selection P7 7 Edge/Level Interrupt Source Selection P6 6 Edge/Level Interrupt Source Selection P5 5 Edge/Level Interrupt Source Selection P4 4 Edge/Level Interrupt Source Selection P3 3 Edge/Level Interrupt Source Selection P2 2 Edge/Level Interrupt Source Selection P1 1 Edge/Level Interrupt Source Selection P0 0 Edge/Level Interrupt Source Selection P31 31 Edge/Level Interrupt Source Selection
PIO_LOCKSRLock Status
Address 0x400E0EE0
Reset 0x00000000
Access read only
Size 32-bit 32 fields
Field Bits What it does P30 30 Lock Status P29 29 Lock Status P28 28 Lock Status P27 27 Lock Status P26 26 Lock Status P25 25 Lock Status P24 24 Lock Status P23 23 Lock Status P22 22 Lock Status P21 21 Lock Status P20 20 Lock Status P19 19 Lock Status P18 18 Lock Status P17 17 Lock Status P16 16 Lock Status P15 15 Lock Status P14 14 Lock Status P13 13 Lock Status P12 12 Lock Status P11 11 Lock Status P10 10 Lock Status P9 9 Lock Status P8 8 Lock Status P7 7 Lock Status P6 6 Lock Status P5 5 Lock Status P4 4 Lock Status P3 3 Lock Status P2 2 Lock Status P1 1 Lock Status P0 0 Lock Status P31 31 Lock Status
PIO_WPMRWrite Protection Mode Register
Address 0x400E0EE4
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does WPEN 0 Write Protection Enable WPKEY 31:8 Write Protection Key5261647 Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
PIO_WPSRWrite Protection Status Register
Address 0x400E0EE8
Reset 0x00000000
Access read only
Size 32-bit 2 fields
Field Bits What it does WPVSRC 23:8 Write Protection Violation Source WPVS 0 Write Protection Violation Status
PIO_SCHMITTSchmitt Trigger Register
Address 0x400E0F00
Reset 0x00000000
Access read/write
Size 32-bit 32 fields
Field Bits What it does SCHMITT30 30 Schmitt Trigger Control SCHMITT29 29 Schmitt Trigger Control SCHMITT28 28 Schmitt Trigger Control SCHMITT27 27 Schmitt Trigger Control SCHMITT26 26 Schmitt Trigger Control SCHMITT25 25 Schmitt Trigger Control SCHMITT24 24 Schmitt Trigger Control SCHMITT23 23 Schmitt Trigger Control SCHMITT22 22 Schmitt Trigger Control SCHMITT21 21 Schmitt Trigger Control SCHMITT20 20 Schmitt Trigger Control SCHMITT19 19 Schmitt Trigger Control SCHMITT18 18 Schmitt Trigger Control SCHMITT17 17 Schmitt Trigger Control SCHMITT16 16 Schmitt Trigger Control SCHMITT15 15 Schmitt Trigger Control SCHMITT14 14 Schmitt Trigger Control SCHMITT13 13 Schmitt Trigger Control SCHMITT12 12 Schmitt Trigger Control SCHMITT11 11 Schmitt Trigger Control SCHMITT10 10 Schmitt Trigger Control SCHMITT9 9 Schmitt Trigger Control SCHMITT8 8 Schmitt Trigger Control SCHMITT7 7 Schmitt Trigger Control SCHMITT6 6 Schmitt Trigger Control SCHMITT5 5 Schmitt Trigger Control SCHMITT4 4 Schmitt Trigger Control SCHMITT3 3 Schmitt Trigger Control SCHMITT2 2 Schmitt Trigger Control SCHMITT1 1 Schmitt Trigger Control SCHMITT0 0 Schmitt Trigger Control SCHMITT31 31 Schmitt Trigger Control
PIO_DRIVERI/O Drive Register
Address 0x400E0F18
Reset 0x00000000
Access read/write
Size 32-bit 32 fields
Field Bits What it does LINE30 30 Drive of PIO Line 300 Lowest drive1 Highest drive LINE29 29 Drive of PIO Line 290 Lowest drive1 Highest drive LINE28 28 Drive of PIO Line 280 Lowest drive1 Highest drive LINE27 27 Drive of PIO Line 270 Lowest drive1 Highest drive LINE26 26 Drive of PIO Line 260 Lowest drive1 Highest drive LINE25 25 Drive of PIO Line 250 Lowest drive1 Highest drive LINE24 24 Drive of PIO Line 240 Lowest drive1 Highest drive LINE23 23 Drive of PIO Line 230 Lowest drive1 Highest drive LINE22 22 Drive of PIO Line 220 Lowest drive1 Highest drive LINE21 21 Drive of PIO Line 210 Lowest drive1 Highest drive LINE20 20 Drive of PIO Line 200 Lowest drive1 Highest drive LINE19 19 Drive of PIO Line 190 Lowest drive1 Highest drive LINE18 18 Drive of PIO Line 180 Lowest drive1 Highest drive LINE17 17 Drive of PIO Line 170 Lowest drive1 Highest drive LINE16 16 Drive of PIO Line 160 Lowest drive1 Highest drive LINE15 15 Drive of PIO Line 150 Lowest drive1 Highest drive LINE14 14 Drive of PIO Line 140 Lowest drive1 Highest drive LINE13 13 Drive of PIO Line 130 Lowest drive1 Highest drive LINE12 12 Drive of PIO Line 120 Lowest drive1 Highest drive LINE11 11 Drive of PIO Line 110 Lowest drive1 Highest drive LINE10 10 Drive of PIO Line 100 Lowest drive1 Highest drive LINE9 9 Drive of PIO Line 90 Lowest drive1 Highest drive LINE8 8 Drive of PIO Line 80 Lowest drive1 Highest drive LINE7 7 Drive of PIO Line 70 Lowest drive1 Highest drive LINE6 6 Drive of PIO Line 60 Lowest drive1 Highest drive LINE5 5 Drive of PIO Line 50 Lowest drive1 Highest drive LINE4 4 Drive of PIO Line 40 Lowest drive1 Highest drive LINE3 3 Drive of PIO Line 30 Lowest drive1 Highest drive LINE2 2 Drive of PIO Line 20 Lowest drive1 Highest drive LINE1 1 Drive of PIO Line 10 Lowest drive1 Highest drive LINE0 0 Drive of PIO Line 00 Lowest drive1 Highest drive LINE31 31 Drive of PIO Line 310 Lowest drive1 Highest drive
PIO_PCMRParallel Capture Mode Register
Address 0x400E0F50
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does FRSTS 11 Parallel Capture Mode First Sample HALFS 10 Parallel Capture Mode Half Sampling ALWYS 9 Parallel Capture Mode Always Sampling DSIZE 5:4 Parallel Capture Mode Data Size0 The reception data in the PIO_PCRHR is a byte (8-bit)1 The reception data in the PIO_PCRHR is a half-word (16-bit)2 The reception data in the PIO_PCRHR is a word (32-bit) PCEN 0 Parallel Capture Mode Enable
PIO_PCIERParallel Capture Interrupt Enable Register
Address 0x400E0F54
Reset 0x00000000
Access write only
Size 32-bit 4 fields
Field Bits What it does RXBUFF 3 Reception Buffer Full Interrupt Enable ENDRX 2 End of Reception Transfer Interrupt Enable OVRE 1 Parallel Capture Mode Overrun Error Interrupt Enable DRDY 0 Parallel Capture Mode Data Ready Interrupt Enable
PIO_PCIDRParallel Capture Interrupt Disable Register
Address 0x400E0F58
Reset 0x00000000
Access write only
Size 32-bit 4 fields
Field Bits What it does RXBUFF 3 Reception Buffer Full Interrupt Disable ENDRX 2 End of Reception Transfer Interrupt Disable OVRE 1 Parallel Capture Mode Overrun Error Interrupt Disable DRDY 0 Parallel Capture Mode Data Ready Interrupt Disable
PIO_PCIMRParallel Capture Interrupt Mask Register
Address 0x400E0F5C
Reset 0x00000000
Access read only
Size 32-bit 4 fields
Field Bits What it does RXBUFF 3 Reception Buffer Full Interrupt Mask ENDRX 2 End of Reception Transfer Interrupt Mask OVRE 1 Parallel Capture Mode Overrun Error Interrupt Mask DRDY 0 Parallel Capture Mode Data Ready Interrupt Mask
PIO_PCISRParallel Capture Interrupt Status Register
Address 0x400E0F60
Reset 0x00000000
Access read only
Size 32-bit 2 fields
Field Bits What it does OVRE 1 Parallel Capture Mode Overrun Error DRDY 0 Parallel Capture Mode Data Ready
PIO_PCRHRParallel Capture Reception Holding Register
Address 0x400E0F64
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does RDATA 31:0 Parallel Capture Mode Reception Data
BETA