ATSAMV71Q21RT AFEC0 registers

The 29 registers of AFEC0 (Analog Front-End Controller), from 0x4003C000, with their reset value and every field. The ATSAMV71Q21RT has 3003 registers in 69 peripherals, one page each.

AFEC0 Analog Front-End Controller

AFEC_CRAFEC Control Register

Address: 0x4003C000
Reset: 0x00000000
Access: write only
Size: 32-bit

2 fields

Field	Bits	What it does
START	1	Start Conversion
SWRST	0	Software Reset

AFEC_MRAFEC Mode Register

Address: 0x4003C004
Reset: 0x00000000
Access: read/write
Size: 32-bit

11 fields

Field	Bits	What it does
TRANSFER	29:28	Transfer Period
TRACKTIM	27:24	Tracking Time
ONE	23	One
STARTUP	19:16	Start-up Time `0` 0 periods of AFE clock `1` 8 periods of AFE clock `2` 16 periods of AFE clock `3` 24 periods of AFE clock `4` 64 periods of AFE clock `5` 80 periods of AFE clock `6` 96 periods of AFE clock `7` 112 periods of AFE clock `8` 512 periods of AFE clock `9` 576 periods of AFE clock `10` 640 periods of AFE clock `11` 704 periods of AFE clock `12` 768 periods of AFE clock `13` 832 periods of AFE clock `14` 896 periods of AFE clock `15` 960 periods of AFE clock
PRESCAL	15:8	Prescaler Rate Selection
FREERUN	7	Free Run Mode `0` Normal mode `1` Free Run mode: Never wait for any trigger.
FWUP	6	Fast Wake-up `0` Normal Sleep mode: The sleep mode is defined by the SLEEP bit. `1` Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF.
SLEEP	5	Sleep Mode `0` Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. `1` Sleep mode: The AFE and reference voltage circuitry are OFF between conversions.
TRGSEL	3:1	Trigger Selection `0` AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 `1` TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 `2` TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 `3` TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 `4` PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 `5` PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 `6` Analog Comparator
TRGEN	0	Trigger Enable `0` Hardware triggers are disabled. Starting a conversion is only possible by software. `1` Hardware trigger selected by TRGSEL field is enabled.
USEQ	31	User Sequence Enable `0` Normal mode: The controller converts channels in a simple numeric order. `1` User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R.

AFEC_EMRAFEC Extended Mode Register

Address: 0x4003C008
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
SIGNMODE	29:28	Sign Mode `0` Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. `1` Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. `2` All channels: Unsigned conversions. `3` All channels: Signed conversions.
STM	25	Single Trigger Mode
TAG	24	TAG of the AFEC_LDCR
RES	18:16	Resolution `0` 12-bit resolution, AFE sample rate is maximum (no averaging). `2` 13-bit resolution, AFE sample rate divided by 4 (averaging). `3` 14-bit resolution, AFE sample rate divided by 16 (averaging). `4` 15-bit resolution, AFE sample rate divided by 64 (averaging). `5` 16-bit resolution, AFE sample rate divided by 256 (averaging).
CMPFILTER	13:12	Compare Event Filtering
CMPALL	9	Compare All Channels
CMPSEL	7:3	Comparison Selected Channel
CMPMODE	1:0	Comparison Mode `0` Generates an event when the converted data is lower than the low threshold of the window. `1` Generates an event when the converted data is higher than the high threshold of the window. `2` Generates an event when the converted data is in the comparison window. `3` Generates an event when the converted data is out of the comparison window.

AFEC_SEQ1RAFEC Channel Sequence 1 Register

Address: 0x4003C00C
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
USCH6	27:24	User Sequence Number 6
USCH5	23:20	User Sequence Number 5
USCH4	19:16	User Sequence Number 4
USCH3	15:12	User Sequence Number 3
USCH2	11:8	User Sequence Number 2
USCH1	7:4	User Sequence Number 1
USCH0	3:0	User Sequence Number 0
USCH7	31:28	User Sequence Number 7

AFEC_SEQ2RAFEC Channel Sequence 2 Register

Address: 0x4003C010
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
USCH11	15:12	User Sequence Number 11
USCH10	11:8	User Sequence Number 10
USCH9	7:4	User Sequence Number 9
USCH8	3:0	User Sequence Number 8

AFEC_CHERAFEC Channel Enable Register

Address: 0x4003C014
Reset: 0x00000000
Access: write only
Size: 32-bit

12 fields

Field	Bits	What it does
CH11	11	Channel 11 Enable
CH10	10	Channel 10 Enable
CH9	9	Channel 9 Enable
CH8	8	Channel 8 Enable
CH7	7	Channel 7 Enable
CH6	6	Channel 6 Enable
CH5	5	Channel 5 Enable
CH4	4	Channel 4 Enable
CH3	3	Channel 3 Enable
CH2	2	Channel 2 Enable
CH1	1	Channel 1 Enable
CH0	0	Channel 0 Enable

AFEC_CHDRAFEC Channel Disable Register

Address: 0x4003C018
Reset: 0x00000000
Access: write only
Size: 32-bit

12 fields

Field	Bits	What it does
CH11	11	Channel 11 Disable
CH10	10	Channel 10 Disable
CH9	9	Channel 9 Disable
CH8	8	Channel 8 Disable
CH7	7	Channel 7 Disable
CH6	6	Channel 6 Disable
CH5	5	Channel 5 Disable
CH4	4	Channel 4 Disable
CH3	3	Channel 3 Disable
CH2	2	Channel 2 Disable
CH1	1	Channel 1 Disable
CH0	0	Channel 0 Disable

AFEC_CHSRAFEC Channel Status Register

Address: 0x4003C01C
Reset: 0x00000000
Access: read only
Size: 32-bit

12 fields

Field	Bits	What it does
CH11	11	Channel 11 Status
CH10	10	Channel 10 Status
CH9	9	Channel 9 Status
CH8	8	Channel 8 Status
CH7	7	Channel 7 Status
CH6	6	Channel 6 Status
CH5	5	Channel 5 Status
CH4	4	Channel 4 Status
CH3	3	Channel 3 Status
CH2	2	Channel 2 Status
CH1	1	Channel 1 Status
CH0	0	Channel 0 Status

AFEC_LCDRAFEC Last Converted Data Register

Address: 0x4003C020
Reset: 0x00000000
Access: read only
Size: 32-bit

2 fields

Field	Bits	What it does
CHNB	27:24	Channel Number
LDATA	15:0	Last Data Converted

AFEC_IERAFEC Interrupt Enable Register

Address: 0x4003C024
Reset: 0x00000000
Access: write only
Size: 32-bit

16 fields

Field	Bits	What it does
TEMPCHG	30	Temperature Change Interrupt Enable
COMPE	26	Comparison Event Interrupt Enable
GOVRE	25	General Overrun Error Interrupt Enable
DRDY	24	Data Ready Interrupt Enable
EOC11	11	End of Conversion Interrupt Enable 11
EOC10	10	End of Conversion Interrupt Enable 10
EOC9	9	End of Conversion Interrupt Enable 9
EOC8	8	End of Conversion Interrupt Enable 8
EOC7	7	End of Conversion Interrupt Enable 7
EOC6	6	End of Conversion Interrupt Enable 6
EOC5	5	End of Conversion Interrupt Enable 5
EOC4	4	End of Conversion Interrupt Enable 4
EOC3	3	End of Conversion Interrupt Enable 3
EOC2	2	End of Conversion Interrupt Enable 2
EOC1	1	End of Conversion Interrupt Enable 1
EOC0	0	End of Conversion Interrupt Enable 0

AFEC_IDRAFEC Interrupt Disable Register

Address: 0x4003C028
Reset: 0x00000000
Access: write only
Size: 32-bit

16 fields

Field	Bits	What it does
TEMPCHG	30	Temperature Change Interrupt Disable
COMPE	26	Comparison Event Interrupt Disable
GOVRE	25	General Overrun Error Interrupt Disable
DRDY	24	Data Ready Interrupt Disable
EOC11	11	End of Conversion Interrupt Disable 11
EOC10	10	End of Conversion Interrupt Disable 10
EOC9	9	End of Conversion Interrupt Disable 9
EOC8	8	End of Conversion Interrupt Disable 8
EOC7	7	End of Conversion Interrupt Disable 7
EOC6	6	End of Conversion Interrupt Disable 6
EOC5	5	End of Conversion Interrupt Disable 5
EOC4	4	End of Conversion Interrupt Disable 4
EOC3	3	End of Conversion Interrupt Disable 3
EOC2	2	End of Conversion Interrupt Disable 2
EOC1	1	End of Conversion Interrupt Disable 1
EOC0	0	End of Conversion Interrupt Disable 0

AFEC_IMRAFEC Interrupt Mask Register

Address: 0x4003C02C
Reset: 0x00000000
Access: read only
Size: 32-bit

16 fields

Field	Bits	What it does
TEMPCHG	30	Temperature Change Interrupt Mask
COMPE	26	Comparison Event Interrupt Mask
GOVRE	25	General Overrun Error Interrupt Mask
DRDY	24	Data Ready Interrupt Mask
EOC11	11	End of Conversion Interrupt Mask 11
EOC10	10	End of Conversion Interrupt Mask 10
EOC9	9	End of Conversion Interrupt Mask 9
EOC8	8	End of Conversion Interrupt Mask 8
EOC7	7	End of Conversion Interrupt Mask 7
EOC6	6	End of Conversion Interrupt Mask 6
EOC5	5	End of Conversion Interrupt Mask 5
EOC4	4	End of Conversion Interrupt Mask 4
EOC3	3	End of Conversion Interrupt Mask 3
EOC2	2	End of Conversion Interrupt Mask 2
EOC1	1	End of Conversion Interrupt Mask 1
EOC0	0	End of Conversion Interrupt Mask 0

AFEC_ISRAFEC Interrupt Status Register

Address: 0x4003C030
Reset: 0x00000000
Access: read only
Size: 32-bit

16 fields

Field	Bits	What it does
TEMPCHG	30	Temperature Change (cleared on read)
COMPE	26	Comparison Error (cleared by reading AFEC_ISR)
GOVRE	25	General Overrun Error (cleared by reading AFEC_ISR)
DRDY	24	Data Ready (cleared by reading AFEC_LCDR)
EOC11	11	End of Conversion 11 (cleared by reading AFEC_CDRx)
EOC10	10	End of Conversion 10 (cleared by reading AFEC_CDRx)
EOC9	9	End of Conversion 9 (cleared by reading AFEC_CDRx)
EOC8	8	End of Conversion 8 (cleared by reading AFEC_CDRx)
EOC7	7	End of Conversion 7 (cleared by reading AFEC_CDRx)
EOC6	6	End of Conversion 6 (cleared by reading AFEC_CDRx)
EOC5	5	End of Conversion 5 (cleared by reading AFEC_CDRx)
EOC4	4	End of Conversion 4 (cleared by reading AFEC_CDRx)
EOC3	3	End of Conversion 3 (cleared by reading AFEC_CDRx)
EOC2	2	End of Conversion 2 (cleared by reading AFEC_CDRx)
EOC1	1	End of Conversion 1 (cleared by reading AFEC_CDRx)
EOC0	0	End of Conversion 0 (cleared by reading AFEC_CDRx)

AFEC_OVERAFEC Overrun Status Register

Address: 0x4003C04C
Reset: 0x00000000
Access: read only
Size: 32-bit

12 fields

Field	Bits	What it does
OVRE11	11	Overrun Error 11
OVRE10	10	Overrun Error 10
OVRE9	9	Overrun Error 9
OVRE8	8	Overrun Error 8
OVRE7	7	Overrun Error 7
OVRE6	6	Overrun Error 6
OVRE5	5	Overrun Error 5
OVRE4	4	Overrun Error 4
OVRE3	3	Overrun Error 3
OVRE2	2	Overrun Error 2
OVRE1	1	Overrun Error 1
OVRE0	0	Overrun Error 0

AFEC_CWRAFEC Compare Window Register

Address: 0x4003C050
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
LOWTHRES	15:0	Low Threshold
HIGHTHRES	31:16	High Threshold

AFEC_CGRAFEC Channel Gain Register

Address: 0x4003C054
Reset: 0x00000000
Access: read/write
Size: 32-bit

12 fields

Field	Bits	What it does
GAIN11	23:22	Gain for Channel 11
GAIN10	21:20	Gain for Channel 10
GAIN9	19:18	Gain for Channel 9
GAIN8	17:16	Gain for Channel 8
GAIN7	15:14	Gain for Channel 7
GAIN6	13:12	Gain for Channel 6
GAIN5	11:10	Gain for Channel 5
GAIN4	9:8	Gain for Channel 4
GAIN3	7:6	Gain for Channel 3
GAIN2	5:4	Gain for Channel 2
GAIN1	3:2	Gain for Channel 1
GAIN0	1:0	Gain for Channel 0

AFEC_DIFFRAFEC Channel Differential Register

Address: 0x4003C060
Reset: 0x00000000
Access: read/write
Size: 32-bit

12 fields

Field	Bits	What it does
DIFF11	11	Differential inputs for channel 11
DIFF10	10	Differential inputs for channel 10
DIFF9	9	Differential inputs for channel 9
DIFF8	8	Differential inputs for channel 8
DIFF7	7	Differential inputs for channel 7
DIFF6	6	Differential inputs for channel 6
DIFF5	5	Differential inputs for channel 5
DIFF4	4	Differential inputs for channel 4
DIFF3	3	Differential inputs for channel 3
DIFF2	2	Differential inputs for channel 2
DIFF1	1	Differential inputs for channel 1
DIFF0	0	Differential inputs for channel 0

AFEC_CSELRAFEC Channel Selection Register

Address: 0x4003C064
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CSEL	3:0	Channel Selection

AFEC_CDRAFEC Channel Data Register

Address: 0x4003C068
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
DATA	15:0	Converted Data

AFEC_COCRAFEC Channel Offset Compensation Register

Address: 0x4003C06C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
AOFF	9:0	Analog Offset

AFEC_TEMPMRAFEC Temperature Sensor Mode Register

Address: 0x4003C070
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
TEMPCMPMOD	5:4	Temperature Comparison Mode `0` Generates an event when the converted data is lower than the low threshold of the window. `1` Generates an event when the converted data is higher than the high threshold of the window. `2` Generates an event when the converted data is in the comparison window. `3` Generates an event when the converted data is out of the comparison window.
RTCT	0	Temperature Sensor RTC Trigger Mode

AFEC_TEMPCWRAFEC Temperature Compare Window Register

Address: 0x4003C074
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
TLOWTHRES	15:0	Temperature Low Threshold
THIGHTHRES	31:16	Temperature High Threshold

AFEC_ACRAFEC Analog Control Register

Address: 0x4003C094
Reset: 0x00000000
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
IBCTL	9:8	AFE Bias Current Control
PGA1EN	3	PGA1 Enable
PGA0EN	2	PGA0 Enable

AFEC_SHMRAFEC Sample & Hold Mode Register

Address: 0x4003C0A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

12 fields

Field	Bits	What it does
DUAL11	11	Dual Sample & Hold for channel 11
DUAL10	10	Dual Sample & Hold for channel 10
DUAL9	9	Dual Sample & Hold for channel 9
DUAL8	8	Dual Sample & Hold for channel 8
DUAL7	7	Dual Sample & Hold for channel 7
DUAL6	6	Dual Sample & Hold for channel 6
DUAL5	5	Dual Sample & Hold for channel 5
DUAL4	4	Dual Sample & Hold for channel 4
DUAL3	3	Dual Sample & Hold for channel 3
DUAL2	2	Dual Sample & Hold for channel 2
DUAL1	1	Dual Sample & Hold for channel 1
DUAL0	0	Dual Sample & Hold for channel 0

AFEC_COSRAFEC Correction Select Register

Address: 0x4003C0D0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CSEL	0	Sample & Hold unit Correction Select

AFEC_CVRAFEC Correction Values Register

Address: 0x4003C0D4
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
OFFSETCORR	15:0	Offset Correction
GAINCORR	31:16	Gain Correction

AFEC_CECRAFEC Channel Error Correction Register

Address: 0x4003C0D8
Reset: 0x00000000
Access: read/write
Size: 32-bit

12 fields

Field	Bits	What it does
ECORR11	11	Error Correction Enable for channel 11
ECORR10	10	Error Correction Enable for channel 10
ECORR9	9	Error Correction Enable for channel 9
ECORR8	8	Error Correction Enable for channel 8
ECORR7	7	Error Correction Enable for channel 7
ECORR6	6	Error Correction Enable for channel 6
ECORR5	5	Error Correction Enable for channel 5
ECORR4	4	Error Correction Enable for channel 4
ECORR3	3	Error Correction Enable for channel 3
ECORR2	2	Error Correction Enable for channel 2
ECORR1	1	Error Correction Enable for channel 1
ECORR0	0	Error Correction Enable for channel 0

AFEC_WPMRAFEC Write Protection Mode Register

Address: 0x4003C0E4
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
WPEN	0	Write Protection Enable
WPKEY	31:8	Write Protect KEY `4277315` Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

AFEC_WPSRAFEC Write Protection Status Register

Address: 0x4003C0E8
Reset: 0x00000000
Access: read only
Size: 32-bit

2 fields

Field	Bits	What it does
WPVSRC	23:8	Write Protect Violation Source
WPVS	0	Write Protect Violation Status