The 35 registers of SCB (System Control Block), from 0xE000ED00, with their reset value and every field. The ATSAMV71Q21RT has 3003 registers in 69 peripherals, one page each.
SCB System Control Block
CPUIDCPUID Base Register
Address
0xE000ED00
Reset
0x411FC271
Access
read only
Size
32-bit
5 fields
Field
Bits
What it does
VARIANT
23:20
Indicates processor revision: 0x2 = Revision 2
ARCHITECTURE
19:16
Indicates architecture. Reads as 0xF
PARTNO
15:4
Indicates part number
REVISION
3:0
Indicates patch release: 0x0 = Patch 0
IMPLEMENTER
31:24
Implementer code
ICSRInterrupt Control and State Register
Address
0xE000ED04
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
Field
Bits
What it does
PENDSVSET
28
Sets the PendSV exception as pending, or reads the current state of the exception
0 write: no effect; read: PendSV exception is not pending
1 write: changes PendSV exception state to pending; read: PendSV exception is pending
PENDSVCLR
27
Removes the pending status of the PendSV exception
0 no effect
1 removes the pending state from the PendSV exception
PENDSTSET
26
Sets the SysTick exception as pending, or reads the current state of the exception
0 write: no effect; read: SysTick exception is not pending
1 write: changes SysTick exception state to pending; read: SysTick exception is pending
PENDSTCLR
25
Removes the pending status of the SysTick exception
0 no effect
1 removes the pending state from the SysTick exception
ISRPREEMPT
23
Indicates whether a pending exception will be serviced on exit from debug halt state
0 Will not service
1 Will service a pending exception
ISRPENDING
22
Is external interrupt, generated by the NVIC, pending
VECTPENDING
17:12
Exception number of the highest priority pending enabled exception
RETTOBASE
11
Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR
0 there are preempted active exceptions to execute
1 there are no active exceptions, or the currently-executing exception is the only active exception
VECTACTIVE
8:0
Active exception number
NMIPENDSET
31
Makes the NMI exception active, or reads the state of the exception
0 write: no effect; read: NMI exception is not pending
1 write: changes NMI exception state to pending; read: NMI exception is pending
VTORVector Table Offset Register
Address
0xE000ED08
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TBLOFF
31:7
Bits[31:7] of the vector table address
AIRCRApplication Interrupt and Reset Control Register
Address
0xE000ED0C
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
ENDIANNESS
15
Memory system endianness
0 Little-endian
1 Big-endian
PRIGROUP
10:8
Interrupt priority grouping field. This field determines the split of group priority from subpriority.
SYSRESETREQ
2
System Reset Request
0 no system reset request
1 asserts a signal to the outer system that requests a reset
VECTCLRACTIVE
1
Clears all active state information for fixed and configurable exceptions
VECTRESET
0
Writing 1 to this bit causes a local system reset
VECTKEY
31:16
Vector key
SCRSystem Control Register
Address
0xE000ED10
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
SEVONPEND
4
Determines whether an interrupt transition from inactive state to pending state is a wakeup event
0 only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
1 enabled events and all interrupts, including disabled interrupts, can wakeup the processor
SLEEPDEEP
2
Provides a qualifying hint indicating that waking from sleep might take longer
0 sleep
1 deep sleep
SLEEPONEXIT
1
Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state
0 o not sleep when returning to Thread mode
1 enter sleep, or deep sleep, on return from an ISR
CCRConfiguration and Control Register
Address
0xE000ED14
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
BP
18
Branch prediction enable bi
IC
17
Instruction cache enable bi
DC
16
Cache enable bit
STKALIGN
9
Indicates stack alignment on exception entry
0 4-byte aligned
1 8-byte aligned
BFHFNMIGN
8
Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions.
0 data bus faults caused by load and store instructions cause a lock-up
1 handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions
DIV_0_TRP
4
Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0
0 do not trap divide by 0
1 trap divide by 0
UNALIGN_TRP
3
Enables unaligned access traps
0 do not trap unaligned halfword and word accesses
1 trap unaligned halfword and word accesses
USERSETMPEND
1
Enables unprivileged software access to the STIR
0 disable
1 enable
NONBASETHRDENA
0
Controls whether the processor can enter Thread mode with exceptions active
0 processor can enter Thread mode only when no exception is active
1 processor can enter Thread mode from any level under the control of an EXC_RETURN value
SHPR1System Handler Priority Register 1
Address
0xE000ED18
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
PRI_6
23:16
Priority of system handler 6, UsageFault
PRI_5
15:8
Priority of system handler 5, BusFault
PRI_4
7:0
Priority of system handler 4, MemManage
SHPR2System Handler Priority Register 2
Address
0xE000ED1C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
PRI_11
31:24
Priority of system handler 11, SVCall
SHPR3System Handler Priority Register 3
Address
0xE000ED20
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
PRI_14
23:16
Priority of system handler 14, PendSV
PRI_12
7:0
Priority of system handler 12, SysTick
PRI_15
31:24
Priority of system handler 15, SysTick exception
SHCSRSystem Handler Control and State Register
Address
0xE000ED24
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
USGFAULTENA
18
0 disable the exception
1 enable the exception
BUSFAULTENA
17
0 disable the exception
1 enable the exception
MEMFAULTENA
16
0 disable the exception
1 enable the exception
SVCALLPENDED
15
0 exception is not pending
1 exception is pending
BUSFAULTPENDED
14
0 exception is not pending
1 exception is pending
MEMFAULTPENDED
13
0 exception is not pending
1 exception is pending
USGFAULTPENDED
12
0 exception is not pending
1 exception is pending
SYSTICKACT
11
0 exception is not active
1 exception is active
PENDSVACT
10
0 exception is not active
1 exception is active
MONITORACT
8
0 exception is not active
1 exception is active
SVCALLACT
7
0 exception is not active
1 exception is active
USGFAULTACT
3
0 exception is not active
1 exception is active
BUSFAULTACT
1
0 exception is not active
1 exception is active
MEMFAULTACT
0
0 exception is not active
1 exception is active
CFSRConfigurable Fault Status Registers
Address
0xE000ED28
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
Field
Bits
What it does
DIVBYZERO
25
0 no divide by zero fault, or divide by zero trapping not enabled
1 the processor has executed an SDIV or UDIV instruction with a divisor of 0
UNALIGNED
24
0 no unaligned access fault, or unaligned access trapping not enabled
1 the processor has made an unaligned memory access
NOCP
19
0 no UsageFault caused by attempting to access a coprocessor
1 the processor has attempted to access a coprocessor
INVPC
18
0 no invalid PC load UsageFault
1 the processor has attempted an illegal load of EXC_RETURN to the PC
INVSTATE
17
0 no invalid state UsageFault
1 the processor has attempted to execute an instruction that makes illegal use of the EPSR
UNDEFINSTR
16
0 no undefined instruction UsageFault
1 the processor has attempted to execute an undefined instruction
BFARVALID
15
0 value in BFAR is not a valid fault address
1 BFAR holds a valid fault address
LSPERR
13
0 No bus fault occurred during floating-point lazy state preservation
1 A bus fault occurred during floating-point lazy state preservation
STKERR
12
0 no stacking fault
1 stacking for an exception entry has caused one or more BusFaults
UNSTKERR
11
0 no unstacking fault
1 unstack for an exception return has caused one or more BusFaults
IMPRECISERR
10
0 no imprecise data bus error
1 a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error
PRECISERR
9
0 no precise data bus error
1 a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault
IBUSERR
8
0 no instruction bus error
1 instruction bus error
MMARVALID
7
0 value in MMAR is not a valid fault address
1 MMAR holds a valid fault address
MLSPERR
5
0 No MemManage fault occurred during floating-point lazy state preservation
1 A MemManage fault occurred during floating-point lazy state preservation
MSTKERR
4
0 no stacking fault
1 stacking for an exception entry has caused one or more access violations
MUNSTKERR
3
0 no unstacking fault
1 unstack for an exception return has caused one or more access violations
DACCVIOL
1
0 no data access violation fault
1 the processor attempted a load or store at a location that does not permit the operation
IACCVIOL
0
0 no instruction access violation fault
1 the processor attempted an instruction fetch from a location that does not permit execution
HFSRHardFault Status register
Address
0xE000ED2C
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
FORCED
30
Indicates that a fault with configurable priority has been escalated to a HardFault exception
0 no forced HardFault
1 forced HardFault
VECTTBL
1
Indicates when a fault has occurred because of a vector table read error on exception processing
0 no BusFault on vector table read
1 BusFault on vector table read
DEBUGEVT
31
Indicates when a Debug event has occurred
DFSRDebug Fault Status Register
Address
0xE000ED30
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
EXTERNAL
4
debug event generated because of the assertion of an external debug request
0 No EDBGRQ debug event
1 EDBGRQ debug event
VCATCH
3
triggering of a Vector catch
0 No Vector catch triggered
1 Vector catch triggered
DWTTRAP
2
debug event generated by the DWT
0 No current debug events generated by the DWT
1 At least one current debug event generated by the DWT
BKPT
1
debug event generated by BKPT instruction execution or a breakpoint match in FPB
0 No current breakpoint debug event
1 At least one current breakpoint debug event
HALTED
0
debug event generated by
0 No active halt request debug event
1 Halt request debug event active
MMFARMemManage Fault Address Register
Address
0xE000ED34
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
ADDRESS
31:0
Data address for an MPU fault
BFARBusFault Address Register
Address
0xE000ED38
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
ADDRESS
31:0
Data address for a precise bus fault
AFSRAuxiliary Fault Status Register
Address
0xE000ED3C
Reset
0x00000000
Access
read/write
Size
32-bit
CLIDRCache Level ID Register
Address
0xE000ED78
Reset
0x09000003
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
LoU
29:27
Level of Unification
0 if neither instruction nor data cache is implemented
1 if either cache is implemented
LoC
26:24
Level of Coherency
0 if neither instruction nor data cache is implemented
1 if either cache is implemented
CTRCache Type Register
Address
0xE000ED7C
Reset
0x8303C003
Access
read only
Size
32-bit
5 fields
Field
Bits
What it does
CWG
27:24
Cache Writeback Granule
ERG
23:20
Exclusives Reservation Granule
DMINLINE
19:16
Smallest cache line of all the data and unified caches under the core control
IMINLINE
3:0
Smallest cache line of all the instruction caches under the control of the processor
FORMAT
31:29
Register format
CCSIDRCache Size ID Register
Address
0xE000ED80
Reset
0x00000000
Access
read only
Size
32-bit
7 fields
Field
Bits
What it does
WB
30
Write-Back support
RA
29
Read allocation support
WA
28
Write allocation support
NumSets
27:12
number of sets
Associativity
11:3
number of ways
LineSize
2:0
number of words in each cache line
WT
31
Write-Through support
CSSELRCache Size Selection Register
Address
0xE000ED84
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
LEVEL
3:1
cache level selected
IND
0
selection of instruction or data cache
0 Data cache
1 Instruction cache
CPACRCoprocessor Access Control Register
Address
0xE000ED88
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
CP11
23:22
Access privileges for coprocessor 11.
CP10
21:20
Access privileges for coprocessor 10.
ICIALLUI-cache invalidate all to PoU
Address
0xE000EE50
Reset
0x00000000
Access
write only
Size
32-bit
ICIMVAUI-cache invalidate by MVA to PoU
Address
0xE000EE58
Reset
0x00000000
Access
write only
Size
32-bit
DCIMVACD-cache invalidate by MVA to PoC
Address
0xE000EE5C
Reset
0x00000000
Access
write only
Size
32-bit
DCISWD-cache invalidate by set-way
Address
0xE000EE60
Reset
0x00000000
Access
write only
Size
32-bit
DCCMVAUD-cache clean by MVA to PoU
Address
0xE000EE64
Reset
0x00000000
Access
write only
Size
32-bit
DCCMVACD-cache clean by MVA to PoC
Address
0xE000EE68
Reset
0x00000000
Access
write only
Size
32-bit
DCCSWD-cache clean by set-way
Address
0xE000EE6C
Reset
0x00000000
Access
write only
Size
32-bit
DCCIMVACD-cache clean and invalidate by MVA to PoC
Address
0xE000EE70
Reset
0x00000000
Access
write only
Size
32-bit
DCCISWD-cache clean and invalidate by set-way
Address
0xE000EE74
Reset
0x00000000
Access
write only
Size
32-bit
BPIALLBranch predictor invalidate all
Address
0xE000EE78
Reset
0x00000000
Access
write only
Size
32-bit
STIRSoftware Trigger Interrupt Register
Address
0xE000EF00
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
INTID
8:0
Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3.
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