The 13 registers of SDRAMC (SDRAM Controller), from 0x40084000, with their reset value and every field. The ATSAMV71Q21RT has 3003 registers in 69 peripherals, one page each.
SDRAMC SDRAM Controller
SDRAMC_MRSDRAMC Mode Register
Address
0x40084000
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
MODE
2:0
SDRAMC Command Mode
0 Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, the command must be followed by a write to the SDRAM.
1 The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM.
2 The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM.
3 The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM.
4 The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, the command must be followed by a write to the SDRAM.
5 The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power
6 Deep Power-down mode. Enters Deep Power-down mode.
SDRAMC_TRSDRAMC Refresh Timer Register
Address
0x40084004
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
COUNT
11:0
SDRAMC Refresh Timer Count
SDRAMC_CRSDRAMC Configuration Register
Address
0x40084008
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
TRAS
27:24
Active to Precharge Delay
TRCD
23:20
Row to Column Delay
TRP
19:16
Row Precharge Delay
TRC_TRFC
15:12
Row Cycle Delay and Row Refresh Cycle
TWR
11:8
Write Recovery Delay
DBW
7
Data Bus Width
CAS
6:5
CAS Latency
1 1 cycle CAS latency
2 2 cycle CAS latency
3 3 cycle CAS latency
NB
4
Number of Banks
0 2 banks
1 4 banks
NR
3:2
Number of Row Bits
0 11 row bits
1 12 row bits
2 13 row bits
NC
1:0
Number of Column Bits
0 8 column bits
1 9 column bits
2 10 column bits
3 11 column bits
TXSR
31:28
Exit Self-Refresh to Active Delay
SDRAMC_LPRSDRAMC Low Power Register
Address
0x40084010
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
TIMEOUT
13:12
Time to Define When Low-power Mode Is Enabled
0 The SDRAMC activates the SDRAM Low-power mode immediately after the end of the last transfer.
1 The SDRAMC activates the SDRAM Low-power mode 64 clock cycles after the end of the last transfer.
2 The SDRAMC activates the SDRAM Low-power mode 128 clock cycles after the end of the last transfer.
DS
11:10
Drive Strength (only for low-power SDRAM)
TCSR
9:8
Temperature Compensated Self-Refresh (only for low-power SDRAM)
PASR
6:4
Partial Array Self-refresh (only for low-power SDRAM)
LPCB
1:0
Low-power Configuration Bits
0 The low-power feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device.
1 The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self-refresh mode when accessed and enters it after the access.
2 The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down mode when accessed and enters it after the access.
3 The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM.
SDRAMC_IERSDRAMC Interrupt Enable Register
Address
0x40084014
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
RES
0
Refresh Error Interrupt Enable
SDRAMC_IDRSDRAMC Interrupt Disable Register
Address
0x40084018
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
RES
0
Refresh Error Interrupt Disable
SDRAMC_IMRSDRAMC Interrupt Mask Register
Address
0x4008401C
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
RES
0
Refresh Error Interrupt Mask
SDRAMC_ISRSDRAMC Interrupt Status Register
Address
0x40084020
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
RES
0
Refresh Error Status (cleared on read)
SDRAMC_MDRSDRAMC Memory Device Register
Address
0x40084024
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
MD
1:0
Memory Device Type
0 SDRAM
1 Low-power SDRAM
SDRAMC_CFR1SDRAMC Configuration Register 1
Address
0x40084028
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
UNAL
8
Support Unaligned Access
0 Unaligned access is not supported.
1 Unaligned access is supported.
TMRD
3:0
Load Mode Register Command to Active or Refresh Command
BETA