ATxmega128B1 LCD registers

The 30 registers of LCD (LCD Controller), from 0xD00, with their reset value and every field. The ATxmega128B1 has 535 registers in 50 peripherals, one page each.

LCD LCD Controller

CTRLAControl Register A

Address
0xD00
Reset
0x00
Access
read/write
  1. 7ENABLE
  2. 6XBIAS
  3. 5DATCLK
  4. 4COMSWP
  5. 3SEGSWP
  6. 2CLRDT
  7. 1SEGON
  8. 0BLANK
8 fields
FieldBitsWhat it does
ENABLE7LCD Enable
XBIAS6External Register Bias Generation
DATCLK5Data Register Lock
COMSWP4Common Bus Swap
SEGSWP3Segment Bus Swap
CLRDT2Clear Data Register
SEGON1Segments On
BLANK0Blanking Display Mode

CTRLBControl Register B

Address
0xD01
Reset
0x00
Access
read/write
  1. 7PRESC
  2. 6CLKDIV2
  3. 5CLKDIV1
  4. 4CLKDIV0
  5. 3LPWAV
  6. 2–
  7. 1DUTY1
  8. 0DUTY0
4 fields
FieldBitsWhat it does
PRESC7LCD Prescaler Select
  • 0 clk_lcd/8
  • 1 clk_lcd/16
CLKDIV6:4LCD Clock Divide
  • 0 frame rate of 256 Hz
  • 1 frame rate of 128 Hz
  • 2 frame rate of 83.5 Hz
  • 3 frame rate of 64 Hz
  • 4 frame rate of 51.2 Hz
  • 5 frame rate of 42.7 Hz
  • 6 frame rate of 36.6 Hz
  • 7 frame rate of 32 Hz
LPWAV3Low Power Waveform
DUTY1:0Duty Select
  • 0 Duty=1/4, Bias=1/3, COM0:3
  • 1 Duty=Static, Bias=Static, COM0
  • 2 Duty=1/2, Bias=1/3, COM0:1
  • 3 Duty=1/3, Bias=1/3, COM0:2

CTRLCControl Register C

Address
0xD02
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5PMSK5
  4. 4PMSK4
  5. 3PMSK3
  6. 2PMSK2
  7. 1PMSK1
  8. 0PMSK0
1 field
FieldBitsWhat it does
PMSK5:0LCD Port Mask

INTCTRLInterrupt Enable Register

Address
0xD03
Reset
0x00
Access
read/write
  1. 7XIME4
  2. 6XIME3
  3. 5XIME2
  4. 4XIME1
  5. 3XIME0
  6. 2–
  7. 1FCINTLVL1
  8. 0FCINTLVL0
2 fields
FieldBitsWhat it does
XIME7:3eXtended Interrupt Mode Enable
FCINTLVL1:0Interrupt Level
  • 0 Interrupt disabled
  • 1 Low level
  • 2 Medium level
  • 3 High level

INTFLAGInterrupt Flag Register

Address
0xD04
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0FCIF
1 field
FieldBitsWhat it does
FCIF0LCD Frame Completed Interrupt Flag

CTRLDControl Register D

Address
0xD05
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3BLINKEN
  6. 2–
  7. 1BLINKRATE1
  8. 0BLINKRATE0
2 fields
FieldBitsWhat it does
BLINKEN3Blink Enable
BLINKRATE1:0LCD Blink Rate
  • 0 4Hz Blink Rate
  • 1 2Hz Blink Rate
  • 2 1Hz Blink Rate
  • 3 0.5Hz Blink Rate

CTRLEControl Register E

Address
0xD06
Reset
0x00
Access
read/write
  1. 7BPS13
  2. 6BPS12
  3. 5BPS11
  4. 4BPS10
  5. 3BPS03
  6. 2BPS02
  7. 1BPS01
  8. 0BPS00
2 fields
FieldBitsWhat it does
BPS17:4Blink Pixel Selection 1
BPS03:0Blink Pixel Selection 0

CTRLFControl Register F

Address
0xD07
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5FCONT5
  4. 4FCONT4
  5. 3FCONT3
  6. 2FCONT2
  7. 1FCONT1
  8. 0FCONT0
1 field
FieldBitsWhat it does
FCONT5:0Fine Contrast

CTRLGControl Register G

Address
0xD08
Reset
0x00
Access
read/write
  1. 7TDG1
  2. 6TDG0
  3. 5STSEG5
  4. 4STSEG4
  5. 3STSEG3
  6. 2STSEG2
  7. 1STSEG1
  8. 0STSEG0
2 fields
FieldBitsWhat it does
TDG7:6Type of Digit
  • 0 7-segment with 3 COMs
  • 1 7-segment with 4 COMs
  • 2 14-segment with 4 COMs
  • 3 16-segment with 3 COMs
STSEG5:0Start Segment

CTRLHControl Register H

Address
0xD09
Reset
0x00
Access
read/write
  1. 7DEC
  2. 6DCODE6
  3. 5DCODE5
  4. 4DCODE4
  5. 3DCODE3
  6. 2DCODE2
  7. 1DCODE1
  8. 0DCODE0
2 fields
FieldBitsWhat it does
DEC7Decrement of Start Segment
DCODE6:0Display Code

DATA0LCD Data Register 0

Address
0xD10
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA1LCD Data Register 1

Address
0xD11
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA2LCD Data Register 2

Address
0xD12
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA3LCD Data Register 3

Address
0xD13
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA4LCD Data Register 4

Address
0xD14
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA5LCD Data Register 5

Address
0xD15
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA6LCD Data Register 6

Address
0xD16
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA7LCD Data Register 7

Address
0xD17
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA8LCD Data Register 8

Address
0xD18
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA9LCD Data Register 9

Address
0xD19
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA10LCD Data Register 10

Address
0xD1A
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA11LCD Data Register 11

Address
0xD1B
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA12LCD Data Register 12

Address
0xD1C
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA13LCD Data Register 13

Address
0xD1D
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA14LCD Data Register 14

Address
0xD1E
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA15LCD Data Register 15

Address
0xD1F
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA16LCD Data Register 16

Address
0xD20
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA17LCD Data Register 17

Address
0xD21
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA18LCD Data Register 18

Address
0xD22
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA19LCD Data Register 19

Address
0xD23
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–