ATxmega16C4 PORTA registers

The 22 registers of PORTA (I/O Port Configuration), from 0x600, with their reset value and every field. The ATxmega16C4 has 463 registers in 47 peripherals, one page each.

PORTA I/O Port Configuration

DIRI/O Port Data Direction

Address: 0x600
Reset: 0x00
Access: read/write

7DIR7
6DIR6
5DIR5
4DIR4
3DIR3
2DIR2
1DIR1
0DIR0

DIRSETI/O Port Data Direction Set

Address: 0x601
Reset: 0x00
Access: read/write

7DIRSET7
6DIRSET6
5DIRSET5
4DIRSET4
3DIRSET3
2DIRSET2
1DIRSET1
0DIRSET0

DIRCLRI/O Port Data Direction Clear

Address: 0x602
Reset: 0x00
Access: read/write

7DIRCLR7
6DIRCLR6
5DIRCLR5
4DIRCLR4
3DIRCLR3
2DIRCLR2
1DIRCLR1
0DIRCLR0

DIRTGLI/O Port Data Direction Toggle

Address: 0x603
Reset: 0x00
Access: read/write

7DIRTGL7
6DIRTGL6
5DIRTGL5
4DIRTGL4
3DIRTGL3
2DIRTGL2
1DIRTGL1
0DIRTGL0

OUTI/O Port Output

Address: 0x604
Reset: 0x00
Access: read/write

7OUT7
6OUT6
5OUT5
4OUT4
3OUT3
2OUT2
1OUT1
0OUT0

OUTSETI/O Port Output Set

Address: 0x605
Reset: 0x00
Access: read/write

7OUTSET7
6OUTSET6
5OUTSET5
4OUTSET4
3OUTSET3
2OUTSET2
1OUTSET1
0OUTSET0

OUTCLRI/O Port Output Clear

Address: 0x606
Reset: 0x00
Access: read/write

7OUTCLR7
6OUTCLR6
5OUTCLR5
4OUTCLR4
3OUTCLR3
2OUTCLR2
1OUTCLR1
0OUTCLR0

OUTTGLI/O Port Output Toggle

Address: 0x607
Reset: 0x00
Access: read/write

7OUTTGL7
6OUTTGL6
5OUTTGL5
4OUTTGL4
3OUTTGL3
2OUTTGL2
1OUTTGL1
0OUTTGL0

INI/O port Input

Address: 0x608
Reset: 0x00
Access: read/write

7IN7
6IN6
5IN5
4IN4
3IN3
2IN2
1IN1
0IN0

INTCTRLInterrupt Control Register

Address: 0x609
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3INT1LVL1
2INT1LVL0
1INT0LVL1
0INT0LVL0

2 fields

Field	Bits	What it does
INT1LVL	3:2	Port Interrupt 1 Level `0` Interrupt Disabled `1` Low Level `2` Medium Level `3` High Level
INT0LVL	1:0	Port Interrupt 0 Level `0` Interrupt Disabled `1` Low Level `2` Medium Level `3` High Level

INT0MASKPort Interrupt 0 Mask

Address: 0x60A
Reset: 0x00
Access: read/write

7INT0MASK7
6INT0MASK6
5INT0MASK5
4INT0MASK4
3INT0MASK3
2INT0MASK2
1INT0MASK1
0INT0MASK0

INT1MASKPort Interrupt 1 Mask

Address: 0x60B
Reset: 0x00
Access: read/write

7INT1MASK7
6INT1MASK6
5INT1MASK5
4INT1MASK4
3INT1MASK3
2INT1MASK2
1INT1MASK1
0INT1MASK0

INTFLAGSInterrupt Flag Register

Address: 0x60C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1INT1IF
0INT0IF

2 fields

Field	Bits	What it does
INT1IF	1	Port Interrupt 1 Flag
INT0IF	0	Port Interrupt 0 Flag

REMAPI/O Port Pin Remap Register

Address: 0x60E
Reset: 0x00
Access: read/write

7–
6–
5SPI
4USART0
3TC0D
2TC0C
1TC0B
0TC0A

6 fields

Field	Bits	What it does
SPI	5	SPI
USART0	4	USART0
TC0D	3	Timer/Counter 0 Output Compare D
TC0C	2	Timer/Counter 0 Output Compare C
TC0B	1	Timer/Counter 0 Output Compare B
TC0A	0	Timer/Counter 0 Output Compare A

PIN0CTRLPin 0 Control Register

Address: 0x610
Reset: 0x00
Access: read/write

7SRLEN
6INVEN
5OPC2
4OPC1
3OPC0
2ISC2
1ISC1
0ISC0

4 fields

Field	Bits	What it does
SRLEN	7	Slew Rate Enable
INVEN	6	Inverted I/O Enable
OPC	5:3	Output/Pull Configuration `0` Totempole `1` Totempole w/ Bus keeper on Input and Output `2` Totempole w/ Pull-down on Input `3` Totempole w/ Pull-up on Input `4` Wired OR `5` Wired AND `6` Wired OR w/ Pull-down `7` Wired AND w/ Pull-up
ISC	2:0	Input/Sense Configuration `0` Sense Both Edges `1` Sense Rising Edge `2` Sense Falling Edge `3` Sense Level (Transparent For Events) `7` Disable Digital Input Buffer

PIN1CTRLPin 1 Control Register

Address: 0x611
Reset: 0x00
Access: read/write

7SRLEN
6INVEN
5OPC2
4OPC1
3OPC0
2ISC2
1ISC1
0ISC0

4 fields

Field	Bits	What it does
SRLEN	7	Slew Rate Enable
INVEN	6	Inverted I/O Enable
OPC	5:3	Output/Pull Configuration `0` Totempole `1` Totempole w/ Bus keeper on Input and Output `2` Totempole w/ Pull-down on Input `3` Totempole w/ Pull-up on Input `4` Wired OR `5` Wired AND `6` Wired OR w/ Pull-down `7` Wired AND w/ Pull-up
ISC	2:0	Input/Sense Configuration `0` Sense Both Edges `1` Sense Rising Edge `2` Sense Falling Edge `3` Sense Level (Transparent For Events) `7` Disable Digital Input Buffer

PIN2CTRLPin 2 Control Register

Address: 0x612
Reset: 0x00
Access: read/write

7SRLEN
6INVEN
5OPC2
4OPC1
3OPC0
2ISC2
1ISC1
0ISC0

4 fields

Field	Bits	What it does
SRLEN	7	Slew Rate Enable
INVEN	6	Inverted I/O Enable
OPC	5:3	Output/Pull Configuration `0` Totempole `1` Totempole w/ Bus keeper on Input and Output `2` Totempole w/ Pull-down on Input `3` Totempole w/ Pull-up on Input `4` Wired OR `5` Wired AND `6` Wired OR w/ Pull-down `7` Wired AND w/ Pull-up
ISC	2:0	Input/Sense Configuration `0` Sense Both Edges `1` Sense Rising Edge `2` Sense Falling Edge `3` Sense Level (Transparent For Events) `7` Disable Digital Input Buffer

PIN3CTRLPin 3 Control Register

Address: 0x613
Reset: 0x00
Access: read/write

7SRLEN
6INVEN
5OPC2
4OPC1
3OPC0
2ISC2
1ISC1
0ISC0

4 fields

Field	Bits	What it does
SRLEN	7	Slew Rate Enable
INVEN	6	Inverted I/O Enable
OPC	5:3	Output/Pull Configuration `0` Totempole `1` Totempole w/ Bus keeper on Input and Output `2` Totempole w/ Pull-down on Input `3` Totempole w/ Pull-up on Input `4` Wired OR `5` Wired AND `6` Wired OR w/ Pull-down `7` Wired AND w/ Pull-up
ISC	2:0	Input/Sense Configuration `0` Sense Both Edges `1` Sense Rising Edge `2` Sense Falling Edge `3` Sense Level (Transparent For Events) `7` Disable Digital Input Buffer

PIN4CTRLPin 4 Control Register

Address: 0x614
Reset: 0x00
Access: read/write

7SRLEN
6INVEN
5OPC2
4OPC1
3OPC0
2ISC2
1ISC1
0ISC0

4 fields

Field	Bits	What it does
SRLEN	7	Slew Rate Enable
INVEN	6	Inverted I/O Enable
OPC	5:3	Output/Pull Configuration `0` Totempole `1` Totempole w/ Bus keeper on Input and Output `2` Totempole w/ Pull-down on Input `3` Totempole w/ Pull-up on Input `4` Wired OR `5` Wired AND `6` Wired OR w/ Pull-down `7` Wired AND w/ Pull-up
ISC	2:0	Input/Sense Configuration `0` Sense Both Edges `1` Sense Rising Edge `2` Sense Falling Edge `3` Sense Level (Transparent For Events) `7` Disable Digital Input Buffer

PIN5CTRLPin 5 Control Register

Address: 0x615
Reset: 0x00
Access: read/write

7SRLEN
6INVEN
5OPC2
4OPC1
3OPC0
2ISC2
1ISC1
0ISC0

4 fields

Field	Bits	What it does
SRLEN	7	Slew Rate Enable
INVEN	6	Inverted I/O Enable
OPC	5:3	Output/Pull Configuration `0` Totempole `1` Totempole w/ Bus keeper on Input and Output `2` Totempole w/ Pull-down on Input `3` Totempole w/ Pull-up on Input `4` Wired OR `5` Wired AND `6` Wired OR w/ Pull-down `7` Wired AND w/ Pull-up
ISC	2:0	Input/Sense Configuration `0` Sense Both Edges `1` Sense Rising Edge `2` Sense Falling Edge `3` Sense Level (Transparent For Events) `7` Disable Digital Input Buffer

PIN6CTRLPin 6 Control Register

Address: 0x616
Reset: 0x00
Access: read/write

7SRLEN
6INVEN
5OPC2
4OPC1
3OPC0
2ISC2
1ISC1
0ISC0

4 fields

Field	Bits	What it does
SRLEN	7	Slew Rate Enable
INVEN	6	Inverted I/O Enable
OPC	5:3	Output/Pull Configuration `0` Totempole `1` Totempole w/ Bus keeper on Input and Output `2` Totempole w/ Pull-down on Input `3` Totempole w/ Pull-up on Input `4` Wired OR `5` Wired AND `6` Wired OR w/ Pull-down `7` Wired AND w/ Pull-up
ISC	2:0	Input/Sense Configuration `0` Sense Both Edges `1` Sense Rising Edge `2` Sense Falling Edge `3` Sense Level (Transparent For Events) `7` Disable Digital Input Buffer

PIN7CTRLPin 7 Control Register

Address: 0x617
Reset: 0x00
Access: read/write

7SRLEN
6INVEN
5OPC2
4OPC1
3OPC0
2ISC2
1ISC1
0ISC0

4 fields

Field	Bits	What it does
SRLEN	7	Slew Rate Enable
INVEN	6	Inverted I/O Enable
OPC	5:3	Output/Pull Configuration `0` Totempole `1` Totempole w/ Bus keeper on Input and Output `2` Totempole w/ Pull-down on Input `3` Totempole w/ Pull-up on Input `4` Wired OR `5` Wired AND `6` Wired OR w/ Pull-down `7` Wired AND w/ Pull-up
ISC	2:0	Input/Sense Configuration `0` Sense Both Edges `1` Sense Rising Edge `2` Sense Falling Edge `3` Sense Level (Transparent For Events) `7` Disable Digital Input Buffer