ATxmega192A3 NVM registers

The 12 registers of NVM (Non Volatile Memory Controller), from 0x1C0, with their reset value and every field. The ATxmega192A3 has 599 registers in 63 peripherals, one page each.

NVM Non Volatile Memory Controller

ADDR0Address Register 0

Address
0x1C0
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

ADDR1Address Register 1

Address
0x1C1
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

ADDR2Address Register 2

Address
0x1C2
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA0Data Register 0

Address
0x1C4
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA1Data Register 1

Address
0x1C5
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DATA2Data Register 2

Address
0x1C6
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

CMDCommand

Address
0x1CA
Reset
0x00
Access
read/write
  1. 7–
  2. 6CMD6
  3. 5CMD5
  4. 4CMD4
  5. 3CMD3
  6. 2CMD2
  7. 1CMD1
  8. 0CMD0
1 field
FieldBitsWhat it does
CMD6:0Command
  • 0 Noop/Ordinary LPM
  • 1 Read user signature row
  • 2 Read calibration row
  • 6 Read EEPROM
  • 7 Read fuse byte
  • 8 Write lock bits
  • 24 Erase user signature row
  • 26 Write user signature row
  • 32 Erase Application Section
  • 34 Erase Application Section page
  • 35 Load Flash page buffer
  • 36 Write Application Section page
  • 37 Erase-and-write Application Section page
  • 38 Erase/flush Flash page buffer
  • 42 Erase Boot Section page
  • 43 Erase Flash Page
  • 44 Write Boot Section page
  • 45 Erase-and-write Boot Section page
  • 46 Write Flash Page
  • 47 Erase-and-write Flash Page
  • 48 Erase EEPROM
  • 50 Erase EEPROM page
  • 51 Load EEPROM page buffer
  • 52 Write EEPROM page
  • 53 Erase-and-write EEPROM page
  • 54 Erase/flush EEPROM page buffer
  • 56 Generate Application section CRC
  • 57 Generate Boot Section CRC
  • 64 Erase Chip
  • 67 Read NVM
  • 76 Write Fuse byte
  • 104 Erase Boot Section
  • 120 Generate Flash Range CRC

CTRLAControl Register A

Address
0x1CB
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0CMDEX
1 field
FieldBitsWhat it does
CMDEX0Command Execute

CTRLBControl Register B

Address
0x1CC
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3EEMAPEN
  6. 2FPRM
  7. 1EPRM
  8. 0SPMLOCK
4 fields
FieldBitsWhat it does
EEMAPEN3EEPROM Mapping Enable
FPRM2Flash Power Reduction Enable
EPRM1EEPROM Power Reduction Enable
SPMLOCK0SPM Lock

INTCTRLInterrupt Control

Address
0x1CD
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3SPMLVL1
  6. 2SPMLVL0
  7. 1EELVL1
  8. 0EELVL0
2 fields
FieldBitsWhat it does
SPMLVL3:2SPM Interrupt Level
  • 0 Interrupt disabled
  • 1 Low level
  • 2 Medium level
  • 3 High level
EELVL1:0EEPROM Interrupt Level
  • 0 Interrupt disabled
  • 1 Low level
  • 2 Medium level
  • 3 High level

STATUSStatus

Address
0x1CF
Reset
0x00
Access
read/write
  1. 7NVMBUSY
  2. 6FBUSY
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1EELOAD
  8. 0FLOAD
4 fields
FieldBitsWhat it does
NVMBUSY7Non-volatile Memory Busy
FBUSY6Flash Memory Busy
EELOAD1EEPROM Page Buffer Active Loading
FLOAD0Flash Page Buffer Active Loading

LOCKBITSLock Bits

Address
0x1D0
Reset
0x00
Access
read/write
  1. 7BLBB1
  2. 6BLBB0
  3. 5BLBA1
  4. 4BLBA0
  5. 3BLBAT1
  6. 2BLBAT0
  7. 1LB1
  8. 0LB0
4 fields
FieldBitsWhat it does
BLBB7:6Boot Lock Bits - Boot Section
  • 0 Read and write not allowed
  • 1 Read not allowed
  • 2 Write not allowed
  • 3 No locks
BLBA5:4Boot Lock Bits - Application Section
  • 0 Read and write not allowed
  • 1 Read not allowed
  • 2 Write not allowed
  • 3 No locks
BLBAT3:2Boot Lock Bits - Application Table
  • 0 Read and write not allowed
  • 1 Read not allowed
  • 2 Write not allowed
  • 3 No locks
LB1:0Lock Bits
  • 0 Read and write not allowed
  • 2 Write not allowed
  • 3 No locks