ATxmega256A3U PORTCFG registers

The 5 registers of PORTCFG (Port Configuration), from 0xB0, with their reset value and every field. The ATxmega256A3U has 707 registers in 67 peripherals, one page each.

PORTCFG Port Configuration

MPCMASKMulti-pin Configuration Mask

Address
0xB0
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

VPCTRLAVirtual Port Control Register A

Address
0xB2
Reset
0x00
Access
read/write
  1. 7VP1MAP3
  2. 6VP1MAP2
  3. 5VP1MAP1
  4. 4VP1MAP0
  5. 3VP0MAP3
  6. 2VP0MAP2
  7. 1VP0MAP1
  8. 0VP0MAP0
2 fields
FieldBitsWhat it does
VP1MAP7:4Virtual Port 1 Mapping
  • 0 Mapped To PORTA
  • 1 Mapped To PORTB
  • 2 Mapped To PORTC
  • 3 Mapped To PORTD
  • 4 Mapped To PORTE
  • 5 Mapped To PORTF
  • 6 Mapped To PORTG
  • 7 Mapped To PORTH
  • 8 Mapped To PORTJ
  • 9 Mapped To PORTK
  • 10 Mapped To PORTL
  • 11 Mapped To PORTM
  • 12 Mapped To PORTN
  • 13 Mapped To PORTP
  • 14 Mapped To PORTQ
  • 15 Mapped To PORTR
VP0MAP3:0Virtual Port 0 Mapping
  • 0 Mapped To PORTA
  • 1 Mapped To PORTB
  • 2 Mapped To PORTC
  • 3 Mapped To PORTD
  • 4 Mapped To PORTE
  • 5 Mapped To PORTF
  • 6 Mapped To PORTG
  • 7 Mapped To PORTH
  • 8 Mapped To PORTJ
  • 9 Mapped To PORTK
  • 10 Mapped To PORTL
  • 11 Mapped To PORTM
  • 12 Mapped To PORTN
  • 13 Mapped To PORTP
  • 14 Mapped To PORTQ
  • 15 Mapped To PORTR

VPCTRLBVirtual Port Control Register B

Address
0xB3
Reset
0x00
Access
read/write
  1. 7VP3MAP3
  2. 6VP3MAP2
  3. 5VP3MAP1
  4. 4VP3MAP0
  5. 3VP2MAP3
  6. 2VP2MAP2
  7. 1VP2MAP1
  8. 0VP2MAP0
2 fields
FieldBitsWhat it does
VP3MAP7:4Virtual Port 3 Mapping
  • 0 Mapped To PORTA
  • 1 Mapped To PORTB
  • 2 Mapped To PORTC
  • 3 Mapped To PORTD
  • 4 Mapped To PORTE
  • 5 Mapped To PORTF
  • 6 Mapped To PORTG
  • 7 Mapped To PORTH
  • 8 Mapped To PORTJ
  • 9 Mapped To PORTK
  • 10 Mapped To PORTL
  • 11 Mapped To PORTM
  • 12 Mapped To PORTN
  • 13 Mapped To PORTP
  • 14 Mapped To PORTQ
  • 15 Mapped To PORTR
VP2MAP3:0Virtual Port 2 Mapping
  • 0 Mapped To PORTA
  • 1 Mapped To PORTB
  • 2 Mapped To PORTC
  • 3 Mapped To PORTD
  • 4 Mapped To PORTE
  • 5 Mapped To PORTF
  • 6 Mapped To PORTG
  • 7 Mapped To PORTH
  • 8 Mapped To PORTJ
  • 9 Mapped To PORTK
  • 10 Mapped To PORTL
  • 11 Mapped To PORTM
  • 12 Mapped To PORTN
  • 13 Mapped To PORTP
  • 14 Mapped To PORTQ
  • 15 Mapped To PORTR

CLKEVOUTClock and Event Out Register

Address
0xB4
Reset
0x00
Access
read/write
  1. 7CLKEVPIN
  2. 6RTCOUT
  3. 5EVOUT1
  4. 4EVOUT0
  5. 3CLKOUTSEL1
  6. 2CLKOUTSEL0
  7. 1CLKOUT1
  8. 0CLKOUT0
5 fields
FieldBitsWhat it does
CLKEVPIN7Peripheral Clock and Event Output pin Select
  • 0 Clock and Event Output on PIN 7
  • 1 Clock and Event Output on PIN 4
RTCOUT6RTC Clock Output
EVOUT5:4Event Output Port
  • 0 Event Output Disabled
  • 1 Event Channel 7 Output on Port C pin 7
  • 2 Event Channel 7 Output on Port D pin 7
  • 3 Event Channel 7 Output on Port E pin 7
CLKOUTSEL3:2Peripheral Clock Output Select
  • 0 1x Peripheral Clock Output to pin
  • 1 2x Peripheral Clock Output to pin
  • 2 4x Peripheral Clock Output to pin
CLKOUT1:0Peripheral Clock Output Port
  • 0 System Clock Output Disabled
  • 1 System Clock Output on Port C pin 7
  • 2 System Clock Output on Port D pin 7
  • 3 System Clock Output on Port E pin 7

EVOUTSELEvent Output Select

Address
0xB6
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2EVOUTSEL2
  7. 1EVOUTSEL1
  8. 0EVOUTSEL0
1 field
FieldBitsWhat it does
EVOUTSEL2:0Event Output Select
  • 0 Event Channel 0 output to pin
  • 1 Event Channel 1 output to pin
  • 2 Event Channel 2 output to pin
  • 3 Event Channel 3 output to pin
  • 4 Event Channel 4 output to pin
  • 5 Event Channel 5 output to pin
  • 6 Event Channel 6 output to pin
  • 7 Event Channel 7 output to pin