ATxmega256D3 TCE2 registers

The 20 registers of TCE2 (16-bit Timer/Counter type 2), from 0xA00, with their reset value and every field. The ATxmega256D3 has 548 registers in 52 peripherals, one page each.

TCE2 16-bit Timer/Counter type 2

CTRLAControl Register A

Address: 0xA00
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CLKSEL3
2CLKSEL2
1CLKSEL1
0CLKSEL0

1 field

Field	Bits	What it does
CLKSEL	3:0	Clock Selection `0` Timer Off `1` System Clock `2` System Clock / 2 `3` System Clock / 4 `4` System Clock / 8 `5` System Clock / 64 `6` System Clock / 256 `7` System Clock / 1024 `8` Event Channel 0 `9` Event Channel 1 `10` Event Channel 2 `11` Event Channel 3

CTRLBControl Register B

Address: 0xA01
Reset: 0x00
Access: read/write

7HCMPDEN
6HCMPCEN
5HCMPBEN
4HCMPAEN
3LCMPDEN
2LCMPCEN
1LCMPBEN
0LCMPAEN

8 fields

Field	Bits	What it does
HCMPDEN	7	High Byte Compare D Enable
HCMPCEN	6	High Byte Compare C Enable
HCMPBEN	5	High Byte Compare B Enable
HCMPAEN	4	High Byte Compare A Enable
LCMPDEN	3	Low Byte Compare D Enable
LCMPCEN	2	Low Byte Compare C Enable
LCMPBEN	1	Low Byte Compare B Enable
LCMPAEN	0	Low Byte Compare A Enable

CTRLCControl register C

Address: 0xA02
Reset: 0x00
Access: read/write

7HCMPD
6HCMPC
5HCMPB
4HCMPA
3LCMPD
2LCMPC
1LCMPB
0LCMPA

8 fields

Field	Bits	What it does
HCMPD	7	High Byte Compare D Output Value
HCMPC	6	High Byte Compare C Output Value
HCMPB	5	High Byte Compare B Output Value
HCMPA	4	High Byte Compare A Output Value
LCMPD	3	Low Byte Compare D Output Value
LCMPC	2	Low Byte Compare C Output Value
LCMPB	1	Low Byte Compare B Output Value
LCMPA	0	Low Byte Compare A Output Value

CTRLEControl Register E

Address: 0xA04
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1BYTEM1
0BYTEM0

1 field

Field	Bits	What it does
BYTEM	1:0	Byte Mode `0` 16-bit mode `1` Timer/Counter operating in byte mode only (TC2) `2` Timer/Counter split into two 8-bit Counters

INTCTRLAInterrupt Control Register A

Address: 0xA06
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3HUNFINTLVL1
2HUNFINTLVL0
1LUNFINTLVL1
0LUNFINTLVL0

2 fields

Field	Bits	What it does
HUNFINTLVL	3:2	High Byte Underflow Interrupt Level `0` Interrupt Disabled `1` Low Level `2` Medium Level `3` High Level
LUNFINTLVL	1:0	Low Byte Underflow interrupt level `0` Interrupt Disabled `1` Low Level `2` Medium Level `3` High Level

INTCTRLBInterrupt Control Register B

Address: 0xA07
Reset: 0x00
Access: read/write

7LCMPDINTLVL1
6LCMPDINTLVL0
5LCMPCINTLVL1
4LCMPCINTLVL0
3LCMPBINTLVL1
2LCMPBINTLVL0
1LCMPAINTLVL1
0LCMPAINTLVL0

4 fields

Field	Bits	What it does
LCMPDINTLVL	7:6	Low Byte Compare D Interrupt Level `0` Interrupt Disabled `1` Low Level `2` Medium Level `3` High Level
LCMPCINTLVL	5:4	Low Byte Compare C Interrupt Level `0` Interrupt Disabled `1` Low Level `2` Medium Level `3` High Level
LCMPBINTLVL	3:2	Low Byte Compare B Interrupt Level `0` Interrupt Disabled `1` Low Level `2` Medium Level `3` High Level
LCMPAINTLVL	1:0	Low Byte Compare A Interrupt Level `0` Interrupt Disabled `1` Low Level `2` Medium Level `3` High Level

CTRLFControl Register F

Address: 0xA09
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CMD1
2CMD0
1CMDEN1
0CMDEN0

2 fields

Field	Bits	What it does
CMD	3:2	Command `0` No Command `2` Force Restart `3` Force Hard Reset
CMDEN	1:0	Command Enable `1` Low Byte Timer/Counter `2` High Byte Timer/Counter `3` Both Low Byte and High Byte Timer/Counters

INTFLAGSInterrupt Flag Register

Address: 0xA0C
Reset: 0x00
Access: read/write

7LCMPDIF
6LCMPCIF
5LCMPBIF
4LCMPAIF
3–
2–
1HUNFIF
0LUNFIF

6 fields

Field	Bits	What it does
LCMPDIF	7	Low Byte Compare D Interrupt Flag
LCMPCIF	6	Low Byte Compare C Interrupt Flag
LCMPBIF	5	Low Byte Compare B Interrupt Flag
LCMPAIF	4	Low Byte Compare A Interrupt Flag
HUNFIF	1	High Byte Underflow Interrupt Flag
LUNFIF	0	Low Byte Underflow Interrupt Flag

LCNTLow Byte Count

Address: 0xA20
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1–
0–

HCNTHigh Byte Count

Address: 0xA21
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1–
0–

LPERLow Byte Period

Address: 0xA26
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1–
0–

HPERHigh Byte Period

Address: 0xA27
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1–
0–

LCMPALow Byte Compare A

Address: 0xA28
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1–
0–

HCMPAHigh Byte Compare A

Address: 0xA29
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1–
0–

LCMPBLow Byte Compare B

Address: 0xA2A
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1–
0–

HCMPBHigh Byte Compare B

Address: 0xA2B
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1–
0–

LCMPCLow Byte Compare C

Address: 0xA2C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1–
0–

HCMPCHigh Byte Compare C

Address: 0xA2D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1–
0–

LCMPDLow Byte Compare D

Address: 0xA2E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1–
0–

HCMPDHigh Byte Compare D

Address: 0xA2F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1–
0–