ATxmega64A1 PORTQ registers

The 21 registers of PORTQ (Port Configuration), from 0x7C0, with their reset value and every field. The ATxmega64A1 has 721 registers in 72 peripherals, one page each.

PORTQ Port Configuration

DIRI/O Port Data Direction

Address
0x7C0
Reset
0x00
Access
read/write
  1. 7DIR7
  2. 6DIR6
  3. 5DIR5
  4. 4DIR4
  5. 3DIR3
  6. 2DIR2
  7. 1DIR1
  8. 0DIR0

DIRSETI/O Port Data Direction Set

Address
0x7C1
Reset
0x00
Access
read/write
  1. 7DIRSET7
  2. 6DIRSET6
  3. 5DIRSET5
  4. 4DIRSET4
  5. 3DIRSET3
  6. 2DIRSET2
  7. 1DIRSET1
  8. 0DIRSET0

DIRCLRI/O Port Data Direction Clear

Address
0x7C2
Reset
0x00
Access
read/write
  1. 7DIRCLR7
  2. 6DIRCLR6
  3. 5DIRCLR5
  4. 4DIRCLR4
  5. 3DIRCLR3
  6. 2DIRCLR2
  7. 1DIRCLR1
  8. 0DIRCLR0

DIRTGLI/O Port Data Direction Toggle

Address
0x7C3
Reset
0x00
Access
read/write
  1. 7DIRTGL7
  2. 6DIRTGL6
  3. 5DIRTGL5
  4. 4DIRTGL4
  5. 3DIRTGL3
  6. 2DIRTGL2
  7. 1DIRTGL1
  8. 0DIRTGL0

OUTI/O Port Output

Address
0x7C4
Reset
0x00
Access
read/write
  1. 7OUT7
  2. 6OUT6
  3. 5OUT5
  4. 4OUT4
  5. 3OUT3
  6. 2OUT2
  7. 1OUT1
  8. 0OUT0

OUTSETI/O Port Output Set

Address
0x7C5
Reset
0x00
Access
read/write
  1. 7OUTSET7
  2. 6OUTSET6
  3. 5OUTSET5
  4. 4OUTSET4
  5. 3OUTSET3
  6. 2OUTSET2
  7. 1OUTSET1
  8. 0OUTSET0

OUTCLRI/O Port Output Clear

Address
0x7C6
Reset
0x00
Access
read/write
  1. 7OUTCLR7
  2. 6OUTCLR6
  3. 5OUTCLR5
  4. 4OUTCLR4
  5. 3OUTCLR3
  6. 2OUTCLR2
  7. 1OUTCLR1
  8. 0OUTCLR0

OUTTGLI/O Port Output Toggle

Address
0x7C7
Reset
0x00
Access
read/write
  1. 7OUTTGL7
  2. 6OUTTGL6
  3. 5OUTTGL5
  4. 4OUTTGL4
  5. 3OUTTGL3
  6. 2OUTTGL2
  7. 1OUTTGL1
  8. 0OUTTGL0

INI/O port Input

Address
0x7C8
Reset
0x00
Access
read/write
  1. 7IN7
  2. 6IN6
  3. 5IN5
  4. 4IN4
  5. 3IN3
  6. 2IN2
  7. 1IN1
  8. 0IN0

INTCTRLInterrupt Control Register

Address
0x7C9
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3INT1LVL1
  6. 2INT1LVL0
  7. 1INT0LVL1
  8. 0INT0LVL0
2 fields
FieldBitsWhat it does
INT1LVL3:2Port Interrupt 1 Level
  • 0 Interrupt Disabled
  • 1 Low Level
  • 2 Medium Level
  • 3 High Level
INT0LVL1:0Port Interrupt 0 Level
  • 0 Interrupt Disabled
  • 1 Low Level
  • 2 Medium Level
  • 3 High Level

INT0MASKPort Interrupt 0 Mask

Address
0x7CA
Reset
0x00
Access
read/write
  1. 7INT0MASK7
  2. 6INT0MASK6
  3. 5INT0MASK5
  4. 4INT0MASK4
  5. 3INT0MASK3
  6. 2INT0MASK2
  7. 1INT0MASK1
  8. 0INT0MASK0

INT1MASKPort Interrupt 1 Mask

Address
0x7CB
Reset
0x00
Access
read/write
  1. 7INT1MASK7
  2. 6INT1MASK6
  3. 5INT1MASK5
  4. 4INT1MASK4
  5. 3INT1MASK3
  6. 2INT1MASK2
  7. 1INT1MASK1
  8. 0INT1MASK0

INTFLAGSInterrupt Flag Register

Address
0x7CC
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1INT1IF
  8. 0INT0IF
2 fields
FieldBitsWhat it does
INT1IF1Port Interrupt 1 Flag
INT0IF0Port Interrupt 0 Flag

PIN0CTRLPin 0 Control Register

Address
0x7D0
Reset
0x00
Access
read/write
  1. 7SRLEN
  2. 6INVEN
  3. 5OPC2
  4. 4OPC1
  5. 3OPC0
  6. 2ISC2
  7. 1ISC1
  8. 0ISC0
4 fields
FieldBitsWhat it does
SRLEN7Slew Rate Enable
INVEN6Inverted I/O Enable
OPC5:3Output/Pull Configuration
  • 0 Totempole
  • 1 Totempole w/ Bus keeper on Input and Output
  • 2 Totempole w/ Pull-down on Input
  • 3 Totempole w/ Pull-up on Input
  • 4 Wired OR
  • 5 Wired AND
  • 6 Wired OR w/ Pull-down
  • 7 Wired AND w/ Pull-up
ISC2:0Input/Sense Configuration
  • 0 Sense Both Edges
  • 1 Sense Rising Edge
  • 2 Sense Falling Edge
  • 3 Sense Level (Transparent For Events)
  • 7 Disable Digital Input Buffer

PIN1CTRLPin 1 Control Register

Address
0x7D1
Reset
0x00
Access
read/write
  1. 7SRLEN
  2. 6INVEN
  3. 5OPC2
  4. 4OPC1
  5. 3OPC0
  6. 2ISC2
  7. 1ISC1
  8. 0ISC0
4 fields
FieldBitsWhat it does
SRLEN7Slew Rate Enable
INVEN6Inverted I/O Enable
OPC5:3Output/Pull Configuration
  • 0 Totempole
  • 1 Totempole w/ Bus keeper on Input and Output
  • 2 Totempole w/ Pull-down on Input
  • 3 Totempole w/ Pull-up on Input
  • 4 Wired OR
  • 5 Wired AND
  • 6 Wired OR w/ Pull-down
  • 7 Wired AND w/ Pull-up
ISC2:0Input/Sense Configuration
  • 0 Sense Both Edges
  • 1 Sense Rising Edge
  • 2 Sense Falling Edge
  • 3 Sense Level (Transparent For Events)
  • 7 Disable Digital Input Buffer

PIN2CTRLPin 2 Control Register

Address
0x7D2
Reset
0x00
Access
read/write
  1. 7SRLEN
  2. 6INVEN
  3. 5OPC2
  4. 4OPC1
  5. 3OPC0
  6. 2ISC2
  7. 1ISC1
  8. 0ISC0
4 fields
FieldBitsWhat it does
SRLEN7Slew Rate Enable
INVEN6Inverted I/O Enable
OPC5:3Output/Pull Configuration
  • 0 Totempole
  • 1 Totempole w/ Bus keeper on Input and Output
  • 2 Totempole w/ Pull-down on Input
  • 3 Totempole w/ Pull-up on Input
  • 4 Wired OR
  • 5 Wired AND
  • 6 Wired OR w/ Pull-down
  • 7 Wired AND w/ Pull-up
ISC2:0Input/Sense Configuration
  • 0 Sense Both Edges
  • 1 Sense Rising Edge
  • 2 Sense Falling Edge
  • 3 Sense Level (Transparent For Events)
  • 7 Disable Digital Input Buffer

PIN3CTRLPin 3 Control Register

Address
0x7D3
Reset
0x00
Access
read/write
  1. 7SRLEN
  2. 6INVEN
  3. 5OPC2
  4. 4OPC1
  5. 3OPC0
  6. 2ISC2
  7. 1ISC1
  8. 0ISC0
4 fields
FieldBitsWhat it does
SRLEN7Slew Rate Enable
INVEN6Inverted I/O Enable
OPC5:3Output/Pull Configuration
  • 0 Totempole
  • 1 Totempole w/ Bus keeper on Input and Output
  • 2 Totempole w/ Pull-down on Input
  • 3 Totempole w/ Pull-up on Input
  • 4 Wired OR
  • 5 Wired AND
  • 6 Wired OR w/ Pull-down
  • 7 Wired AND w/ Pull-up
ISC2:0Input/Sense Configuration
  • 0 Sense Both Edges
  • 1 Sense Rising Edge
  • 2 Sense Falling Edge
  • 3 Sense Level (Transparent For Events)
  • 7 Disable Digital Input Buffer

PIN4CTRLPin 4 Control Register

Address
0x7D4
Reset
0x00
Access
read/write
  1. 7SRLEN
  2. 6INVEN
  3. 5OPC2
  4. 4OPC1
  5. 3OPC0
  6. 2ISC2
  7. 1ISC1
  8. 0ISC0
4 fields
FieldBitsWhat it does
SRLEN7Slew Rate Enable
INVEN6Inverted I/O Enable
OPC5:3Output/Pull Configuration
  • 0 Totempole
  • 1 Totempole w/ Bus keeper on Input and Output
  • 2 Totempole w/ Pull-down on Input
  • 3 Totempole w/ Pull-up on Input
  • 4 Wired OR
  • 5 Wired AND
  • 6 Wired OR w/ Pull-down
  • 7 Wired AND w/ Pull-up
ISC2:0Input/Sense Configuration
  • 0 Sense Both Edges
  • 1 Sense Rising Edge
  • 2 Sense Falling Edge
  • 3 Sense Level (Transparent For Events)
  • 7 Disable Digital Input Buffer

PIN5CTRLPin 5 Control Register

Address
0x7D5
Reset
0x00
Access
read/write
  1. 7SRLEN
  2. 6INVEN
  3. 5OPC2
  4. 4OPC1
  5. 3OPC0
  6. 2ISC2
  7. 1ISC1
  8. 0ISC0
4 fields
FieldBitsWhat it does
SRLEN7Slew Rate Enable
INVEN6Inverted I/O Enable
OPC5:3Output/Pull Configuration
  • 0 Totempole
  • 1 Totempole w/ Bus keeper on Input and Output
  • 2 Totempole w/ Pull-down on Input
  • 3 Totempole w/ Pull-up on Input
  • 4 Wired OR
  • 5 Wired AND
  • 6 Wired OR w/ Pull-down
  • 7 Wired AND w/ Pull-up
ISC2:0Input/Sense Configuration
  • 0 Sense Both Edges
  • 1 Sense Rising Edge
  • 2 Sense Falling Edge
  • 3 Sense Level (Transparent For Events)
  • 7 Disable Digital Input Buffer

PIN6CTRLPin 6 Control Register

Address
0x7D6
Reset
0x00
Access
read/write
  1. 7SRLEN
  2. 6INVEN
  3. 5OPC2
  4. 4OPC1
  5. 3OPC0
  6. 2ISC2
  7. 1ISC1
  8. 0ISC0
4 fields
FieldBitsWhat it does
SRLEN7Slew Rate Enable
INVEN6Inverted I/O Enable
OPC5:3Output/Pull Configuration
  • 0 Totempole
  • 1 Totempole w/ Bus keeper on Input and Output
  • 2 Totempole w/ Pull-down on Input
  • 3 Totempole w/ Pull-up on Input
  • 4 Wired OR
  • 5 Wired AND
  • 6 Wired OR w/ Pull-down
  • 7 Wired AND w/ Pull-up
ISC2:0Input/Sense Configuration
  • 0 Sense Both Edges
  • 1 Sense Rising Edge
  • 2 Sense Falling Edge
  • 3 Sense Level (Transparent For Events)
  • 7 Disable Digital Input Buffer

PIN7CTRLPin 7 Control Register

Address
0x7D7
Reset
0x00
Access
read/write
  1. 7SRLEN
  2. 6INVEN
  3. 5OPC2
  4. 4OPC1
  5. 3OPC0
  6. 2ISC2
  7. 1ISC1
  8. 0ISC0
4 fields
FieldBitsWhat it does
SRLEN7Slew Rate Enable
INVEN6Inverted I/O Enable
OPC5:3Output/Pull Configuration
  • 0 Totempole
  • 1 Totempole w/ Bus keeper on Input and Output
  • 2 Totempole w/ Pull-down on Input
  • 3 Totempole w/ Pull-up on Input
  • 4 Wired OR
  • 5 Wired AND
  • 6 Wired OR w/ Pull-down
  • 7 Wired AND w/ Pull-up
ISC2:0Input/Sense Configuration
  • 0 Sense Both Edges
  • 1 Sense Rising Edge
  • 2 Sense Falling Edge
  • 3 Sense Level (Transparent For Events)
  • 7 Disable Digital Input Buffer