ATxmega64A3 ADCB registers

The 13 registers of ADCB (Analog-to-Digital Converter), from 0x240, with their reset value and every field. The ATxmega64A3 has 599 registers in 63 peripherals, one page each.

ADCB Analog-to-Digital Converter

CTRLAControl Register A

Address
0x240
Reset
0x00
Access
read/write
  1. 7DMASEL1
  2. 6DMASEL0
  3. 5CH3START
  4. 4CH2START
  5. 3CH1START
  6. 2CH0START
  7. 1FLUSH
  8. 0ENABLE
7 fields
FieldBitsWhat it does
DMASEL7:6DMA Selection
  • 0 Combined DMA request OFF
  • 1 ADC Channel 0 or 1
  • 2 ADC Channel 0 or 1 or 2
  • 3 ADC Channel 0 or 1 or 2 or 3
CH3START5Channel 3 Start Conversion
CH2START4Channel 2 Start Conversion
CH1START3Channel 1 Start Conversion
CH0START2Channel 0 Start Conversion
FLUSH1Flush Pipeline
ENABLE0Enable ADC

CTRLBControl Register B

Address
0x241
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4CONMODE
  5. 3FREERUN
  6. 2RESOLUTION1
  7. 1RESOLUTION0
  8. 0–
3 fields
FieldBitsWhat it does
CONMODE4Conversion Mode
FREERUN3Free Running Mode Enable
RESOLUTION2:1Result Resolution
  • 0 12-bit right-adjusted result
  • 2 8-bit right-adjusted result
  • 3 12-bit left-adjusted result

REFCTRLReference Control

Address
0x242
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5REFSEL1
  4. 4REFSEL0
  5. 3–
  6. 2–
  7. 1BANDGAP
  8. 0TEMPREF
3 fields
FieldBitsWhat it does
REFSEL5:4Reference Selection
  • 0 Internal 1V
  • 1 Internal VCC / 1.6V
  • 2 External reference on PORT A
  • 3 External reference on PORT B
BANDGAP1Bandgap enable
TEMPREF0Temperature Reference Enable

EVCTRLEvent Control

Address
0x243
Reset
0x00
Access
read/write
  1. 7SWEEP1
  2. 6SWEEP0
  3. 5EVSEL2
  4. 4EVSEL1
  5. 3EVSEL0
  6. 2EVACT2
  7. 1EVACT1
  8. 0EVACT0
3 fields
FieldBitsWhat it does
SWEEP7:6Channel Sweep Selection
  • 0 ADC Channel 0
  • 1 ADC Channel 0,1
  • 2 ADC Channel 0,1,2
  • 3 ADC Channel 0,1,2,3
EVSEL5:3Event Input Select
  • 0 Event Channel 0,1,2,3
  • 1 Event Channel 1,2,3,4
  • 2 Event Channel 2,3,4,5
  • 3 Event Channel 3,4,5,6
  • 4 Event Channel 4,5,6,7
  • 5 Event Channel 5,6,7
  • 6 Event Channel 6,7
  • 7 Event Channel 7
EVACT2:0Event Action Select
  • 0 No event action
  • 1 First event triggers channel 0
  • 2 First two events trigger channel 0,1
  • 3 First three events trigger channel 0,1,2
  • 4 Events trigger channel 0,1,2,3
  • 5 First event triggers sweep
  • 6 The ADC is flushed and restarted for accurate timing

PRESCALERClock Prescaler

Address
0x244
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2PRESCALER2
  7. 1PRESCALER1
  8. 0PRESCALER0
1 field
FieldBitsWhat it does
PRESCALER2:0Clock Prescaler Selection
  • 0 Divide clock by 4
  • 1 Divide clock by 8
  • 2 Divide clock by 16
  • 3 Divide clock by 32
  • 4 Divide clock by 64
  • 5 Divide clock by 128
  • 6 Divide clock by 256
  • 7 Divide clock by 512

INTFLAGSInterrupt Flags

Address
0x246
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3CH3IF
  6. 2CH2IF
  7. 1CH1IF
  8. 0CH0IF
4 fields
FieldBitsWhat it does
CH3IF3Channel 3 Interrupt Flag
CH2IF2Channel 2 Interrupt Flag
CH1IF1Channel 1 Interrupt Flag
CH0IF0Channel 0 Interrupt Flag

TEMPTemporary register

Address
0x247
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

CALCalibration Value

Address
0x24C
Reset
0x0000
Access
read/write
Size
16-bit

CH0RESChannel 0 Result

Address
0x250
Reset
0x0000
Access
read/write
Size
16-bit

CH1RESChannel 1 Result

Address
0x252
Reset
0x0000
Access
read/write
Size
16-bit

CH2RESChannel 2 Result

Address
0x254
Reset
0x0000
Access
read/write
Size
16-bit

CH3RESChannel 3 Result

Address
0x256
Reset
0x0000
Access
read/write
Size
16-bit

CMPCompare Value

Address
0x258
Reset
0x0000
Access
read/write
Size
16-bit