ATxmega64D4 CLK registers

The 4 registers of CLK (Clock System), from 0x40, with their reset value and every field. The ATxmega64D4 has 441 registers in 45 peripherals, one page each.

CLK Clock System

CTRLControl Register

Address
0x40 I/O 0x20
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2SCLKSEL2
  7. 1SCLKSEL1
  8. 0SCLKSEL0
1 field
FieldBitsWhat it does
SCLKSEL2:0System Clock Selection
  • 0 Internal 2 MHz RC Oscillator
  • 1 Internal 32 MHz RC Oscillator
  • 2 Internal 32.768 kHz RC Oscillator
  • 3 External Crystal Oscillator or Clock
  • 4 Phase Locked Loop

PSCTRLPrescaler Control Register

Address
0x41 I/O 0x21
Reset
0x00
Access
read/write
  1. 7–
  2. 6PSADIV4
  3. 5PSADIV3
  4. 4PSADIV2
  5. 3PSADIV1
  6. 2PSADIV0
  7. 1PSBCDIV1
  8. 0PSBCDIV0
2 fields
FieldBitsWhat it does
PSADIV6:2Prescaler A Division Factor
  • 0 Divide by 1
  • 1 Divide by 2
  • 3 Divide by 4
  • 5 Divide by 8
  • 7 Divide by 16
  • 9 Divide by 32
  • 11 Divide by 64
  • 13 Divide by 128
  • 15 Divide by 256
  • 17 Divide by 512
PSBCDIV1:0Prescaler B and C Division factor
  • 0 Divide B by 1 and C by 1
  • 1 Divide B by 1 and C by 2
  • 2 Divide B by 4 and C by 1
  • 3 Divide B by 2 and C by 2

LOCKLock register

Address
0x42 I/O 0x22
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0LOCK
1 field
FieldBitsWhat it does
LOCK0Clock System Lock

RTCCTRLRTC Control Register

Address
0x43 I/O 0x23
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3RTCSRC2
  6. 2RTCSRC1
  7. 1RTCSRC0
  8. 0RTCEN
2 fields
FieldBitsWhat it does
RTCSRC3:1Clock Source
  • 0 1 kHz from internal 32kHz ULP
  • 1 1.024 kHz from 32.768 kHz crystal oscillator on TOSC
  • 2 1.024 kHz from 32.768 kHz internal oscillator
  • 5 32.768 kHz from 32.768 kHz crystal oscillator on TOSC
  • 6 32.768 kHz from 32.768 kHz internal oscillator
  • 7 External Clock from TOSC1
RTCEN0Clock Source Enable