AVR16DU20 TWI0 registers

The 14 registers of TWI0 (Two-Wire Interface), from 0x900, with their reset value and every field. The AVR16DU20 has 408 registers in 39 peripherals, one page each.

TWI0 Two-Wire Interface

CTRLAControl A

Address
0x900
Reset
0x00
Access
read/write
  1. 7–
  2. 6INPUTLVL
  3. 5–
  4. 4SDASETUP
  5. 3SDAHOLD1
  6. 2SDAHOLD0
  7. 1FMPEN
  8. 0–
4 fields
FieldBitsWhat it does
INPUTLVL6Input voltage transition level
  • 0 I2C input voltage transition level
  • 1 SMBus 3.0 input voltage transition level
SDASETUP4SDA Setup Time
  • 0 SDA setup time is four clock cycles
  • 1 SDA setup time is eight clock cycle
SDAHOLD3:2SDA Hold Time
  • 0 No SDA Hold Delay
  • 1 Short SDA hold time
  • 2 Meets SMBUS 2.0 specification under typical conditions
  • 3 Meets SMBUS 2.0 specificaiton across all corners
FMPEN1Fast-mode Plus Enable
  • 0 Operating in Standard-mode or Fast-mode
  • 1 Operating in Fast-mode Plus

DBGCTRLDebug Control

Address
0x902
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0DBGRUN
1 field
FieldBitsWhat it does
DBGRUN0Debug Run
  • 0 The peripheral is halted in Break Debug mode and ignores events
  • 1 The peripheral will continue to run in Break Debug mode when the CPU is halted

MCTRLAHost Control A

Address
0x903
Reset
0x00
Access
read/write
  1. 7RIEN
  2. 6WIEN
  3. 5–
  4. 4QCEN
  5. 3TIMEOUT1
  6. 2TIMEOUT0
  7. 1SMEN
  8. 0ENABLE
6 fields
FieldBitsWhat it does
RIEN7Read Interrupt Enable
WIEN6Write Interrupt Enable
QCEN4Quick Command Enable
TIMEOUT3:2Inactive Bus Time-Out
  • 0 Bus time-out disabled. I2C.
  • 1 50us - SMBus
  • 2 100us
  • 3 200us
SMEN1Smart Mode Enable
ENABLE0Enable

MCTRLBHost Control B

Address
0x904
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3FLUSH
  6. 2ACKACT
  7. 1MCMD1
  8. 0MCMD0
3 fields
FieldBitsWhat it does
FLUSH3Flush
ACKACT2Acknowledge Action
  • 0 Send ACK
  • 1 Send NACK
MCMD1:0Command
  • 0 No action
  • 1 Execute Acknowledge Action followed by repeated Start.
  • 2 Execute Acknowledge Action followed by a byte read/write operation. Read/write is defined by DIR.
  • 3 Execute Acknowledge Action followed by issuing a Stop condition.

MSTATUSHost STATUS

Address
0x905
Reset
0x00
Access
read/write
  1. 7RIF
  2. 6WIF
  3. 5CLKHOLD
  4. 4RXACK
  5. 3ARBLOST
  6. 2BUSERR
  7. 1BUSSTATE1
  8. 0BUSSTATE0
7 fields
FieldBitsWhat it does
RIF7Read Interrupt Flag
WIF6Write Interrupt Flag
CLKHOLD5Clock Hold
RXACK4Received Acknowledge
ARBLOST3Arbitration Lost
BUSERR2Bus Error
BUSSTATE1:0Bus State
  • 0 Unknown bus state
  • 1 Bus is idle
  • 2 This TWI controls the bus
  • 3 The bus is busy

MBAUDHost Baud Rate

Address
0x906
Reset
0x00
Access
read/write
  1. 7BAUD7
  2. 6BAUD6
  3. 5BAUD5
  4. 4BAUD4
  5. 3BAUD3
  6. 2BAUD2
  7. 1BAUD1
  8. 0BAUD0
1 field
FieldBitsWhat it does
BAUD7:0Baud Rate

MADDRHost Address

Address
0x907
Reset
0x00
Access
read/write
  1. 7ADDR7
  2. 6ADDR6
  3. 5ADDR5
  4. 4ADDR4
  5. 3ADDR3
  6. 2ADDR2
  7. 1ADDR1
  8. 0ADDR0
1 field
FieldBitsWhat it does
ADDR7:0Address

MDATAHost Data

Address
0x908
Reset
0x00
Access
read/write
  1. 7DATA7
  2. 6DATA6
  3. 5DATA5
  4. 4DATA4
  5. 3DATA3
  6. 2DATA2
  7. 1DATA1
  8. 0DATA0
1 field
FieldBitsWhat it does
DATA7:0Data

SCTRLAClient Control A

Address
0x909
Reset
0x00
Access
read/write
  1. 7DIEN
  2. 6APIEN
  3. 5PIEN
  4. 4–
  5. 3–
  6. 2PMEN
  7. 1SMEN
  8. 0ENABLE
6 fields
FieldBitsWhat it does
DIEN7Data Interrupt Enable
APIEN6Address or Stop Interrupt Enable
PIEN5Stop Interrupt Enable
PMEN2Address Recognition Mode
SMEN1Smart Mode Enable
ENABLE0Enable

SCTRLBClient Control B

Address
0x90A
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2ACKACT
  7. 1SCMD1
  8. 0SCMD0
2 fields
FieldBitsWhat it does
ACKACT2Acknowledge Action
  • 0 Send ACK
  • 1 Send NACK
SCMD1:0Command
  • 0 No Action
  • 2 Complete transaction
  • 3 Used in response to an interrupt

SSTATUSClient Status

Address
0x90B
Reset
0x00
Access
read/write
  1. 7DIF
  2. 6APIF
  3. 5CLKHOLD
  4. 4RXACK
  5. 3COLL
  6. 2BUSERR
  7. 1DIR
  8. 0AP
8 fields
FieldBitsWhat it does
DIF7Data Interrupt Flag
APIF6Address or Stop Interrupt Flag
CLKHOLD5Clock Hold
RXACK4Received Acknowledge
COLL3Collision
BUSERR2Bus Error
DIR1Read/Write Direction
AP0Address or Stop
  • 0 A Stop condition generated the interrupt on APIF flag
  • 1 Address detection generated the interrupt on APIF flag

SADDRClient Address

Address
0x90C
Reset
0x00
Access
read/write
  1. 7ADDR7
  2. 6ADDR6
  3. 5ADDR5
  4. 4ADDR4
  5. 3ADDR3
  6. 2ADDR2
  7. 1ADDR1
  8. 0ADDR0
1 field
FieldBitsWhat it does
ADDR7:0Address

SDATAClient Data

Address
0x90D
Reset
0x00
Access
read/write
  1. 7DATA7
  2. 6DATA6
  3. 5DATA5
  4. 4DATA4
  5. 3DATA3
  6. 2DATA2
  7. 1DATA1
  8. 0DATA0
1 field
FieldBitsWhat it does
DATA7:0Data

SADDRMASKClient Address Mask

Address
0x90E
Reset
0x00
Access
read/write
  1. 7ADDRMASK6
  2. 6ADDRMASK5
  3. 5ADDRMASK4
  4. 4ADDRMASK3
  5. 3ADDRMASK2
  6. 2ADDRMASK1
  7. 1ADDRMASK0
  8. 0ADDREN
2 fields
FieldBitsWhat it does
ADDRMASK7:1Address Mask
ADDREN0Address Mask Enable