AVR16EB28 CLKCTRL registers The 10 registers of CLKCTRL (Clock controller), from 0x60, with their reset value and every field. The AVR16EB28 has 423 registers in 40 peripherals, one page each.
CLKCTRL Clock controller MCLKCTRLAMCLK Control A
Address 0x60
Reset 0x00
Access read/write 7 CLKOUT 6 – 5 – 4 – 3 CLKSEL3 2 CLKSEL2 1 CLKSEL1 0 CLKSEL0 2 fields
Field Bits What it does CLKOUT 7 System clock out CLKSEL 3:0 Clock select0 Internal high-frequency oscillator1 Internal 32.768 kHz oscillator2 32.768 kHz crystal oscillator3 External clock4 PLL Oscillator
MCLKCTRLBMCLK Control B
Address 0x61
Reset 0x11
Access read/write 7 – 6 – 5 PBDIV 4 PDIV3 3 PDIV2 2 PDIV1 1 PDIV0 0 PEN 3 fields
Field Bits What it does PBDIV 5 Prescaler B division0 No division1 Divide by 4 PDIV 4:1 Prescaler division0 Divide by 21 Divide by 42 Divide by 83 Divide by 164 Divide by 325 Divide by 648 Divide by 69 Divide by 1010 Divide by 1211 Divide by 2412 Divide by 48 PEN 0 Prescaler enable
MCLKSTATUSMCLK Status
Address 0x65
Reset 0x00
Access read only 7 – 6 – 5 PLLS 4 EXTS 3 XOSC32KS 2 OSC32KS 1 OSCHFS 0 SOSC 6 fields
Field Bits What it does PLLS 5 PLL status EXTS 4 External Clock status XOSC32KS 3 32.768 kHz Crystal Oscillator status OSC32KS 2 32KHz oscillator status OSCHFS 1 High frequency oscillator status SOSC 0 System Oscillator changing
MCLKTIMEBASEMCLK Timebase
Address 0x66
Reset 0x00
Access read/write 7 – 6 – 5 – 4 TIMEBASE4 3 TIMEBASE3 2 TIMEBASE2 1 TIMEBASE1 0 TIMEBASE0 1 field
Field Bits What it does TIMEBASE 4:0 Timebase
OSCHFCTRLAOSCHF Control A
Address 0x68
Reset 0x0C
Access read/write 7 RUNSTDBY 6 – 5 – 4 – 3 – 2 – 1 AUTOTUNE1 0 AUTOTUNE0 2 fields
Field Bits What it does RUNSTDBY 7 Run in standby AUTOTUNE 1:0 Automatic Oscillator Tune0 Disabled1 Tune against 32.768 kHz Crystal Oscillator
OSCHFTUNEOSCHF Tune
Address 0x69
Reset 0x00
Access read/write 7 TUNE7 6 TUNE6 5 TUNE5 4 TUNE4 3 TUNE3 2 TUNE2 1 TUNE1 0 TUNE0 1 field
Field Bits What it does TUNE 7:0 Oscillator Tune
PLLCTRLAPLL Control A
Address 0x70
Reset 0x00
Access read/write 7 RUNSTDBY 6 SOURCE1 5 SOURCE0 4 SOURCEDIV1 3 SOURCEDIV0 2 – 1 MULFAC1 0 MULFAC0 4 fields
Field Bits What it does RUNSTDBY 7 Run in Standby SOURCE 6:5 PLL Source0 Internal High Frequency Oscillator1 External Clock SOURCEDIV 4:3 PLL Source Division0 Source undivided1 Divide source by 22 Divide source by 43 Divide source by 6 MULFAC 1:0 PLL Multiplication Factor0 PLL Disabled2 Multiply by 83 Multiply by 16
PLLCTRLBPLL Control B
Address 0x71
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CLKDIV 1 field
Field Bits What it does CLKDIV 0 PLL Output Clock Division0 PLL output clock undivided1 PLL output clock divided by 2
OSC32KCTRLAOSC32K Control A
Address 0x78
Reset 0x00
Access read/write 7 RUNSTDBY 6 – 5 – 4 – 3 – 2 – 1 – 0 – 1 field
Field Bits What it does RUNSTDBY 7 Run standby
XOSC32KCTRLAXOSC32K Control A
Address 0x7C
Reset 0x00
Access read/write 7 RUNSTDBY 6 – 5 CSUT1 4 CSUT0 3 – 2 SEL 1 LPMODE 0 ENABLE 5 fields
Field Bits What it does RUNSTDBY 7 Run standby CSUT 5:4 Crystal startup time0 1k cycles1 16k cycles2 32k cycles3 64k cycles SEL 2 Select LPMODE 1 Low power mode ENABLE 0 Enable
BETA