The 24 registers of TCD0 (Timer Counter D), from 0xB80, with their reset value and every field. The AVR32DA28 has 471 registers in 45 peripherals, one page each.
TCD0 Timer Counter D
CTRLAControl A
Address
0xB80
Reset
0x00
Access
read/write
7–
6CLKSEL1
5CLKSEL0
4CNTPRES1
3CNTPRES0
2SYNCPRES1
1SYNCPRES0
0ENABLE
4 fields
Field
Bits
What it does
CLKSEL
6:5
Clock select
0 Internal High-Frequency Oscillator
1 PLL
2 External Clock
3 Peripheral Clock
CNTPRES
4:3
Counter prescaler
0 Sync clock divided by 1
1 Sync clock divided by 4
2 Sync clock divided by 32
SYNCPRES
2:1
Synchronization prescaler
0 Selected clock source divided by 1
1 Selected clock source divided by 2
2 Selected clock source divided by 4
3 Selected clock source divided by 8
ENABLE
0
Enable
CTRLBControl B
Address
0xB81
Reset
0x00
Access
read/write
7–
6–
5–
4–
3–
2–
1WGMODE1
0WGMODE0
1 field
Field
Bits
What it does
WGMODE
1:0
Waveform generation mode
0 One ramp mode
1 Two ramp mode
2 Four ramp mode
3 Dual slope mode
CTRLCControl C
Address
0xB82
Reset
0x00
Access
read/write
7CMPDSEL
6CMPCSEL
5–
4–
3FIFTY
2–
1AUPDATE
0CMPOVR
5 fields
Field
Bits
What it does
CMPDSEL
7
Compare D output select
0 PWM A output
1 PWM B output
CMPCSEL
6
Compare C output select
0 PWM A output
1 PWM B output
FIFTY
3
Fifty percent waveform
AUPDATE
1
Auto update
CMPOVR
0
Compare output value override
CTRLDControl D
Address
0xB83
Reset
0x00
Access
read/write
7CMPBVAL3
6CMPBVAL2
5CMPBVAL1
4CMPBVAL0
3CMPAVAL3
2CMPAVAL2
1CMPAVAL1
0CMPAVAL0
2 fields
Field
Bits
What it does
CMPBVAL
7:4
Compare B value
CMPAVAL
3:0
Compare A value
CTRLEControl E
Address
0xB84
Reset
0x00
Access
read/write
7DISEOC
6–
5–
4SCAPTUREB
3SCAPTUREA
2RESTART
1SYNC
0SYNCEOC
6 fields
Field
Bits
What it does
DISEOC
7
Disable at end of cycle
SCAPTUREB
4
Software Capture B Strobe
SCAPTUREA
3
Software Capture A Strobe
RESTART
2
Restart strobe
SYNC
1
synchronize strobe
SYNCEOC
0
Synchronize end of cycle strobe
EVCTRLAEVCTRLA
Address
0xB88
Reset
0x00
Access
read/write
7CFG1
6CFG0
5–
4EDGE
3–
2ACTION
1–
0TRIGEI
4 fields
Field
Bits
What it does
CFG
7:6
Event config
0 Neither Filter nor Asynchronous Event is enabled
1 Input Capture Noise Cancellation Filter enabled
2 Asynchronous Event output qualification enabled
EDGE
4
Edge select
0 The falling edge or low level of event generates retrigger or fault action
1 The rising edge or high level of event generates retrigger or fault action
ACTION
2
Event action
0 Event trigger a fault
1 Event trigger a fault and capture
TRIGEI
0
Trigger event enable
EVCTRLBEVCTRLB
Address
0xB89
Reset
0x00
Access
read/write
7CFG1
6CFG0
5–
4EDGE
3–
2ACTION
1–
0TRIGEI
4 fields
Field
Bits
What it does
CFG
7:6
Event config
0 Neither Filter nor Asynchronous Event is enabled
1 Input Capture Noise Cancellation Filter enabled
2 Asynchronous Event output qualification enabled
EDGE
4
Edge select
0 The falling edge or low level of event generates retrigger or fault action
1 The rising edge or high level of event generates retrigger or fault action
ACTION
2
Event action
0 Event trigger a fault
1 Event trigger a fault and capture
TRIGEI
0
Trigger event enable
INTCTRLInterrupt Control
Address
0xB8C
Reset
0x00
Access
read/write
7–
6–
5–
4–
3TRIGB
2TRIGA
1–
0OVF
3 fields
Field
Bits
What it does
TRIGB
3
Trigger B interrupt enable
TRIGA
2
Trigger A interrupt enable
OVF
0
Overflow interrupt enable
INTFLAGSInterrupt Flags
Address
0xB8D
Reset
0x00
Access
read/write
7–
6–
5–
4–
3TRIGB
2TRIGA
1–
0OVF
3 fields
Field
Bits
What it does
TRIGB
3
Trigger B interrupt enable
TRIGA
2
Trigger A interrupt enable
OVF
0
Overflow interrupt enable
STATUSStatus
Address
0xB8E
Reset
0x00
Access
read/write
7PWMACTB
6PWMACTA
5–
4–
3–
2–
1CMDRDY
0ENRDY
4 fields
Field
Bits
What it does
PWMACTB
7
PWM activity on B
PWMACTA
6
PWM activity on A
CMDRDY
1
Command ready
ENRDY
0
Enable ready
INPUTCTRLAInput Control A
Address
0xB90
Reset
0x00
Access
read/write
7–
6–
5–
4–
3INPUTMODE3
2INPUTMODE2
1INPUTMODE1
0INPUTMODE0
1 field
Field
Bits
What it does
INPUTMODE
3:0
Input mode
0 Input has no actions
1 Stop output, jump to opposite compare cycle and wait
2 Stop output, execute opposite compare cycle and wait
3 stop output, execute opposite compare cycle while fault active
4 Stop all outputs, maintain frequency
5 Stop all outputs, execute dead time while fault active
6 Stop all outputs, jump to next compare cycle and wait
7 Stop all outputs, wait for software action
8 Stop output on edge, jump to next compare cycle
9 Stop output on edge, maintain frequency
10 Stop output at level, maintain frequency
INPUTCTRLBInput Control B
Address
0xB91
Reset
0x00
Access
read/write
7–
6–
5–
4–
3INPUTMODE3
2INPUTMODE2
1INPUTMODE1
0INPUTMODE0
1 field
Field
Bits
What it does
INPUTMODE
3:0
Input mode
0 Input has no actions
1 Stop output, jump to opposite compare cycle and wait
2 Stop output, execute opposite compare cycle and wait
3 stop output, execute opposite compare cycle while fault active
4 Stop all outputs, maintain frequency
5 Stop all outputs, execute dead time while fault active
6 Stop all outputs, jump to next compare cycle and wait