AVR32DB48 OPAMP registers The 22 registers of OPAMP (Operational Amplifier System), from 0x700, with their reset value and every field. The AVR32DB48 has 690 registers in 58 peripherals, one page each.
OPAMP Operational Amplifier System CTRLAControl A
Address 0x700
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 ENABLE 1 field
Field Bits What it does ENABLE 0 Op Amp System Enable
DBGCTRLDebug Control
Address 0x701
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 DBGRUN 1 field
Field Bits What it does DBGRUN 0 Run in Debug Mode
TIMEBASETimebase Value
Address 0x702
Reset 0x01
Access read/write 7 – 6 TIMEBASE6 5 TIMEBASE5 4 TIMEBASE4 3 TIMEBASE3 2 TIMEBASE2 1 TIMEBASE1 0 TIMEBASE0 1 field
Field Bits What it does TIMEBASE 6:0 Timebase Value
PWRCTRLPower Control
Address 0x70F
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 IRSEL 1 field
Field Bits What it does IRSEL 0 Input Range Select0 Full Input Range1 Reduced Input Range
OP0CTRLAOp Amp 0 Control A
Address 0x710
Reset 0x00
Access read/write 7 RUNSTBY 6 – 5 – 4 – 3 OUTMODE1 2 OUTMODE0 1 EVENTEN 0 ALWAYSON 4 fields
Field Bits What it does RUNSTBY 7 Run in Standby Mode OUTMODE 3:2 Output Mode0 Output Driver Off1 Output Driver in Normal Mode EVENTEN 1 Enable Events ALWAYSON 0 Always On
OP0STATUSOp Amp 0 Status
Address 0x711
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SETTLED 1 field
Field Bits What it does SETTLED 0 Settled
OP0RESMUXOp Amp 0 Resistor Ladder Multiplexer
Address 0x712
Reset 0x00
Access read/write 7 MUXWIP2 6 MUXWIP1 5 MUXWIP0 4 MUXBOT2 3 MUXBOT1 2 MUXBOT0 1 MUXTOP1 0 MUXTOP0 3 fields
Field Bits What it does MUXWIP 7:5 Multiplexer Wiper selector0 R1 = 15R, R2 = 1R, R2/R1 = 0.071 R1 = 14R, R2 = 2R, R2/R1 = 0.142 R1 = 12R, R2 = 4R, R2/R1 = 0.333 R1 = 8R, R2 = 8R, R2/R1 = 14 R1 = 6R, R2 = 10R, R2/R1 = 1.675 R1 = 4R, R2 = 12R, R2/R1 = 36 R1 = 2R, R2 = 14R, R2/R1 = 77 R1 = 1R, R2 = 15R, R2/R1 = 15 MUXBOT 4:2 Multiplexer Bottom0 Multiplexer off1 Positive input pin for OPn2 Negative input pin for OPn3 DAC output4 Link OP[n-1] output5 Ground MUXTOP 1:0 Multiplexer Top0 Multiplexer off1 OPn output2 VDD
OP0INMUXOp Amp 0 Input Multiplexer
Address 0x713
Reset 0x00
Access read/write 7 – 6 MUXNEG2 5 MUXNEG1 4 MUXNEG0 3 – 2 MUXPOS2 1 MUXPOS1 0 MUXPOS0 2 fields
Field Bits What it does MUXNEG 6:4 Negative Input Multiplexer0 Negative input pin for OPn1 Wiper from OPn's resistor ladder2 OPn output (unity gain)3 DAC output MUXPOS 2:0 Positive Input Multiplexer0 Positive input pin for OPn1 Wiper from OPn's resistor ladder2 DAC output3 Ground4 VDD/2
OP0SETTLEOp Amp 0 Settle
Address 0x714
Reset 0x00
Access read/write 7 – 6 SETTLE6 5 SETTLE5 4 SETTLE4 3 SETTLE3 2 SETTLE2 1 SETTLE1 0 SETTLE0 1 field
Field Bits What it does SETTLE 6:0 Settle Time
OP0CALOp Amp 0 Calibration
Address 0x715
Reset 0x00
Access read/write 7 CAL7 6 CAL6 5 CAL5 4 CAL4 3 CAL3 2 CAL2 1 CAL1 0 CAL0 1 field
Field Bits What it does CAL 7:0 Calibration (for input offset voltage)
OP1CTRLAOp Amp 1 Control A
Address 0x718
Reset 0x00
Access read/write 7 RUNSTBY 6 – 5 – 4 – 3 OUTMODE1 2 OUTMODE0 1 EVENTEN 0 ALWAYSON 4 fields
Field Bits What it does RUNSTBY 7 Run in Standby Mode OUTMODE 3:2 Output Mode0 Output Driver Off1 Output Driver in Normal Mode EVENTEN 1 Enable Events ALWAYSON 0 Always On
OP1STATUSOp Amp 1 Status
Address 0x719
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SETTLED 1 field
Field Bits What it does SETTLED 0 Settled
OP1RESMUXOp Amp 1 Resistor Ladder Multiplexer
Address 0x71A
Reset 0x00
Access read/write 7 MUXWIP2 6 MUXWIP1 5 MUXWIP0 4 MUXBOT2 3 MUXBOT1 2 MUXBOT0 1 MUXTOP1 0 MUXTOP0 3 fields
Field Bits What it does MUXWIP 7:5 Multiplexer Wiper selector0 R1 = 15R, R2 = 1R, R2/R1 = 0.071 R1 = 14R, R2 = 2R, R2/R1 = 0.142 R1 = 12R, R2 = 4R, R2/R1 = 0.333 R1 = 8R, R2 = 8R, R2/R1 = 14 R1 = 6R, R2 = 10R, R2/R1 = 1.675 R1 = 4R, R2 = 12R, R2/R1 = 36 R1 = 2R, R2 = 14R, R2/R1 = 77 R1 = 1R, R2 = 15R, R2/R1 = 15 MUXBOT 4:2 Multiplexer Bottom0 Multiplexer off1 Positive input pin for OPn2 Negative input pin for OPn3 DAC output4 Link OP[n-1] output5 Ground MUXTOP 1:0 Multiplexer Top0 Multiplexer off1 OPn output2 VDD
OP1INMUXOp Amp 1 Input Multiplexer
Address 0x71B
Reset 0x00
Access read/write 7 – 6 MUXNEG2 5 MUXNEG1 4 MUXNEG0 3 – 2 MUXPOS2 1 MUXPOS1 0 MUXPOS0 2 fields
Field Bits What it does MUXNEG 6:4 Negative Input Multiplexer0 Negative input pin for OPn1 Wiper from OPn's resistor ladder2 OPn output (unity gain)3 DAC output MUXPOS 2:0 Positive Input Multiplexer0 Positive input pin for OPn1 Wiper from OPn's resistor ladder2 DAC output3 Ground4 VDD/25 Output from OP0
OP1SETTLEOp Amp 1 Settle
Address 0x71C
Reset 0x00
Access read/write 7 – 6 SETTLE6 5 SETTLE5 4 SETTLE4 3 SETTLE3 2 SETTLE2 1 SETTLE1 0 SETTLE0 1 field
Field Bits What it does SETTLE 6:0 Settle Time
OP1CALOp Amp 1 Calibration
Address 0x71D
Reset 0x00
Access read/write 7 CAL7 6 CAL6 5 CAL5 4 CAL4 3 CAL3 2 CAL2 1 CAL1 0 CAL0 1 field
Field Bits What it does CAL 7:0 Calibration (for input offset voltage)
OP2CTRLAOp Amp 2 Control A
Address 0x720
Reset 0x00
Access read/write 7 RUNSTBY 6 – 5 – 4 – 3 OUTMODE1 2 OUTMODE0 1 EVENTEN 0 ALWAYSON 4 fields
Field Bits What it does RUNSTBY 7 Run in Standby Mode OUTMODE 3:2 Output Mode0 Output Driver Off1 Output Driver in Normal Mode EVENTEN 1 Enable Events ALWAYSON 0 Always On
OP2STATUSOp Amp 2 Status
Address 0x721
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SETTLED 1 field
Field Bits What it does SETTLED 0 Settled
OP2RESMUXOp Amp 2 Resistor Ladder Multiplexer
Address 0x722
Reset 0x00
Access read/write 7 MUXWIP2 6 MUXWIP1 5 MUXWIP0 4 MUXBOT2 3 MUXBOT1 2 MUXBOT0 1 MUXTOP1 0 MUXTOP0 3 fields
Field Bits What it does MUXWIP 7:5 Multiplexer Wiper selector0 R1 = 15R, R2 = 1R, R2/R1 = 0.071 R1 = 14R, R2 = 2R, R2/R1 = 0.142 R1 = 12R, R2 = 4R, R2/R1 = 0.333 R1 = 8R, R2 = 8R, R2/R1 = 14 R1 = 6R, R2 = 10R, R2/R1 = 1.675 R1 = 4R, R2 = 12R, R2/R1 = 36 R1 = 2R, R2 = 14R, R2/R1 = 77 R1 = 1R, R2 = 15R, R2/R1 = 15 MUXBOT 4:2 Multiplexer Bottom0 Multiplexer off1 Positive input pin for OPn2 Negative input pin for OPn3 DAC output4 Link OP[n-1] output5 Ground MUXTOP 1:0 Multiplexer Top0 Multiplexer off1 OPn output2 VDD
OP2INMUXOp Amp 2 Input Multiplexer
Address 0x723
Reset 0x00
Access read/write 7 – 6 MUXNEG2 5 MUXNEG1 4 MUXNEG0 3 – 2 MUXPOS2 1 MUXPOS1 0 MUXPOS0 2 fields
Field Bits What it does MUXNEG 6:4 Negative Input Multiplexer0 Negative input pin for OPn1 Wiper from OPn's resistor ladder2 OPn output (unity gain)3 DAC output MUXPOS 2:0 Positive Input Multiplexer0 Positive input pin for OPn1 Wiper from OPn's resistor ladder2 DAC output3 Ground4 VDD/25 Output from OP16 Wiper from OP0's resistor ladder
OP2SETTLEOp Amp 2 Settle
Address 0x724
Reset 0x00
Access read/write 7 – 6 SETTLE6 5 SETTLE5 4 SETTLE4 3 SETTLE3 2 SETTLE2 1 SETTLE1 0 SETTLE0 1 field
Field Bits What it does SETTLE 6:0 Settle Time
OP2CALOp Amp 2 Calibration
Address 0x725
Reset 0x00
Access read/write 7 CAL7 6 CAL6 5 CAL5 4 CAL4 3 CAL3 2 CAL2 1 CAL1 0 CAL0 1 field
Field Bits What it does CAL 7:0 Calibration (for input offset voltage)