AVR32EA28 CCL registers

The 21 registers of CCL (Configurable Custom Logic), from 0x1C0, with their reset value and every field. The AVR32EA28 has 492 registers in 43 peripherals, one page each.

CCL Configurable Custom Logic

CTRLAControl Register A

Address
0x1C0
Reset
0x00
Access
read/write
  1. 7–
  2. 6RUNSTDBY
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0ENABLE
2 fields
FieldBitsWhat it does
RUNSTDBY6Run in Standby
ENABLE0Enable

SEQCTRL0Sequential Control 0

Address
0x1C1
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3SEQSEL3
  6. 2SEQSEL2
  7. 1SEQSEL1
  8. 0SEQSEL0
1 field
FieldBitsWhat it does
SEQSEL3:0Sequential Selection
  • 0 Sequential logic disabled
  • 1 D FlipFlop
  • 2 JK FlipFlop
  • 3 D Latch
  • 4 RS Latch

SEQCTRL1Sequential Control 1

Address
0x1C2
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3SEQSEL3
  6. 2SEQSEL2
  7. 1SEQSEL1
  8. 0SEQSEL0
1 field
FieldBitsWhat it does
SEQSEL3:0Sequential Selection
  • 0 Sequential logic disabled
  • 1 D FlipFlop
  • 2 JK FlipFlop
  • 3 D Latch
  • 4 RS Latch

INTCTRL0Interrupt Control 0

Address
0x1C5
Reset
0x00
Access
read/write
  1. 7INTMODE31
  2. 6INTMODE30
  3. 5INTMODE21
  4. 4INTMODE20
  5. 3INTMODE11
  6. 2INTMODE10
  7. 1INTMODE01
  8. 0INTMODE00
4 fields
FieldBitsWhat it does
INTMODE37:6Interrupt Mode for LUT3
  • 0 Interrupt disabled
  • 1 Sense rising edge
  • 2 Sense falling edge
  • 3 Sense both edges
INTMODE25:4Interrupt Mode for LUT2
  • 0 Interrupt disabled
  • 1 Sense rising edge
  • 2 Sense falling edge
  • 3 Sense both edges
INTMODE13:2Interrupt Mode for LUT1
  • 0 Interrupt disabled
  • 1 Sense rising edge
  • 2 Sense falling edge
  • 3 Sense both edges
INTMODE01:0Interrupt Mode for LUT0
  • 0 Interrupt disabled
  • 1 Sense rising edge
  • 2 Sense falling edge
  • 3 Sense both edges

INTFLAGSInterrupt Flags

Address
0x1C7
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3INT3
  6. 2INT2
  7. 1INT1
  8. 0INT0
1 field
FieldBitsWhat it does
INT3:0Interrupt Flag

LUT0CTRLALUT 0 Control A

Address
0x1C8
Reset
0x00
Access
read/write
  1. 7EDGEDET
  2. 6OUTEN
  3. 5FILTSEL1
  4. 4FILTSEL0
  5. 3CLKSRC2
  6. 2CLKSRC1
  7. 1CLKSRC0
  8. 0ENABLE
5 fields
FieldBitsWhat it does
EDGEDET7Edge Detection Enable
  • 0 Edge detector is disabled
  • 1 Edge detector is enabled
OUTEN6Output Enable
FILTSEL5:4Filter Selection
  • 0 Filter disabled
  • 1 Synchronizer enabled
  • 2 Filter enabled
CLKSRC3:1Clock Source Selection
  • 0 Peripheral Clock
  • 1 INSEL2 selection
  • 4 Internal High Frequency oscillator
  • 5 Internal 32.768 kHz oscillator
  • 6 Internal 32.768 kHz oscillator divided by 32
ENABLE0LUT Enable

LUT0CTRLBLUT 0 Control B

Address
0x1C9
Reset
0x00
Access
read/write
  1. 7INSEL13
  2. 6INSEL12
  3. 5INSEL11
  4. 4INSEL10
  5. 3INSEL03
  6. 2INSEL02
  7. 1INSEL01
  8. 0INSEL00
2 fields
FieldBitsWhat it does
INSEL17:4LUT Input 1 Source Selection
  • 0 Masked input
  • 1 Feedback input
  • 2 Output from LUT[n+1] as input source
  • 3 Event A as input source
  • 4 Event B as input source
  • 5 IN1 input source
  • 6 AC1 output input source
  • 7 USART1 TxD input source
  • 8 SPI0 MISO input source
  • 9 TCA0 WO1 input source
  • 10 TCA1 WO1 input source
  • 11 TCB1 WO input source
INSEL03:0LUT Input 0 Source Selection
  • 0 Masked input
  • 1 Feedback input
  • 2 Output from LUT[n+1] as input source
  • 3 Event A as input source
  • 4 Event B as input source
  • 5 IN0 input source
  • 6 AC0 output input source
  • 7 USART0 TxD input source
  • 8 SPI0 MISO input source
  • 9 TCA0 WO0 input source
  • 10 TCA1 WO0 input source
  • 11 TCB0 WO input source

LUT0CTRLCLUT 0 Control C

Address
0x1CA
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3INSEL23
  6. 2INSEL22
  7. 1INSEL21
  8. 0INSEL20
1 field
FieldBitsWhat it does
INSEL23:0LUT Input 2 Source Selection
  • 0 Masked input
  • 1 Feedback input
  • 2 Output from LUT[n+1] as input source
  • 3 Event A as input source
  • 4 Event B as input source
  • 5 IN2 input source
  • 6 AC1 output input source
  • 7 USART2 TxD input source
  • 8 SPI0 MISO input source
  • 9 TCA0 WO2 input source
  • 10 TCA1 WO2 input source
  • 11 TCB2 WO input source

TRUTH0Truth 0

Address
0x1CB
Reset
0x00
Access
read/write
  1. 7TRUTH7
  2. 6TRUTH6
  3. 5TRUTH5
  4. 4TRUTH4
  5. 3TRUTH3
  6. 2TRUTH2
  7. 1TRUTH1
  8. 0TRUTH0
1 field
FieldBitsWhat it does
TRUTH7:0Truth Table

LUT1CTRLALUT 1 Control A

Address
0x1CC
Reset
0x00
Access
read/write
  1. 7EDGEDET
  2. 6OUTEN
  3. 5FILTSEL1
  4. 4FILTSEL0
  5. 3CLKSRC2
  6. 2CLKSRC1
  7. 1CLKSRC0
  8. 0ENABLE
5 fields
FieldBitsWhat it does
EDGEDET7Edge Detection Enable
  • 0 Edge detector is disabled
  • 1 Edge detector is enabled
OUTEN6Output Enable
FILTSEL5:4Filter Selection
  • 0 Filter disabled
  • 1 Synchronizer enabled
  • 2 Filter enabled
CLKSRC3:1Clock Source Selection
  • 0 Peripheral Clock
  • 1 INSEL2 selection
  • 4 Internal High Frequency oscillator
  • 5 Internal 32.768 kHz oscillator
  • 6 Internal 32.768 kHz oscillator divided by 32
ENABLE0LUT Enable

LUT1CTRLBLUT 1 Control B

Address
0x1CD
Reset
0x00
Access
read/write
  1. 7INSEL13
  2. 6INSEL12
  3. 5INSEL11
  4. 4INSEL10
  5. 3INSEL03
  6. 2INSEL02
  7. 1INSEL01
  8. 0INSEL00
2 fields
FieldBitsWhat it does
INSEL17:4LUT Input 1 Source Selection
  • 0 Masked input
  • 1 Feedback input
  • 2 Output from LUT[n+1] as input source
  • 3 Event A as input source
  • 4 Event B as input source
  • 5 IN1 input source
  • 6 AC1 output input source
  • 7 USART1 TxD input source
  • 8 SPI0 MISO input source
  • 9 TCA0 WO1 input source
  • 10 TCA1 WO1 input source
  • 11 TCB1 WO input source
INSEL03:0LUT Input 0 Source Selection
  • 0 Masked input
  • 1 Feedback input
  • 2 Output from LUT[n+1] as input source
  • 3 Event A as input source
  • 4 Event B as input source
  • 5 IN0 input source
  • 6 AC0 output input source
  • 7 USART0 TxD input source
  • 8 SPI0 MISO input source
  • 9 TCA0 WO0 input source
  • 10 TCA1 WO0 input source
  • 11 TCB0 WO input source

LUT1CTRLCLUT 1 Control C

Address
0x1CE
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3INSEL23
  6. 2INSEL22
  7. 1INSEL21
  8. 0INSEL20
1 field
FieldBitsWhat it does
INSEL23:0LUT Input 2 Source Selection
  • 0 Masked input
  • 1 Feedback input
  • 2 Output from LUT[n+1] as input source
  • 3 Event A as input source
  • 4 Event B as input source
  • 5 IN2 input source
  • 6 AC1 output input source
  • 7 USART2 TxD input source
  • 8 SPI0 MISO input source
  • 9 TCA0 WO2 input source
  • 10 TCA1 WO2 input source
  • 11 TCB2 WO input source

TRUTH1Truth 1

Address
0x1CF
Reset
0x00
Access
read/write
  1. 7TRUTH7
  2. 6TRUTH6
  3. 5TRUTH5
  4. 4TRUTH4
  5. 3TRUTH3
  6. 2TRUTH2
  7. 1TRUTH1
  8. 0TRUTH0
1 field
FieldBitsWhat it does
TRUTH7:0Truth Table

LUT2CTRLALUT 2 Control A

Address
0x1D0
Reset
0x00
Access
read/write
  1. 7EDGEDET
  2. 6OUTEN
  3. 5FILTSEL1
  4. 4FILTSEL0
  5. 3CLKSRC2
  6. 2CLKSRC1
  7. 1CLKSRC0
  8. 0ENABLE
5 fields
FieldBitsWhat it does
EDGEDET7Edge Detection Enable
  • 0 Edge detector is disabled
  • 1 Edge detector is enabled
OUTEN6Output Enable
FILTSEL5:4Filter Selection
  • 0 Filter disabled
  • 1 Synchronizer enabled
  • 2 Filter enabled
CLKSRC3:1Clock Source Selection
  • 0 Peripheral Clock
  • 1 INSEL2 selection
  • 4 Internal High Frequency oscillator
  • 5 Internal 32.768 kHz oscillator
  • 6 Internal 32.768 kHz oscillator divided by 32
ENABLE0LUT Enable

LUT2CTRLBLUT 2 Control B

Address
0x1D1
Reset
0x00
Access
read/write
  1. 7INSEL13
  2. 6INSEL12
  3. 5INSEL11
  4. 4INSEL10
  5. 3INSEL03
  6. 2INSEL02
  7. 1INSEL01
  8. 0INSEL00
2 fields
FieldBitsWhat it does
INSEL17:4LUT Input 1 Source Selection
  • 0 Masked input
  • 1 Feedback input
  • 2 Output from LUT[n+1] as input source
  • 3 Event A as input source
  • 4 Event B as input source
  • 5 IN1 input source
  • 6 AC1 output input source
  • 7 USART1 TxD input source
  • 8 SPI0 MISO input source
  • 9 TCA0 WO1 input source
  • 10 TCA1 WO1 input source
  • 11 TCB1 WO input source
INSEL03:0LUT Input 0 Source Selection
  • 0 Masked input
  • 1 Feedback input
  • 2 Output from LUT[n+1] as input source
  • 3 Event A as input source
  • 4 Event B as input source
  • 5 IN0 input source
  • 6 AC0 output input source
  • 7 USART0 TxD input source
  • 8 SPI0 MISO input source
  • 9 TCA0 WO0 input source
  • 10 TCA1 WO0 input source
  • 11 TCB0 WO input source

LUT2CTRLCLUT 2 Control C

Address
0x1D2
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3INSEL23
  6. 2INSEL22
  7. 1INSEL21
  8. 0INSEL20
1 field
FieldBitsWhat it does
INSEL23:0LUT Input 2 Source Selection
  • 0 Masked input
  • 1 Feedback input
  • 2 Output from LUT[n+1] as input source
  • 3 Event A as input source
  • 4 Event B as input source
  • 5 IN2 input source
  • 6 AC1 output input source
  • 7 USART2 TxD input source
  • 8 SPI0 MISO input source
  • 9 TCA0 WO2 input source
  • 10 TCA1 WO2 input source
  • 11 TCB2 WO input source

TRUTH2Truth 2

Address
0x1D3
Reset
0x00
Access
read/write
  1. 7TRUTH7
  2. 6TRUTH6
  3. 5TRUTH5
  4. 4TRUTH4
  5. 3TRUTH3
  6. 2TRUTH2
  7. 1TRUTH1
  8. 0TRUTH0
1 field
FieldBitsWhat it does
TRUTH7:0Truth Table

LUT3CTRLALUT 3 Control A

Address
0x1D4
Reset
0x00
Access
read/write
  1. 7EDGEDET
  2. 6OUTEN
  3. 5FILTSEL1
  4. 4FILTSEL0
  5. 3CLKSRC2
  6. 2CLKSRC1
  7. 1CLKSRC0
  8. 0ENABLE
5 fields
FieldBitsWhat it does
EDGEDET7Edge Detection Enable
  • 0 Edge detector is disabled
  • 1 Edge detector is enabled
OUTEN6Output Enable
FILTSEL5:4Filter Selection
  • 0 Filter disabled
  • 1 Synchronizer enabled
  • 2 Filter enabled
CLKSRC3:1Clock Source Selection
  • 0 Peripheral Clock
  • 1 INSEL2 selection
  • 4 Internal High Frequency oscillator
  • 5 Internal 32.768 kHz oscillator
  • 6 Internal 32.768 kHz oscillator divided by 32
ENABLE0LUT Enable

LUT3CTRLBLUT 3 Control B

Address
0x1D5
Reset
0x00
Access
read/write
  1. 7INSEL13
  2. 6INSEL12
  3. 5INSEL11
  4. 4INSEL10
  5. 3INSEL03
  6. 2INSEL02
  7. 1INSEL01
  8. 0INSEL00
2 fields
FieldBitsWhat it does
INSEL17:4LUT Input 1 Source Selection
  • 0 Masked input
  • 1 Feedback input
  • 2 Output from LUT[n+1] as input source
  • 3 Event A as input source
  • 4 Event B as input source
  • 5 IN1 input source
  • 6 AC1 output input source
  • 7 USART1 TxD input source
  • 8 SPI0 MISO input source
  • 9 TCA0 WO1 input source
  • 10 TCA1 WO1 input source
  • 11 TCB1 WO input source
INSEL03:0LUT Input 0 Source Selection
  • 0 Masked input
  • 1 Feedback input
  • 2 Output from LUT[n+1] as input source
  • 3 Event A as input source
  • 4 Event B as input source
  • 5 IN0 input source
  • 6 AC0 output input source
  • 7 USART0 TxD input source
  • 8 SPI0 MISO input source
  • 9 TCA0 WO0 input source
  • 10 TCA1 WO0 input source
  • 11 TCB0 WO input source

LUT3CTRLCLUT 3 Control C

Address
0x1D6
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3INSEL23
  6. 2INSEL22
  7. 1INSEL21
  8. 0INSEL20
1 field
FieldBitsWhat it does
INSEL23:0LUT Input 2 Source Selection
  • 0 Masked input
  • 1 Feedback input
  • 2 Output from LUT[n+1] as input source
  • 3 Event A as input source
  • 4 Event B as input source
  • 5 IN2 input source
  • 6 AC1 output input source
  • 7 USART2 TxD input source
  • 8 SPI0 MISO input source
  • 9 TCA0 WO2 input source
  • 10 TCA1 WO2 input source
  • 11 TCB2 WO input source

TRUTH3Truth 3

Address
0x1D7
Reset
0x00
Access
read/write
  1. 7TRUTH7
  2. 6TRUTH6
  3. 5TRUTH5
  4. 4TRUTH4
  5. 3TRUTH3
  6. 2TRUTH2
  7. 1TRUTH1
  8. 0TRUTH0
1 field
FieldBitsWhat it does
TRUTH7:0Truth Table