AVR32EA28 FUSE registers

The 7 registers of FUSE (Fuses), from 0x1050, with their reset value and every field. The AVR32EA28 has 492 registers in 43 peripherals, one page each.

FUSE Fuses

WDTCFGWatchdog Configuration

Address
0x1050
Reset
0x00
Access
read/write
  1. 7WINDOW3
  2. 6WINDOW2
  3. 5WINDOW1
  4. 4WINDOW0
  5. 3PERIOD3
  6. 2PERIOD2
  7. 1PERIOD1
  8. 0PERIOD0
2 fields
FieldBitsWhat it does
WINDOW7:4Watchdog Window Timeout Period
  • 0 Window mode off
  • 1 8 cycles (8ms)
  • 2 16 cycles (16ms)
  • 3 32 cycles (32ms)
  • 4 64 cycles (64ms)
  • 5 128 cycles (0.128s)
  • 6 256 cycles (0.256s)
  • 7 512 cycles (0.512s)
  • 8 1K cycles (1.0s)
  • 9 2K cycles (2.0s)
  • 10 4K cycles (4.0s)
  • 11 8K cycles (8.0s)
PERIOD3:0Watchdog Timeout Period
  • 0 Watch-Dog timer Off
  • 1 8 cycles (8ms)
  • 2 16 cycles (16ms)
  • 3 32 cycles (32ms)
  • 4 64 cycles (64ms)
  • 5 128 cycles (0.128s)
  • 6 256 cycles (0.256s)
  • 7 512 cycles (0.512s)
  • 8 1K cycles (1.0s)
  • 9 2K cycles (2.0s)
  • 10 4K cycles (4.0s)
  • 11 8K cycles (8.0s)

BODCFGBOD Configuration

Address
0x1051
Reset
0x00
Access
read/write
  1. 7LVL2
  2. 6LVL1
  3. 5LVL0
  4. 4SAMPFREQ
  5. 3ACTIVE1
  6. 2ACTIVE0
  7. 1SLEEP1
  8. 0SLEEP0
4 fields
FieldBitsWhat it does
LVL7:5BOD Level
  • 0 BOD Disabled during normal operation
  • 1 1.9 V
  • 2 2.7 V
  • 3 4.5 V
SAMPFREQ4BOD Sample Frequency
  • 0 Sampling frequency is 128 Hz
  • 1 Sample frequency is 32 Hz
ACTIVE3:2BOD Operation in Active Mode
  • 0 Disabled
  • 1 Enabled in continuous mode
  • 2 Enabled in sampled mode
  • 3 Enabled in continuous mode. Execution halted at wake-up until BOD is running
SLEEP1:0BOD Operation in Sleep Mode
  • 0 Disabled
  • 1 Enabled in continuous mode
  • 2 Enabled in sampled mode

OSCCFGOscillator Configuration

Address
0x1052
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3OSCHFFRQ
  6. 2–
  7. 1–
  8. 0–
1 field
FieldBitsWhat it does
OSCHFFRQ3High-frequency Oscillator Frequency
  • 0 OSCHF running at 20 MHz
  • 1 OSCHF running at 16 MHz

SYSCFG0System Configuration 0

Address
0x1055
Reset
0xD0
Access
read/write
  1. 7CRCSRC1
  2. 6CRCSRC0
  3. 5CRCSEL
  4. 4UPDIPINCFG
  5. 3RSTPINCFG
  6. 2–
  7. 1–
  8. 0EESAVE
5 fields
FieldBitsWhat it does
CRCSRC7:6CRC Source
  • 0 CRC of full Flash (boot, application code and application data)
  • 1 CRC of boot section
  • 2 CRC of application code and boot sections
  • 3 No CRC
CRCSEL5CRC Select
  • 0 Enable CRC16
  • 1 Enable CRC32
UPDIPINCFG4UPDI Pin Configuration
  • 0 PF7 Configured as GPIO pin
  • 1 PF7 Configured as UPDI pin
RSTPINCFG3Reset Pin Configuration
  • 0 No External Reset
  • 1 PF6 configured as RESET pin
EESAVE0EEPROM Save
  • 0 EEPROM content is erased during chip erase
  • 1 EEPROM content is preserved during chip erase

SYSCFG1System Configuration 1

Address
0x1056
Reset
0x07
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2SUT2
  7. 1SUT1
  8. 0SUT0
1 field
FieldBitsWhat it does
SUT2:0Startup Time
  • 0 0 ms
  • 1 1 ms
  • 2 2 ms
  • 3 4 ms
  • 4 8 ms
  • 5 16 ms
  • 6 32 ms
  • 7 64 ms

CODESIZECode Section Size

Address
0x1057
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

BOOTSIZEBoot Section Size

Address
0x1058
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–