AVR32EA48 USART0 registers The 14 registers of USART0 (Universal Synchronous and Asynchronous Receiver and Transmitter), from 0x800, with their reset value and every field. The AVR32EA48 has 550 registers in 47 peripherals, one page each.
USART0 Universal Synchronous and Asynchronous Receiver and Transmitter RXDATALReceive Data Low Byte
Address 0x800
Reset 0x00
Access read only 7 DATA7 6 DATA6 5 DATA5 4 DATA4 3 DATA3 2 DATA2 1 DATA1 0 DATA0 1 field
Field Bits What it does DATA 7:0 RX Data
RXDATAHReceive Data High Byte
Address 0x801
Reset 0x00
Access read only 7 RXCIF 6 BUFOVF 5 – 4 – 3 – 2 FERR 1 PERR 0 DATA8 5 fields
Field Bits What it does RXCIF 7 Receive Complete Interrupt Flag BUFOVF 6 Buffer Overflow FERR 2 Frame Error PERR 1 Parity Error DATA8 0 Receiver Data Register
TXDATALTransmit Data Low Byte
Address 0x802
Reset 0x00
Access read/write 7 DATA7 6 DATA6 5 DATA5 4 DATA4 3 DATA3 2 DATA2 1 DATA1 0 DATA0 1 field
Field Bits What it does DATA 7:0 Transmit Data Register
TXDATAHTransmit Data High Byte
Address 0x803
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 DATA8 1 field
Field Bits What it does DATA8 0 Transmit Data Register (CHSIZE=9bit)
STATUSStatus
Address 0x804
Reset 0x20
Access read/write 7 RXCIF 6 TXCIF 5 DREIF 4 RXSIF 3 ISFIF 2 – 1 BDF 0 WFB 7 fields
Field Bits What it does RXCIF 7 Receive Complete Interrupt Flag TXCIF 6 Transmit Interrupt Flag DREIF 5 Data Register Empty Flag RXSIF 4 Receive Start Interrupt ISFIF 3 Inconsistent Sync Field Interrupt Flag BDF 1 Break Detected Flag WFB 0 Wait For Break
CTRLAControl A
Address 0x805
Reset 0x00
Access read/write 7 RXCIE 6 TXCIE 5 DREIE 4 RXSIE 3 LBME 2 ABEIE 1 – 0 RS485 7 fields
Field Bits What it does RXCIE 7 Receive Complete Interrupt Enable TXCIE 6 Transmit Complete Interrupt Enable DREIE 5 Data Register Empty Interrupt Enable RXSIE 4 Receiver Start Frame Interrupt Enable LBME 3 Loop-back Mode Enable ABEIE 2 Auto-baud Error Interrupt Enable RS485 0 RS485 Mode internal transmitter0 RS485 Mode disabled1 RS485 Mode enabled
CTRLBControl B
Address 0x806
Reset 0x00
Access read/write 7 RXEN 6 TXEN 5 – 4 SFDEN 3 ODME 2 RXMODE1 1 RXMODE0 0 MPCM 6 fields
Field Bits What it does RXEN 7 Reciever enable TXEN 6 Transmitter Enable SFDEN 4 Start Frame Detection Enable ODME 3 Open Drain Mode Enable RXMODE 2:1 Receiver Mode0 Normal mode1 CLK2x mode2 Generic autobaud mode3 LIN constrained autobaud mode MPCM 0 Multi-processor Communication Mode
CTRLCControl C
Address 0x807
Reset 0x03
Access read/write 7 CMODE1 6 CMODE0 5 PMODE1 4 PMODE0 3 SBMODE 2 CHSIZE2 1 CHSIZE1 0 CHSIZE0 6 fields
Field Bits What it does CMODE 7:6 Communication Mode0 Asynchronous Mode1 Synchronous Mode2 Infrared Communication3 SPI Host Mode PMODE 5:4 Parity Mode0 No Parity2 Even Parity3 Odd Parity SBMODE 3 Stop Bit Mode0 1 stop bit1 2 stop bits CHSIZE 2:0 Character Size0 Character size: 5 bit1 Character size: 6 bit2 Character size: 7 bit3 Character size: 8 bit6 Character size: 9 bit read low byte first7 Character size: 9 bit read high byte first UDORD 2 SPI Host Mode, Data Order UCPHA 1 SPI Host Mode, Clock Phase
BAUDBaud Rate
Address 0x808
Reset 0x0000
Access read/write
Size 16-bit CTRLDControl D
Address 0x80A
Reset 0x00
Access read/write 7 ABW1 6 ABW0 5 – 4 – 3 – 2 – 1 – 0 – 1 field
Field Bits What it does ABW 7:6 Auto Baud Window0 18% tolerance1 15% tolerance2 21% tolerance3 25% tolerance
DBGCTRLDebug Control
Address 0x80B
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 DBGRUN 1 field
Field Bits What it does DBGRUN 0 Debug Run
EVCTRLEvent Control
Address 0x80C
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 IREI 1 field
Field Bits What it does IREI 0 IrDA Event Input Enable
TXPLCTRLIRCOM Transmitter Pulse Length Control
Address 0x80D
Reset 0x00
Access read/write 7 TXPL7 6 TXPL6 5 TXPL5 4 TXPL4 3 TXPL3 2 TXPL2 1 TXPL1 0 TXPL0 1 field
Field Bits What it does TXPL 7:0 Transmit pulse length
RXPLCTRLIRCOM Receiver Pulse Length Control
Address 0x80E
Reset 0x00
Access read/write 7 – 6 RXPL6 5 RXPL5 4 RXPL4 3 RXPL3 2 RXPL2 1 RXPL1 0 RXPL0 1 field
Field Bits What it does RXPL 6:0 Receiver Pulse Lenght
BETA