AVR32EB28 TCF0 registers The 11 registers of TCF0 (24-bit Timer/Counter for frequency generation), from 0xC00, with their reset value and every field. The AVR32EB28 has 423 registers in 40 peripherals, one page each.
TCF0 24-bit Timer/Counter for frequency generation CTRLAControl A
Address 0xC00
Reset 0x00
Access read/write 7 RUNSTDBY 6 – 5 – 4 – 3 PRESC2 2 PRESC1 1 PRESC0 0 ENABLE 3 fields
Field Bits What it does RUNSTDBY 7 Run Standby PRESC 3:1 Clock Prescaler0 Runs directly on Clock Source1 Divide clock source by 22 Divide clock source by 43 Divide clock source by 84 Divide clock source by 165 Divide clock source by 326 Divide clock source by 647 Divide clock source by 128 ENABLE 0 Enable
CTRLBControl B
Address 0xC01
Reset 0x00
Access read/write 7 CMP1EV 6 CMP0EV 5 CLKSEL2 4 CLKSEL1 3 CLKSEL0 2 WGMODE2 1 WGMODE1 0 WGMODE0 4 fields
Field Bits What it does CMP1EV 7 Compare 1 Event Generation0 Event is generated as pulse1 Waveform is used as event output CMP0EV 6 Compare 0 Event Generation0 Event is generated as pulse1 Waveform is used as event output CLKSEL 5:3 Clock Select0 Peripheral Clock1 Event as clock source2 Internal High Frequency Oscillator3 Internal 32.768 kHz Oscillator5 PLL WGMODE 2:0 Waveform Generation Mode0 Frequency1 Numerically Controlled Oscillator Pulse-Frequency2 Numerically Controlled Oscillator Fixed Duty Cycle7 8-bit PWM
CTRLCControl C
Address 0xC02
Reset 0x00
Access read/write 7 – 6 WGPULSE2 5 WGPULSE1 4 WGPULSE0 3 WO1POL 2 WO0POL 1 WO1EN 0 WO0EN 5 fields
Field Bits What it does WGPULSE 6:4 Waveform Generation Pulse Length0 High pulse duration is 1 clock period1 High pulse duration is 2 clock period2 High pulse duration is 4 clock period3 High pulse duration is 8 clock period4 High pulse duration is 16 clock period5 High pulse duration is 32 clock period6 High pulse duration is 64 clock period7 High pulse duration is 128 clock period WO1POL 3 Waveform Output 1 Polarity0 Waveform output set on update and cleared on match1 Waveform output cleared on update and set on match WO0POL 2 Waveform Output 0 Polarity0 Waveform output set on update and cleared on match1 Waveform output cleared on update and set on match WO1EN 1 Waveform Output 1 Enable WO0EN 0 Waveform Output 0 Enable
CTRLDControl D
Address 0xC03
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 CMD1 0 CMD0 1 field
Field Bits What it does CMD 1:0 Command0 No command1 Force update2 Force restart
EVCTRLEvent Control
Address 0xC04
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 FILTERA 2 EVACTA1 1 EVACTA0 0 CNTAEI 3 fields
Field Bits What it does FILTERA 3 Event A Filter EVACTA 2:1 Event Action A0 Restart Counter1 Mask waveform output to '0' CNTAEI 0 Event A Input Enable
INTCTRLInterrupt Control
Address 0xC05
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 CMP1 1 CMP0 0 OVF 3 fields
Field Bits What it does CMP1 2 Compare 1 Interrupt Enable CMP0 1 Compare 0 Interrupt Enable OVF 0 Overflow
INTFLAGSInterrupt Flags
Address 0xC06
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 CMP1 1 CMP0 0 OVF 3 fields
Field Bits What it does CMP1 2 Compare 1 Flag CMP0 1 Compare 0 Flag OVF 0 Overflow Flag
STATUSStatus
Address 0xC07
Reset 0x00
Access read only 7 CMP1BUSY 6 CMP0BUSY 5 PERBUSY 4 CNTBUSY 3 CTRLDBUSY 2 CTRLCBUSY 1 CTRLABUSY 0 – 7 fields
Field Bits What it does CMP1BUSY 7 Compare 1 Synchronization Busy CMP0BUSY 6 Compare 0 Synchronization Busy PERBUSY 5 Period Synchronization Busy CNTBUSY 4 Counter Synchronization Busy CTRLDBUSY 3 Control D Synchronization Busy CTRLCBUSY 2 Control B Synchronization Busy CTRLABUSY 1 Control A Synchronization Busy
DBGCTRLDebug Control
Address 0xC0D
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 DBGRUN 1 field
Field Bits What it does DBGRUN 0 Debug Run
CNTCount
Address 0xC10
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CNT 23:0 Counter
CMPCompare
Address 0xC14
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CMP 23:0 Compare
BETA