AVR32SD20 RTC registers

The 16 registers of RTC (Real-Time Counter), from 0x140, with their reset value and every field. The AVR32SD20 has 580 registers in 51 peripherals, one page each.

RTC Real-Time Counter

CTRLAControl A

Address
0x140
Reset
0x00
Access
read/write
  1. 7RUNSTDBY
  2. 6PRESCALER3
  3. 5PRESCALER2
  4. 4PRESCALER1
  5. 3PRESCALER0
  6. 2–
  7. 1–
  8. 0RTCEN
3 fields
FieldBitsWhat it does
RUNSTDBY7Run In Standby
PRESCALER6:3Prescaling Factor
  • 0 RTC Clock / 1
  • 1 RTC Clock / 2
  • 2 RTC Clock / 4
  • 3 RTC Clock / 8
  • 4 RTC Clock / 16
  • 5 RTC Clock / 32
  • 6 RTC Clock / 64
  • 7 RTC Clock / 128
  • 8 RTC Clock / 256
  • 9 RTC Clock / 512
  • 10 RTC Clock / 1024
  • 11 RTC Clock / 2048
  • 12 RTC Clock / 4096
  • 13 RTC Clock / 8192
  • 14 RTC Clock / 16384
  • 15 RTC Clock / 32768
RTCEN0Enable

STATUSStatus

Address
0x141
Reset
0x00
Access
read only
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3CMPBUSY
  6. 2PERBUSY
  7. 1CNTBUSY
  8. 0CTRLABUSY
4 fields
FieldBitsWhat it does
CMPBUSY3Comparator Synchronization Busy Flag
PERBUSY2Period Synchronization Busy Flag
CNTBUSY1Count Synchronization Busy Flag
CTRLABUSY0CTRLA Synchronization Busy Flag

INTCTRLInterrupt Control

Address
0x142
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1CMP
  8. 0OVF
2 fields
FieldBitsWhat it does
CMP1Compare Match Interrupt enable
OVF0Overflow Interrupt enable

INTFLAGSInterrupt Flags

Address
0x143
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1CMP
  8. 0OVF
2 fields
FieldBitsWhat it does
CMP1Compare Match Interrupt
OVF0Overflow Interrupt Flag

TEMPTemporary

Address
0x144
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0–

DBGCTRLDebug control

Address
0x145
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0DBGRUN
1 field
FieldBitsWhat it does
DBGRUN0Run in debug

CLKSELClock Select

Address
0x147
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1CLKSEL1
  8. 0CLKSEL0
1 field
FieldBitsWhat it does
CLKSEL1:0Clock Select
  • 0 32.768 kHz from OSC32K
  • 1 1.024 kHz from OSC32K
  • 2 32.768 kHz from XOSC32K or external clock from XTAL32K1 pin
  • 3 External clock from XOSCHF or external clock from the XTALHF1 pin

CNTCounter

Address
0x148
Reset
0x0000
Access
read/write
Size
16-bit

PERPeriod

Address
0x14A
Reset
0xFFFF
Access
read/write
Size
16-bit

CMPCompare

Address
0x14C
Reset
0x0000
Access
read/write
Size
16-bit

PITCTRLAPIT Control A

Address
0x150
Reset
0x00
Access
read/write
  1. 7–
  2. 6PERIOD3
  3. 5PERIOD2
  4. 4PERIOD1
  5. 3PERIOD0
  6. 2–
  7. 1–
  8. 0PITEN
2 fields
FieldBitsWhat it does
PERIOD6:3Period
  • 0 Off
  • 1 RTC Clock Cycles 4
  • 2 RTC Clock Cycles 8
  • 3 RTC Clock Cycles 16
  • 4 RTC Clock Cycles 32
  • 5 RTC Clock Cycles 64
  • 6 RTC Clock Cycles 128
  • 7 RTC Clock Cycles 256
  • 8 RTC Clock Cycles 512
  • 9 RTC Clock Cycles 1024
  • 10 RTC Clock Cycles 2048
  • 11 RTC Clock Cycles 4096
  • 12 RTC Clock Cycles 8192
  • 13 RTC Clock Cycles 16384
  • 14 RTC Clock Cycles 32768
PITEN0Enable

PITSTATUSPIT Status

Address
0x151
Reset
0x00
Access
read only
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0CTRLBUSY
1 field
FieldBitsWhat it does
CTRLBUSY0CTRLA Synchronization Busy Flag

PITINTCTRLPIT Interrupt Control

Address
0x152
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0PI
1 field
FieldBitsWhat it does
PI0Periodic Interrupt

PITINTFLAGSPIT Interrupt Flags

Address
0x153
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0PI
1 field
FieldBitsWhat it does
PI0Periodic Interrupt

PITDBGCTRLPIT Debug control

Address
0x155
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0DBGRUN
1 field
FieldBitsWhat it does
DBGRUN0Run in debug

PITEVGENCTRLAPIT Event Generation Control A

Address
0x156
Reset
0x00
Access
read/write
  1. 7EVGEN1SEL3
  2. 6EVGEN1SEL2
  3. 5EVGEN1SEL1
  4. 4EVGEN1SEL0
  5. 3EVGEN0SEL3
  6. 2EVGEN0SEL2
  7. 1EVGEN0SEL1
  8. 0EVGEN0SEL0
2 fields
FieldBitsWhat it does
EVGEN1SEL7:4Event Generation 1 Select
  • 0 No Event Generated
  • 1 CLK_RTC divided by 4
  • 2 CLK_RTC divided by 8
  • 3 CLK_RTC divided by 16
  • 4 CLK_RTC divided by 32
  • 5 CLK_RTC divided by 64
  • 6 CLK_RTC divided by 128
  • 7 CLK_RTC divided by 256
  • 8 CLK_RTC divided by 512
  • 9 CLK_RTC divided by 1024
  • 10 CLK_RTC divided by 2048
  • 11 CLK_RTC divided by 4096
  • 12 CLK_RTC divided by 8192
  • 13 CLK_RTC divided by 16384
  • 14 CLK_RTC divided by 32768
EVGEN0SEL3:0Event Generation 0 Select
  • 0 No Event Generated
  • 1 CLK_RTC divided by 4
  • 2 CLK_RTC divided by 8
  • 3 CLK_RTC divided by 16
  • 4 CLK_RTC divided by 32
  • 5 CLK_RTC divided by 64
  • 6 CLK_RTC divided by 128
  • 7 CLK_RTC divided by 256
  • 8 CLK_RTC divided by 512
  • 9 CLK_RTC divided by 1024
  • 10 CLK_RTC divided by 2048
  • 11 CLK_RTC divided by 4096
  • 12 CLK_RTC divided by 8192
  • 13 CLK_RTC divided by 16384
  • 14 CLK_RTC divided by 32768